Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156598
R. Kertis, K. Fitzpatrick, Yu-Pin Han
A 256K NMOS PRAM with a typical read access time of 5911s after RAS at 80 C and at 4.5V, (Figure 1 ) will be described. Page mode read and write cycles at tester-limited cycle rates of 55ns have been achieved; Figure 2. One key element in achieving this performance was a triplediffused LD3 NMOS transistor structure, a combination of a double-diffused lightly-doped phosphorus junction, surrounded by a halo of boron, and a deep arsenic-diffused heavily-doped junction as the sonrce/drain junction. The structure is similar to the double implanted structure reported earlier', with the following characteristics: N+ junction can be independently driven deep to reduce the parasitic resistance; the Njunction length, depth, and doping concentration can be adjusted according to their needs; the gate to source/drain overlap capacitance is small; boron halo, together with a channel implant control the Vt and provide compensation of the short channel Vt falloff, and the lightly-doped drain provides significantly reduced impact ionization. A second element of the circuit is the use of a two-level metal interconnect system. The additional level of low-resistance interconnect allows both the bit lines and word lines to have minimal transient delays. Double level metal also provides a good power bussing network in the periphery.
{"title":"A 59ns 256K DRAM using LD3technology and double level metal","authors":"R. Kertis, K. Fitzpatrick, Yu-Pin Han","doi":"10.1109/ISSCC.1984.1156598","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156598","url":null,"abstract":"A 256K NMOS PRAM with a typical read access time of 5911s after RAS at 80 C and at 4.5V, (Figure 1 ) will be described. Page mode read and write cycles at tester-limited cycle rates of 55ns have been achieved; Figure 2. One key element in achieving this performance was a triplediffused LD3 NMOS transistor structure, a combination of a double-diffused lightly-doped phosphorus junction, surrounded by a halo of boron, and a deep arsenic-diffused heavily-doped junction as the sonrce/drain junction. The structure is similar to the double implanted structure reported earlier', with the following characteristics: N+ junction can be independently driven deep to reduce the parasitic resistance; the Njunction length, depth, and doping concentration can be adjusted according to their needs; the gate to source/drain overlap capacitance is small; boron halo, together with a channel implant control the Vt and provide compensation of the short channel Vt falloff, and the lightly-doped drain provides significantly reduced impact ionization. A second element of the circuit is the use of a two-level metal interconnect system. The additional level of low-resistance interconnect allows both the bit lines and word lines to have minimal transient delays. Double level metal also provides a good power bussing network in the periphery.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124572240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156593
S. Shimizu, Y. Kamatani, N. Toyoda, K. Kanazawa, M. Mochizuki, T. Terada, A. Hojo
DUAL MODULUS BIPOLAR ECL CIRCUIT ICs have been widely used in phase locked loop (PLL) synthesizer systems. Representative applications have been in the automoble telephone or in transceivers, where low power consumption is required, because of battery operation. Accordingly, commercially available Si ECL divider ICs are not satisfactory; the lowest power consumption available is 150mW2. Gallium arsenide divider ICs, which can operate at less power consumption, are thus promising for such applications. Among the GaAs logic circuits, the Direct Coupled FET Logic (DCFL) is the most attractive for its power consumption feature. However, at present, it is questionable whether the DCFL is practical for commercial products, because of its small noise margin and process sensitivity. The GaAs Source Coupled FET Logic (SCFL)’ basic gate circuit employs a differential pair of FETs. Therefore, merely threshold voltage pairing of differentially-connected FETs is required for normal operation. Consequently, a higher chip yield can be expected.
{"title":"A 1GHz 50mW dual modulus divider IC using source coupled FET logic","authors":"S. Shimizu, Y. Kamatani, N. Toyoda, K. Kanazawa, M. Mochizuki, T. Terada, A. Hojo","doi":"10.1109/ISSCC.1984.1156593","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156593","url":null,"abstract":"DUAL MODULUS BIPOLAR ECL CIRCUIT ICs have been widely used in phase locked loop (PLL) synthesizer systems. Representative applications have been in the automoble telephone or in transceivers, where low power consumption is required, because of battery operation. Accordingly, commercially available Si ECL divider ICs are not satisfactory; the lowest power consumption available is 150mW2. Gallium arsenide divider ICs, which can operate at less power consumption, are thus promising for such applications. Among the GaAs logic circuits, the Direct Coupled FET Logic (DCFL) is the most attractive for its power consumption feature. However, at present, it is questionable whether the DCFL is practical for commercial products, because of its small noise margin and process sensitivity. The GaAs Source Coupled FET Logic (SCFL)’ basic gate circuit employs a differential pair of FETs. Therefore, merely threshold voltage pairing of differentially-connected FETs is required for normal operation. Consequently, a higher chip yield can be expected.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124688624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156594
K. Nishiuchi, N. Kobayashi, S. Kuroda, S. Notomi, T. Nimura, M. Abe, M. Kobayashi
HIGH-SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT)’ is felt to be applicable for high-speed logic operations. This paper will report on the design of a I K x l b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1 . 5 ~ gate devices, and 3pm line process. The memory cell size measures 55 x 3 9 p , and the chip size is 3.0 x 2.9mm. Address access time of 0.911s and an operating power of 360mW at liquid nitrogen temperature have been obtained. A photomicrograph of the RAM is shown in Figure 1. The RAM is organized into 1024 word x lb , and arranged as a 32 x 32 matrix. Using a depletion type HEMT for load devices, E/D type DCFL circuits were employed as the basic circuit. The memory cell is a 6-transistor cross-coupled flipflop circuit with switching devices having gate lengths of 2.Opm. For peripheral circuits, 1 . 5 p gate switching device was chosen for performance reasons, and long gate devices were used as load devices. The circuit diagram of the RAM is shown in Figure 2. To obtain a high-speed operation, sufficiently large operating current was assigned to peripheral circuits, especially to the address buffer, word driver, and output buffer which have large wiring capacitances. As a result, the entire peripheral circuit which has 15% of the total device count, dissipates 85% of the chip dissipation power. As seen in Figure 1, the total area of the peripheral circuits is same as the cell array. But no particular power-down technique was employed in this design. A differential amplifier type sensing circuit and a bit line pull-up scheme were adopted to fetch data in short time from the low power memory cell. To drive large off-chip capacitance quickly, a four-stage output buffer amplifier was used with a final stage of a push-pull type output circuit constructed of high-current enhancement type devices. To obtain
{"title":"A subnanosecond HEMT 1Kb SRAM","authors":"K. Nishiuchi, N. Kobayashi, S. Kuroda, S. Notomi, T. Nimura, M. Abe, M. Kobayashi","doi":"10.1109/ISSCC.1984.1156594","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156594","url":null,"abstract":"HIGH-SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT)’ is felt to be applicable for high-speed logic operations. This paper will report on the design of a I K x l b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1 . 5 ~ gate devices, and 3pm line process. The memory cell size measures 55 x 3 9 p , and the chip size is 3.0 x 2.9mm. Address access time of 0.911s and an operating power of 360mW at liquid nitrogen temperature have been obtained. A photomicrograph of the RAM is shown in Figure 1. The RAM is organized into 1024 word x lb , and arranged as a 32 x 32 matrix. Using a depletion type HEMT for load devices, E/D type DCFL circuits were employed as the basic circuit. The memory cell is a 6-transistor cross-coupled flipflop circuit with switching devices having gate lengths of 2.Opm. For peripheral circuits, 1 . 5 p gate switching device was chosen for performance reasons, and long gate devices were used as load devices. The circuit diagram of the RAM is shown in Figure 2. To obtain a high-speed operation, sufficiently large operating current was assigned to peripheral circuits, especially to the address buffer, word driver, and output buffer which have large wiring capacitances. As a result, the entire peripheral circuit which has 15% of the total device count, dissipates 85% of the chip dissipation power. As seen in Figure 1, the total area of the peripheral circuits is same as the cell array. But no particular power-down technique was employed in this design. A differential amplifier type sensing circuit and a bit line pull-up scheme were adopted to fetch data in short time from the low power memory cell. To drive large off-chip capacitance quickly, a four-stage output buffer amplifier was used with a final stage of a push-pull type output circuit constructed of high-current enhancement type devices. To obtain","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156669
P. Rosini, R. Finaurini, M. Gaibotti
An 8b single chip microprocessor with a memory containing 32Kb of ROM, 512b of RAM and 512b of nonvolatile SRAM, implemented in 4μm double poly floating gate technology, will be described.
{"title":"A 5V-only single chip microcomputer with nonvolatile SRAM","authors":"P. Rosini, R. Finaurini, M. Gaibotti","doi":"10.1109/ISSCC.1984.1156669","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156669","url":null,"abstract":"An 8b single chip microprocessor with a memory containing 32Kb of ROM, 512b of RAM and 512b of nonvolatile SRAM, implemented in 4μm double poly floating gate technology, will be described.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128259644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156670
M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga
A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.
{"title":"A CMOS 12K gate array with flexible 10Kb memory","authors":"M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga","doi":"10.1109/ISSCC.1984.1156670","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156670","url":null,"abstract":"A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127499573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156715
J. Pfiester, J. Shott, J. Meindl
An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.
{"title":"Performance limits of NMOS and CMOS","authors":"J. Pfiester, J. Shott, J. Meindl","doi":"10.1109/ISSCC.1984.1156715","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156715","url":null,"abstract":"An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126265682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156589
B. Gilbert
A fully-parallel 16-channel analog array processor for concurrent signal normalization in pattern recognition applications will be described. Using a standard monolithic bipolar process the chip consumes 1mW, provides a 1MHz bandwidth and unlimited channel-expansion facilities.
{"title":"An analog array processor","authors":"B. Gilbert","doi":"10.1109/ISSCC.1984.1156589","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156589","url":null,"abstract":"A fully-parallel 16-channel analog array processor for concurrent signal normalization in pattern recognition applications will be described. Using a standard monolithic bipolar process the chip consumes 1mW, provides a 1MHz bandwidth and unlimited channel-expansion facilities.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156601
K. Yang, K. Smits, E. Haq, M. Embrathiry, A. Varadi
USING CONVENTIONAL PROCESSING techniques, a DRAM cell utilizing almost the entire cell area for the storage capacitor, has been developed. Thus, even with 300adielectric material, the storage capacitance has been found to provide improved results over prcviously reported 256K DRAM cell^"^'^. And without using s i l i ~ i d e s ~ ’ ~ ’ ~ double metal process2 or multiple row decoders4, upgraded performance has been possible. The layout of the cell is shown in Figure 1. Buried diffused bit lines are formed by an additional masking step that enables the bit lines to be implanted and oxidized prior to the deposition of Poly 1 and normal source/ drain implant. Poly 1 word lines form access transistors at areas where Poly 1 and active areas overlap with no bit line implant. In this manner Poly 1 word lines are able to cross buried bit lines without forming transistors. Poly 1 also forms transistors for the peripheral circuitry. Storage capacitor plates are formed by Poly 2 and Poly 3. The Poly 2 plate is connected to the sourcc of the access transistor by means of a buried contact. Since the Poly 2 capacitor plates lie on top of the word lines, bit lines, and access transistors, they can occupy the entire cell area. The only limitation is the physical spacing between adjacent capacitors. The common terminal for all storage capacitors is a sheet of Poly 3 covering the entire cell area. Metal lines are used to connect Poly 1 word lines outside the memory cell areas and only at desired intervals.
{"title":"Triple poly II DRAM memory cell","authors":"K. Yang, K. Smits, E. Haq, M. Embrathiry, A. Varadi","doi":"10.1109/ISSCC.1984.1156601","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156601","url":null,"abstract":"USING CONVENTIONAL PROCESSING techniques, a DRAM cell utilizing almost the entire cell area for the storage capacitor, has been developed. Thus, even with 300adielectric material, the storage capacitance has been found to provide improved results over prcviously reported 256K DRAM cell^\"^'^. And without using s i l i ~ i d e s ~ ’ ~ ’ ~ double metal process2 or multiple row decoders4, upgraded performance has been possible. The layout of the cell is shown in Figure 1. Buried diffused bit lines are formed by an additional masking step that enables the bit lines to be implanted and oxidized prior to the deposition of Poly 1 and normal source/ drain implant. Poly 1 word lines form access transistors at areas where Poly 1 and active areas overlap with no bit line implant. In this manner Poly 1 word lines are able to cross buried bit lines without forming transistors. Poly 1 also forms transistors for the peripheral circuitry. Storage capacitor plates are formed by Poly 2 and Poly 3. The Poly 2 plate is connected to the sourcc of the access transistor by means of a buried contact. Since the Poly 2 capacitor plates lie on top of the word lines, bit lines, and access transistors, they can occupy the entire cell area. The only limitation is the physical spacing between adjacent capacitors. The common terminal for all storage capacitors is a sheet of Poly 3 covering the entire cell area. Metal lines are used to connect Poly 1 word lines outside the memory cell areas and only at desired intervals.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"64 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156576
G. Madland
The phenomenal progress of the solid-state technologies, which have surfaced as a global resource, achieved in over three decades of pacesetting advancements, reflects the unique spirited creativity of not only engineers and scientists, but the strong alliance of those skilled in management. Today, the sophisticated development excitement continues, with multifaceted chips affording dramatic results. But the complex composition features, with its unlimited application potentials, have spun off a widening range of strategic planning concerns, not only in the expanded need for new procedures in designing and processing, but on the evolving demographic scene. Legislators, legal specialists, international trade authorities, personnel and financial spokesmen, will now be obliged to participate in an even more energetic way in meeting the challenging demands of burgeaning problems ahead to insure progress and stability. A positive program of providing technology on a worldwide basis would, with time, develop new markets and improved international understanding. The role of our industry and the expected participation by the engineering community will be assessed.
{"title":"A positive program for world cooperation","authors":"G. Madland","doi":"10.1109/ISSCC.1984.1156576","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156576","url":null,"abstract":"The phenomenal progress of the solid-state technologies, which have surfaced as a global resource, achieved in over three decades of pacesetting advancements, reflects the unique spirited creativity of not only engineers and scientists, but the strong alliance of those skilled in management. Today, the sophisticated development excitement continues, with multifaceted chips affording dramatic results. But the complex composition features, with its unlimited application potentials, have spun off a widening range of strategic planning concerns, not only in the expanded need for new procedures in designing and processing, but on the evolving demographic scene. Legislators, legal specialists, international trade authorities, personnel and financial spokesmen, will now be obliged to participate in an even more energetic way in meeting the challenging demands of burgeaning problems ahead to insure progress and stability. A positive program of providing technology on a worldwide basis would, with time, develop new markets and improved international understanding. The role of our industry and the expected participation by the engineering community will be assessed.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156608
A. Avanessians, E. Beck, G. Corcoran, I. Eldumiati, J. Elward, A. Glaser, R. Irving, R. Spiwak, R. Wiederhold
THIS PAPER WILL DISCUSS an IC that performs complete link-level control according to a communication protocol that is a superset of the CCITT X.25 level 2 LAPB protocol because it includes the exchange identification frames. In addition to the standard modulo 8 frame sequencing and 16b CRC error detection method set forth by the protocol, the circuit affords a programmable window size (K) comparator, programmable information field length (Nl) and retransmission (N2) counters, and four programmable link assurance timers (T1 through T4). The IC automatically maintains the link by handling supervisory and unnumbered frames without user intervention, interrupting the host CPU only when it requires attention. Typical interrupts are transmitted block acknowledged and packet received: these inform the host that data in the buffers (defined during set up) has been sent or received and require user attention. Other interrupts inform the user of the physical link status. The interface between the IC and the physical link layer (level 1 ) consists of seven signals: request-to-send, clear-to-send, transmit data, received data, transmit clock, receive clock, and receiver carrier detect. These signals assume the usual RS-232 definitions. Finally, a DMA is used to support the circuit to host interface. The host defines regions of memory for the IC wherein i t sets up transmit data buffers, receive data buffers, and buffer management tables. The host is able to monitor the management tables to aid in the transfer of data to and from the data buffers. The circuit consists of a transmitter, receiver, main controller, and interface unit as shown in Figure 1. These four components are essentially independent and loosely coupled. The transmitter and receiver handle low-level aspects of the protocol such as flag generation and detection, zero-bit insertion and deletion, and CRC generation and checking. In addition, the receiver is required to identify and classify all incoming frames so that the main controller can queue and transmit the appropriate responses. A three-channel DMA and interrupt circuit form the heart of the user interface. Both the transmitter and receiver have their own DMA channel to transfer data to and from local memory. The third channel automatically maintains the buffer management tables. With the interrupt handler, it is possible to prioritize and inhibit interrupt collisions generated by the various sections of the chip. 1
{"title":"A VLSI link-level controller","authors":"A. Avanessians, E. Beck, G. Corcoran, I. Eldumiati, J. Elward, A. Glaser, R. Irving, R. Spiwak, R. Wiederhold","doi":"10.1109/ISSCC.1984.1156608","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156608","url":null,"abstract":"THIS PAPER WILL DISCUSS an IC that performs complete link-level control according to a communication protocol that is a superset of the CCITT X.25 level 2 LAPB protocol because it includes the exchange identification frames. In addition to the standard modulo 8 frame sequencing and 16b CRC error detection method set forth by the protocol, the circuit affords a programmable window size (K) comparator, programmable information field length (Nl) and retransmission (N2) counters, and four programmable link assurance timers (T1 through T4). The IC automatically maintains the link by handling supervisory and unnumbered frames without user intervention, interrupting the host CPU only when it requires attention. Typical interrupts are transmitted block acknowledged and packet received: these inform the host that data in the buffers (defined during set up) has been sent or received and require user attention. Other interrupts inform the user of the physical link status. The interface between the IC and the physical link layer (level 1 ) consists of seven signals: request-to-send, clear-to-send, transmit data, received data, transmit clock, receive clock, and receiver carrier detect. These signals assume the usual RS-232 definitions. Finally, a DMA is used to support the circuit to host interface. The host defines regions of memory for the IC wherein i t sets up transmit data buffers, receive data buffers, and buffer management tables. The host is able to monitor the management tables to aid in the transfer of data to and from the data buffers. The circuit consists of a transmitter, receiver, main controller, and interface unit as shown in Figure 1. These four components are essentially independent and loosely coupled. The transmitter and receiver handle low-level aspects of the protocol such as flag generation and detection, zero-bit insertion and deletion, and CRC generation and checking. In addition, the receiver is required to identify and classify all incoming frames so that the main controller can queue and transmit the appropriate responses. A three-channel DMA and interrupt circuit form the heart of the user interface. Both the transmitter and receiver have their own DMA channel to transfer data to and from local memory. The third channel automatically maintains the buffer management tables. With the interrupt handler, it is possible to prioritize and inhibit interrupt collisions generated by the various sections of the chip. 1","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122443342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：