Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156662
S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos
A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm2two-transistor cell and 33100 mil2die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.
采用1.5μm n阱CMOS on epi技术的5V-only 64Kb EEROM，具有85μ m22的双晶体管电池和33100 mil2的芯片面积。地址边缘检测电路技术在50mW有功功耗下实现了100ns的典型访问时间。
{"title":"A 64Kb CMOS EEROM with on-chip ECC","authors":"S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos","doi":"10.1109/ISSCC.1984.1156662","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156662","url":null,"abstract":"A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm<sup>2</sup>two-transistor cell and 33100 mil<sup>2</sup>die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156566
M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura
This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.
{"title":"Facsimile shading corrector","authors":"M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura","doi":"10.1109/ISSCC.1984.1156566","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156566","url":null,"abstract":"This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128034703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156716
M. Degrauwe, W. Sansen
A program, developed for transconductance operational amplifiers systems, to synthesize static, dynamic and adaptive biasing amplifiers in a 5μm CMOS process, will be presented. Yields of ≥60dB gain, phase margin>45°with 10pF load and a slow rate ≤1V/μs have been obtained.
{"title":"A synthesis program for operation amplifiers","authors":"M. Degrauwe, W. Sansen","doi":"10.1109/ISSCC.1984.1156716","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156716","url":null,"abstract":"A program, developed for transconductance operational amplifiers systems, to synthesize static, dynamic and adaptive biasing amplifiers in a 5μm CMOS process, will be presented. Yields of ≥60dB gain, phase margin<tex>>45°</tex>with 10pF load and a slow rate ≤1V/μs have been obtained.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156704
A. Takla, Y. Haque
This report will cover a 300-baud frequency shift keying MODEM, including a handshaking interface integrated in a 5μm CMOS technology.
本报告将介绍一个300波特频移键控调制解调器，包括一个集成在5μm CMOS技术中的握手接口。
{"title":"A 300-baud frequency shift keying MODEM","authors":"A. Takla, Y. Haque","doi":"10.1109/ISSCC.1984.1156704","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156704","url":null,"abstract":"This report will cover a 300-baud frequency shift keying MODEM, including a handshaking interface integrated in a 5μm CMOS technology.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156703
T. Ozawa, S. Koshimaru, O. Kudo, H. Itoh, N. Harashima, N. Yasuoka, H. Asai, T. Yamanaka, S. Kikuchi
A 25ns 64K×1 CMOS SRAM with a 30.9mm2chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.
{"title":"A 25ns 64K SRAM","authors":"T. Ozawa, S. Koshimaru, O. Kudo, H. Itoh, N. Harashima, N. Yasuoka, H. Asai, T. Yamanaka, S. Kikuchi","doi":"10.1109/ISSCC.1984.1156703","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156703","url":null,"abstract":"A 25ns 64K×1 CMOS SRAM with a 30.9mm<sup>2</sup>chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115358095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156693
R. Dutton
The testing problem may dominate cost and even design time for VLSI. Testing at both the system and chip levels will be addressed, stressing the procedures that could be required for full custom versus array-based approaches . . . To be considered too will be the integration of test capability directly on to the chip, and the interface relationships of the designer, producer and test source . . . The techniques which have been successful for MSI and LSI(path scans-LSSD/auto mated test Pattern generation) are likely to fail or have limited applicability for VLSI . . .On-chip testing strategies (self testing of on-board or other macros) may supercede global strategies, such as LSSD...Other equipment and areas that could be involved include the E-beam, and process evaluation and yield maximization testing which may be more appropriate than go/no-go on-board procedures . . .The role of university and education, related to testing and testability, will also be appraised by the panelists.
{"title":"Testing methodology for VLSI","authors":"R. Dutton","doi":"10.1109/ISSCC.1984.1156693","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156693","url":null,"abstract":"The testing problem may dominate cost and even design time for VLSI. Testing at both the system and chip levels will be addressed, stressing the procedures that could be required for full custom versus array-based approaches . . . To be considered too will be the integration of test capability directly on to the chip, and the interface relationships of the designer, producer and test source . . . The techniques which have been successful for MSI and LSI(path scans-LSSD/auto mated test Pattern generation) are likely to fail or have limited applicability for VLSI . . .On-chip testing strategies (self testing of on-board or other macros) may supercede global strategies, such as LSSD...Other equipment and areas that could be involved include the E-beam, and process evaluation and yield maximization testing which may be more appropriate than go/no-go on-board procedures . . .The role of university and education, related to testing and testability, will also be appraised by the panelists.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115615069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156620
N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada
This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.
{"title":"A 16ns 2K×8b CMOS SRAM","authors":"N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada","doi":"10.1109/ISSCC.1984.1156620","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156620","url":null,"abstract":"This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115323495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156600
M. Taguchi, S. Audo, S. Hijiya, T. Nakamura, S. Economo, T. Yabu
CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __
{"title":"A capacitance coupled bit line cell for Mb level DRAMs","authors":"M. Taguchi, S. Audo, S. Hijiya, T. Nakamura, S. Economo, T. Yabu","doi":"10.1109/ISSCC.1984.1156600","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156600","url":null,"abstract":"CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156674
A. Komori, M. Furukawa, T. Sato, T. Komazaki
This paper will discuss subscriber loop transceivers designed for loop loss in excess of 42dB at 200Kb/s, Switched Capacitor filters for thesqrt{f}AGC and digital analog techniques for the bridged tap equalizer will also be covered.
{"title":"A 200Kb/s burst mode transceiver with two-bridge tap equalizer","authors":"A. Komori, M. Furukawa, T. Sato, T. Komazaki","doi":"10.1109/ISSCC.1984.1156674","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156674","url":null,"abstract":"This paper will discuss subscriber loop transceivers designed for loop loss in excess of 42dB at 200Kb/s, Switched Capacitor filters for thesqrt{f}AGC and digital analog techniques for the bridged tap equalizer will also be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121065000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156606
H. Bakoglu, J. Meindl
{"title":"Optimal interconnect circuits for VLSI","authors":"H. Bakoglu, J. Meindl","doi":"10.1109/ISSCC.1984.1156606","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156606","url":null,"abstract":"","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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