Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156662
S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos
A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm2two-transistor cell and 33100 mil2die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.
采用1.5μm n阱CMOS on epi技术的5V-only 64Kb EEROM，具有85μ m22的双晶体管电池和33100 mil2的芯片面积。地址边缘检测电路技术在50mW有功功耗下实现了100ns的典型访问时间。
{"title":"A 64Kb CMOS EEROM with on-chip ECC","authors":"S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos","doi":"10.1109/ISSCC.1984.1156662","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156662","url":null,"abstract":"A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm<sup>2</sup>two-transistor cell and 33100 mil<sup>2</sup>die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156566
M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura
This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.
{"title":"Facsimile shading corrector","authors":"M. Togashi, S. Sato, S. Ohshima, K. Aruga, T. Nakamura","doi":"10.1109/ISSCC.1984.1156566","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156566","url":null,"abstract":"This paper will cover a 5.7mm × 5.73mm chip with 9000 transistors using 3μm CMOS technology and a dissipation of 200mW. The processor incorporates an on-chip 6b parallel ADC and achieves 3% correction accuracy at a 1MHz conversion rate.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128034703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156716
M. Degrauwe, W. Sansen
A program, developed for transconductance operational amplifiers systems, to synthesize static, dynamic and adaptive biasing amplifiers in a 5μm CMOS process, will be presented. Yields of ≥60dB gain, phase margin>45°with 10pF load and a slow rate ≤1V/μs have been obtained.
{"title":"A synthesis program for operation amplifiers","authors":"M. Degrauwe, W. Sansen","doi":"10.1109/ISSCC.1984.1156716","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156716","url":null,"abstract":"A program, developed for transconductance operational amplifiers systems, to synthesize static, dynamic and adaptive biasing amplifiers in a 5μm CMOS process, will be presented. Yields of ≥60dB gain, phase margin<tex>>45°</tex>with 10pF load and a slow rate ≤1V/μs have been obtained.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156704
A. Takla, Y. Haque
This report will cover a 300-baud frequency shift keying MODEM, including a handshaking interface integrated in a 5μm CMOS technology.
本报告将介绍一个300波特频移键控调制解调器，包括一个集成在5μm CMOS技术中的握手接口。
{"title":"A 300-baud frequency shift keying MODEM","authors":"A. Takla, Y. Haque","doi":"10.1109/ISSCC.1984.1156704","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156704","url":null,"abstract":"This report will cover a 300-baud frequency shift keying MODEM, including a handshaking interface integrated in a 5μm CMOS technology.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156643
Y. Fujita, E. Masuda, S. Sakamoto, T. Sakaue, Y. Sato
A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.
{"title":"A bulk CMOS 20MS/s 7b flash ADC","authors":"Y. Fujita, E. Masuda, S. Sakamoto, T. Sakaue, Y. Sato","doi":"10.1109/ISSCC.1984.1156643","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156643","url":null,"abstract":"A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134288758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156603
S. Pope, B. Solberg, R. Brodersen
A DIGITAL MOS-LSI circuit which implements a full-duplcx speech analysis/synthcsis system will be reported. This vocodcr IC analyzes speech in realtime, generating a low-bit-rate digital data stream suitable for transmission or storage. Simultaneously, syntllesized spccch can be generated from an incoming data stream. Vocoders transmit two types of informalion: spectral parameters and excitation parameters. The vocodcr IC uses linear predictive coding(LPC) to reprcsent the spectrum. The excitation is represented by its energy, a voiced/unvoiced decision, and the period of the pitch fundamental.
{"title":"A single chip LPC vocoder","authors":"S. Pope, B. Solberg, R. Brodersen","doi":"10.1109/ISSCC.1984.1156603","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156603","url":null,"abstract":"A DIGITAL MOS-LSI circuit which implements a full-duplcx speech analysis/synthcsis system will be reported. This vocodcr IC analyzes speech in realtime, generating a low-bit-rate digital data stream suitable for transmission or storage. Simultaneously, syntllesized spccch can be generated from an incoming data stream. Vocoders transmit two types of informalion: spectral parameters and excitation parameters. The vocodcr IC uses linear predictive coding(LPC) to reprcsent the spectrum. The excitation is represented by its energy, a voiced/unvoiced decision, and the period of the pitch fundamental.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122000666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156674
A. Komori, M. Furukawa, T. Sato, T. Komazaki
This paper will discuss subscriber loop transceivers designed for loop loss in excess of 42dB at 200Kb/s, Switched Capacitor filters for thesqrt{f}AGC and digital analog techniques for the bridged tap equalizer will also be covered.
{"title":"A 200Kb/s burst mode transceiver with two-bridge tap equalizer","authors":"A. Komori, M. Furukawa, T. Sato, T. Komazaki","doi":"10.1109/ISSCC.1984.1156674","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156674","url":null,"abstract":"This paper will discuss subscriber loop transceivers designed for loop loss in excess of 42dB at 200Kb/s, Switched Capacitor filters for thesqrt{f}AGC and digital analog techniques for the bridged tap equalizer will also be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121065000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/isscc.1984.1156701
Provides a listing of current committee members.
提供当前委员会成员的列表。
{"title":"Program committee 1984 ISSCC","authors":"","doi":"10.1109/isscc.1984.1156701","DOIUrl":"https://doi.org/10.1109/isscc.1984.1156701","url":null,"abstract":"Provides a listing of current committee members.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156693
R. Dutton
The testing problem may dominate cost and even design time for VLSI. Testing at both the system and chip levels will be addressed, stressing the procedures that could be required for full custom versus array-based approaches . . . To be considered too will be the integration of test capability directly on to the chip, and the interface relationships of the designer, producer and test source . . . The techniques which have been successful for MSI and LSI(path scans-LSSD/auto mated test Pattern generation) are likely to fail or have limited applicability for VLSI . . .On-chip testing strategies (self testing of on-board or other macros) may supercede global strategies, such as LSSD...Other equipment and areas that could be involved include the E-beam, and process evaluation and yield maximization testing which may be more appropriate than go/no-go on-board procedures . . .The role of university and education, related to testing and testability, will also be appraised by the panelists.
{"title":"Testing methodology for VLSI","authors":"R. Dutton","doi":"10.1109/ISSCC.1984.1156693","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156693","url":null,"abstract":"The testing problem may dominate cost and even design time for VLSI. Testing at both the system and chip levels will be addressed, stressing the procedures that could be required for full custom versus array-based approaches . . . To be considered too will be the integration of test capability directly on to the chip, and the interface relationships of the designer, producer and test source . . . The techniques which have been successful for MSI and LSI(path scans-LSSD/auto mated test Pattern generation) are likely to fail or have limited applicability for VLSI . . .On-chip testing strategies (self testing of on-board or other macros) may supercede global strategies, such as LSSD...Other equipment and areas that could be involved include the E-beam, and process evaluation and yield maximization testing which may be more appropriate than go/no-go on-board procedures . . .The role of university and education, related to testing and testability, will also be appraised by the panelists.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115615069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156703
T. Ozawa, S. Koshimaru, O. Kudo, H. Itoh, N. Harashima, N. Yasuoka, H. Asai, T. Yamanaka, S. Kikuchi
A 25ns 64K×1 CMOS SRAM with a 30.9mm2chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.
{"title":"A 25ns 64K SRAM","authors":"T. Ozawa, S. Koshimaru, O. Kudo, H. Itoh, N. Harashima, N. Yasuoka, H. Asai, T. Yamanaka, S. Kikuchi","doi":"10.1109/ISSCC.1984.1156703","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156703","url":null,"abstract":"A 25ns 64K×1 CMOS SRAM with a 30.9mm<sup>2</sup>chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115358095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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