2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)最新文献
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529982
P. Liu, J. Zhang, R. Sokolovskij, H. V. van Zeijl, B. Mimoun, G. Zhang
Wafer Level Packaging (WLP) technology for Solid State Lighting application is regarded as great potential for cost reduction. Rigid/Flexible/Rigid (RFR) substrate that is capable of transforming WLP devices from 2-dimentional into 3-dimentional devices is of enormous interest in SSL industry. In this work, numerical simulations were performed to discover the optimized geometry of interconnects in the newly developed RFR substrate to meet the harsh requirements set for SSL products. The relations of maximum temperatures in the substrate as a function of interconnect geometry and bending angle at different current levels were derived. Moreover, by using the derived relations, geometric effects on electromigration behaviours of interconnect were investigated. Suggestions were given for optimizing the geometry of interconnects and avoiding over-bending of the substrate.
{"title":"Geometric optimization of high performance interconnect of Rigid/Flexible/Rigid substrate for Wafer Level Packaging in Solid State Lighting applications by numerical simulations","authors":"P. Liu, J. Zhang, R. Sokolovskij, H. V. van Zeijl, B. Mimoun, G. Zhang","doi":"10.1109/EUROSIME.2013.6529982","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529982","url":null,"abstract":"Wafer Level Packaging (WLP) technology for Solid State Lighting application is regarded as great potential for cost reduction. Rigid/Flexible/Rigid (RFR) substrate that is capable of transforming WLP devices from 2-dimentional into 3-dimentional devices is of enormous interest in SSL industry. In this work, numerical simulations were performed to discover the optimized geometry of interconnects in the newly developed RFR substrate to meet the harsh requirements set for SSL products. The relations of maximum temperatures in the substrate as a function of interconnect geometry and bending angle at different current levels were derived. Moreover, by using the derived relations, geometric effects on electromigration behaviours of interconnect were investigated. Suggestions were given for optimizing the geometry of interconnects and avoiding over-bending of the substrate.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128814478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529940
Taekkeun Lee, Aimee Lim, Young-sun Ko, T. Lee, Byoungok Lee
Customers demand various functions from their applications and, in order to satisfy these demands, module packages must be multifunctional. This applies to power module packages that include power devices, components and control ICs. The modules must also have substrates in order dissipate heat from operating power chips as well as a PCB to create multifunctional circuits. Occasionally, specific clips are used instead of wire interconnections and the inner structures of the power module packages become complicated by a customer's design requests. When those power module packages accept epoxy molding compound (EMC), it may become difficult to achieve good `flowability,' perfect molded packages, and stable wire sweep index and it may also be hard to avoid wire sagging risk. Finite element analysis (FEA) for semiconductor encapsulation early in the design phase is now essential to finding out target designs and proper quality of flow. FEA also helps to recommend proper runner systems, gate design, and the number of gates, which also helps to save time and money when producing the initial mold die. This paper will compare and discuss the limitations of the flow pattern, wire sweep, air vent effect, and air trap between the result of commercial FEA software, Moldflow™ and the real samples.
{"title":"The evaluation of flowability and wire sweep by epoxy molding compound for power module packages using Moldflow™","authors":"Taekkeun Lee, Aimee Lim, Young-sun Ko, T. Lee, Byoungok Lee","doi":"10.1109/EUROSIME.2013.6529940","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529940","url":null,"abstract":"Customers demand various functions from their applications and, in order to satisfy these demands, module packages must be multifunctional. This applies to power module packages that include power devices, components and control ICs. The modules must also have substrates in order dissipate heat from operating power chips as well as a PCB to create multifunctional circuits. Occasionally, specific clips are used instead of wire interconnections and the inner structures of the power module packages become complicated by a customer's design requests. When those power module packages accept epoxy molding compound (EMC), it may become difficult to achieve good `flowability,' perfect molded packages, and stable wire sweep index and it may also be hard to avoid wire sagging risk. Finite element analysis (FEA) for semiconductor encapsulation early in the design phase is now essential to finding out target designs and proper quality of flow. FEA also helps to recommend proper runner systems, gate design, and the number of gates, which also helps to save time and money when producing the initial mold die. This paper will compare and discuss the limitations of the flow pattern, wire sweep, air vent effect, and air trap between the result of commercial FEA software, Moldflow™ and the real samples.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529952
J. Al Ahmar, S. Wiese
The goal in this analysis is to undestand more about the progressing of preexisting cracks in silicon solar cells under different enviromental loads. This enables to estimate critical crack sizes and reduce the losses and to improve realibility. In this work we present a 2D finite element model of encapsulated silicon solar cells containing cracks on critical positions. Cracks were modelled using special elements in ANSYS and the enviromental load caused by the thermal cycle is applied. In order to execute the evaluation of crack propagation on critical areas in the cross section of the solar cell the fracture mechanic theory is used and corresponding parameters are calculated.
{"title":"Analysis and simulation of cracks and micro cracks in PV cells","authors":"J. Al Ahmar, S. Wiese","doi":"10.1109/EUROSIME.2013.6529952","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529952","url":null,"abstract":"The goal in this analysis is to undestand more about the progressing of preexisting cracks in silicon solar cells under different enviromental loads. This enables to estimate critical crack sizes and reduce the losses and to improve realibility. In this work we present a 2D finite element model of encapsulated silicon solar cells containing cracks on critical positions. Cracks were modelled using special elements in ANSYS and the enviromental load caused by the thermal cycle is applied. In order to execute the evaluation of crack propagation on critical areas in the cross section of the solar cell the fracture mechanic theory is used and corresponding parameters are calculated.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529991
D. Vogel, E. Auerswald, J. Auersperg, S. Rzepka, B. Michel
The paper reviews some of the currently used strain / stress measurement tools developed for rather local application - deformation and stress measurement by Digital Image Correlation (DIC) techniques, microRaman, and electron diffraction for stress measurement. The selected methods possess spatial measurement resolutions of 1 μm or better, which makes them ideal to meet typical demands for strain and stress analyses on objects with high gradients, like e.g. advanced MEMS, semiconductor devices, and components of 3D IC integration. DIC methods applied to stress measurement, which have been seized past years by different labs, are described in more detail. Examples of stress determination on TSVs by DIC and microRaman approaches illustrate the utilization of these methods to analyze stresses in electronics components of current interest. Finally, a brief comparison between the DIC, microRaman and electron diffraction techniques (EBSD) is given.
{"title":"Measuring techniques for deformation and stress analysis in micro-dimensions","authors":"D. Vogel, E. Auerswald, J. Auersperg, S. Rzepka, B. Michel","doi":"10.1109/EUROSIME.2013.6529991","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529991","url":null,"abstract":"The paper reviews some of the currently used strain / stress measurement tools developed for rather local application - deformation and stress measurement by Digital Image Correlation (DIC) techniques, microRaman, and electron diffraction for stress measurement. The selected methods possess spatial measurement resolutions of 1 μm or better, which makes them ideal to meet typical demands for strain and stress analyses on objects with high gradients, like e.g. advanced MEMS, semiconductor devices, and components of 3D IC integration. DIC methods applied to stress measurement, which have been seized past years by different labs, are described in more detail. Examples of stress determination on TSVs by DIC and microRaman approaches illustrate the utilization of these methods to analyze stresses in electronics components of current interest. Finally, a brief comparison between the DIC, microRaman and electron diffraction techniques (EBSD) is given.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130818903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529962
M. F. Sousa, O. Holck, T. Braun, J. Bauer, H. Walter, O. Wittler, K. Lang
One of the most prominent failure modes in microelectronics devices is the delamination of epoxy materials (adhesives, molding compounds). The thermal mismatch at the interface between materials leads to stresses that build up during processing steps at different temperatures and in the following thermal cycling through use of the device or reliability testing. These stresses are well understood and are commonly investigated by finite element modeling. Epoxy molding compounds undergo a chemical reaction during processing called curing. Here the two components epoxy and hardener react to form a 3D network giving the molding compound its final material properties. During this process, the volume of the compound decreases, a phenomenon called cure shrinkage. The shrinkage itself can be experimentally determined, e.g. using volumetric measurements. However, due to relaxation processes that take place at higher temperatures and the changing thermal-mechanical properties during the curing process, the stresses that build up due to chemical shrinkage are more complex to consider. In this work, the mechanically relevant cure shrinkage was investigated by a combination of experiments and finite clement simulations. Samples of molding compound on Cu-leadframe material were manufactured using standard procedures. Thermal expansion experiments were performed at several temperatures recording the warpage of the samples. To extract the mechanically relevant shrinkage FE-simulations were performed mimicking the process temperatures. The resulting data was evaluated and discussed with respect to: qualitative behaviour for five different molding compounds; qualitative agreement between simulation and experiment; error margins of simulation results with respect to material properties input data; and error margins of experimental data due to processing variations and experimental setup.
{"title":"Mechanically relevant chemical shrinkage of epoxy molding compounds","authors":"M. F. Sousa, O. Holck, T. Braun, J. Bauer, H. Walter, O. Wittler, K. Lang","doi":"10.1109/EUROSIME.2013.6529962","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529962","url":null,"abstract":"One of the most prominent failure modes in microelectronics devices is the delamination of epoxy materials (adhesives, molding compounds). The thermal mismatch at the interface between materials leads to stresses that build up during processing steps at different temperatures and in the following thermal cycling through use of the device or reliability testing. These stresses are well understood and are commonly investigated by finite element modeling. Epoxy molding compounds undergo a chemical reaction during processing called curing. Here the two components epoxy and hardener react to form a 3D network giving the molding compound its final material properties. During this process, the volume of the compound decreases, a phenomenon called cure shrinkage. The shrinkage itself can be experimentally determined, e.g. using volumetric measurements. However, due to relaxation processes that take place at higher temperatures and the changing thermal-mechanical properties during the curing process, the stresses that build up due to chemical shrinkage are more complex to consider. In this work, the mechanically relevant cure shrinkage was investigated by a combination of experiments and finite clement simulations. Samples of molding compound on Cu-leadframe material were manufactured using standard procedures. Thermal expansion experiments were performed at several temperatures recording the warpage of the samples. To extract the mechanically relevant shrinkage FE-simulations were performed mimicking the process temperatures. The resulting data was evaluated and discussed with respect to: qualitative behaviour for five different molding compounds; qualitative agreement between simulation and experiment; error margins of simulation results with respect to material properties input data; and error margins of experimental data due to processing variations and experimental setup.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529935
R. Couturier, S. Domas, G. Goavec-Mérou, M. Favre, M. Lenczner, A. Meister
Atomic force microscopes (AFM) provide high resolution images of surfaces. In this paper, we focus on an interferometry method for estimation of deflections in arrays of cantilever in quasi-static regime. We propose a novel complete solution with a least square based algorithm to determine interference fringe phases and its optimized FPGA implementation. Simulations and real tests show very good results and open perspectives for real-time estimation and control of cantilever arrays in the dynamic regime.
{"title":"A cost effective AFM setup, combining interferometry and FPGA","authors":"R. Couturier, S. Domas, G. Goavec-Mérou, M. Favre, M. Lenczner, A. Meister","doi":"10.1109/EUROSIME.2013.6529935","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529935","url":null,"abstract":"Atomic force microscopes (AFM) provide high resolution images of surfaces. In this paper, we focus on an interferometry method for estimation of deflections in arrays of cantilever in quasi-static regime. We propose a novel complete solution with a least square based algorithm to determine interference fringe phases and its optimized FPGA implementation. Simulations and real tests show very good results and open perspectives for real-time estimation and control of cantilever arrays in the dynamic regime.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133443778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529967
G. Schondelmaier, S. Hartmann, D. May, A. Shaporin, S. Voigt, R. D. Rodriguez, O. Gordan, D. Zahn, J. Mehner, K. Hiller, B. Wunderle
For properties characterization of nanostructured materials and simultaneously to predict their reliability a tensile testing system consisting of a thermal actuator and a lateral nano-Newton force piezoresistive sensor is presented. The implementation of a piezoresistive load sensor in a MEMS-based tensile testing system can be regarded as an innovative and ultrasensitive method to continuously observe the specimen deformation while simultaneously measuring the applied load electronically with nano-Newton resolution. The primary technique that we have used for the fabrication of these systems is Bonding and Deep Reactive Ion Etching (BDRIE) applied on SOI wafers.
{"title":"Piezoresistive force sensor and thermal actuators usage as applications to nanosystems manipulation: Design, simulations, technology and experiments","authors":"G. Schondelmaier, S. Hartmann, D. May, A. Shaporin, S. Voigt, R. D. Rodriguez, O. Gordan, D. Zahn, J. Mehner, K. Hiller, B. Wunderle","doi":"10.1109/EUROSIME.2013.6529967","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529967","url":null,"abstract":"For properties characterization of nanostructured materials and simultaneously to predict their reliability a tensile testing system consisting of a thermal actuator and a lateral nano-Newton force piezoresistive sensor is presented. The implementation of a piezoresistive load sensor in a MEMS-based tensile testing system can be regarded as an innovative and ultrasensitive method to continuously observe the specimen deformation while simultaneously measuring the applied load electronically with nano-Newton resolution. The primary technique that we have used for the fabrication of these systems is Bonding and Deep Reactive Ion Etching (BDRIE) applied on SOI wafers.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121410410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529918
A. Renault, F. Molière, C. Munier
System in Package components (SiP) are nowadays widely used in commercial telecommunication applications. Based on More than Moore approach, SiP components consists in increasing the number of integrated circuits/packages enclosed in a single module. The main advantage of those technologies remains the possibility to densify the number of Commercial Off-The-Shelf (COTS) subsystems at component level rather than at board level. However, if the asset of SiP components seems to be obvious in term of equipment design, their reliability is still questioning regarding aeronautic environments, which are characterized by harsh and long term stresses. Furthermore, due to their quite novelty, there is no feedback about SiP devices. As a consequence, it becomes mandatory for aeronautic end users to assess in phase lead, the reliability of those devices prior to use them in electronic equipment. On this view, the goal of this paper is based on two pillars. First of all, a general methodology devoted to the component selection as a function of the mission profile and the technology will be presented. In order to underline the method, two configurations of SiP components will be studied according to two aeronautic mission profiles. Those profiles typically concern airplane and helicopter applications and will be described by the means of thermo-mechanical and vibration stresses. Then, some finite element modelling and simulations will be performed at the 2nd reliability level in order to evaluate the impact of SiP architectures on the solder joints integrity. The targeted parameters investigated in this study will be the equivalent stress, the strain and deformation. Next, either the number of cycles or the time to failure will be determined for all SiP configurations and compared to the aeronautic reliability specifications at 2nd reliability level. This approach enables an end-user component to select a suitable SiP device for his application if reliability results got by simulations successfully passes the aeronautic specifications. However, reliability results are strongly linked to the design and process parameters such as solder joints, packaging dimensions and board design or the choice of process assembly for instance. Considering both the lack of design standards and the high number of SiP configurations available on market, guidelines do not exist for end user to evaluate the reliability of commercial SiP. Based on the studied configurations, this paper will supply some design rules of SiP ball grid array architectures at 2nd level of reliability in order to fulfil the reliability specifications. This study has been performed in the framework of the ENIAC project entitled ESiP and is a result of a European collaboration between EADS, Siemens and Murata Electronics Oy.
{"title":"Reliability investigation of system in package devices toward aeronautic requirements: Methodology and application","authors":"A. Renault, F. Molière, C. Munier","doi":"10.1109/EUROSIME.2013.6529918","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529918","url":null,"abstract":"System in Package components (SiP) are nowadays widely used in commercial telecommunication applications. Based on More than Moore approach, SiP components consists in increasing the number of integrated circuits/packages enclosed in a single module. The main advantage of those technologies remains the possibility to densify the number of Commercial Off-The-Shelf (COTS) subsystems at component level rather than at board level. However, if the asset of SiP components seems to be obvious in term of equipment design, their reliability is still questioning regarding aeronautic environments, which are characterized by harsh and long term stresses. Furthermore, due to their quite novelty, there is no feedback about SiP devices. As a consequence, it becomes mandatory for aeronautic end users to assess in phase lead, the reliability of those devices prior to use them in electronic equipment. On this view, the goal of this paper is based on two pillars. First of all, a general methodology devoted to the component selection as a function of the mission profile and the technology will be presented. In order to underline the method, two configurations of SiP components will be studied according to two aeronautic mission profiles. Those profiles typically concern airplane and helicopter applications and will be described by the means of thermo-mechanical and vibration stresses. Then, some finite element modelling and simulations will be performed at the 2nd reliability level in order to evaluate the impact of SiP architectures on the solder joints integrity. The targeted parameters investigated in this study will be the equivalent stress, the strain and deformation. Next, either the number of cycles or the time to failure will be determined for all SiP configurations and compared to the aeronautic reliability specifications at 2nd reliability level. This approach enables an end-user component to select a suitable SiP device for his application if reliability results got by simulations successfully passes the aeronautic specifications. However, reliability results are strongly linked to the design and process parameters such as solder joints, packaging dimensions and board design or the choice of process assembly for instance. Considering both the lack of design standards and the high number of SiP configurations available on market, guidelines do not exist for end user to evaluate the reliability of commercial SiP. Based on the studied configurations, this paper will supply some design rules of SiP ball grid array architectures at 2nd level of reliability in order to fulfil the reliability specifications. This study has been performed in the framework of the ENIAC project entitled ESiP and is a result of a European collaboration between EADS, Siemens and Murata Electronics Oy.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114539054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/EUROSIME.2013.6529943
J. Heilmann, B. Wunderle, S. G. Kumar, O. Hoelck, H. Walter, O. Wittler, G. Engelmann, M. Wolf, G. Beer, K. Pressel
Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermomechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapid isothermal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed.In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry.
{"title":"Reliability of Cu-plated through encapsulant vias (TEV) for 3D-integration","authors":"J. Heilmann, B. Wunderle, S. G. Kumar, O. Hoelck, H. Walter, O. Wittler, G. Engelmann, M. Wolf, G. Beer, K. Pressel","doi":"10.1109/EUROSIME.2013.6529943","DOIUrl":"https://doi.org/10.1109/EUROSIME.2013.6529943","url":null,"abstract":"Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermomechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapid isothermal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed.In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127044545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1016/j.microrel.2014.02.016
E. Parsa, Hao Huang, A. Dasgupta
{"title":"Multi-physics simulations for combined temperature/humidity cycling of potted electronic assemblies","authors":"E. Parsa, Hao Huang, A. Dasgupta","doi":"10.1016/j.microrel.2014.02.016","DOIUrl":"https://doi.org/10.1016/j.microrel.2014.02.016","url":null,"abstract":"","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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