Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550981
M. Duffy, G. Lasser, M. Roberg, Z. Popovic
This paper presents the design and measured continuous wave (CW) performance of a three-stage K-band MMIC power amplifier with greater than 4 W peak output power and a peak power added efficiency (PAE) ranging from 40–45 %. The output power exceeds 3.2 W over the frequency range of 18 to 24 GHz with less than 1.5 dB variation. The MMIC is implemented in Qorvo's 150-nm GaN on SiC process. The three stage architecture enables greater than 20dB of saturated gain from 18.5-24 GHz.
{"title":"A 4-W K-Band 40% PAE Three-Stage MMIC Power Amplifier","authors":"M. Duffy, G. Lasser, M. Roberg, Z. Popovic","doi":"10.1109/BCICTS.2018.8550981","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550981","url":null,"abstract":"This paper presents the design and measured continuous wave (CW) performance of a three-stage K-band MMIC power amplifier with greater than 4 W peak output power and a peak power added efficiency (PAE) ranging from 40–45 %. The output power exceeds 3.2 W over the frequency range of 18 to 24 GHz with less than 1.5 dB variation. The MMIC is implemented in Qorvo's 150-nm GaN on SiC process. The three stage architecture enables greater than 20dB of saturated gain from 18.5-24 GHz.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"15 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120913339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550939
T. Merkle, S. Wagner, A. Tessmann, M. Kuri, H. Massler, A. Leuther
Subject of this paper is an integrated transceiver frontend MMIC that was designed for millimeter-wave wideband radar systems operating at a center frequency of 240 GHz. The MMIC was implemented using a 35 nm InAIAs/InGaAs based metamorphic HEMT technology. The key RF parameters of transmit power, receiver conversion gain and noise figure, are achieved over a 1-dB defined bandwidth of 40 GHz. The MMIC was also packaged and tested in a WR-3 waveguide module. Between 220 and 260 GHz, an output power of 6 dBm with a flatness of better than 1 dB was measured, as well as an average receiver noise figure of 7 dB and a conversion gain of 10 dB. The on-wafer measured output power of the transceiver MMIC reached 8 dBm applying an increased dc drain voltage. Several breakout circuits were manufactured for additional separate on-wafer characterization of sub-functions of the transceiver MMIC. For example, the power amplifier of the transmit path achieved a saturated output power of 10 dBm at 240 GHz while consuming a chip area of only $mathbf{500} mathbf{x} mathbf{225} mu text{m}$.
{"title":"Integrated 220–260 GHz Radar Frontend","authors":"T. Merkle, S. Wagner, A. Tessmann, M. Kuri, H. Massler, A. Leuther","doi":"10.1109/BCICTS.2018.8550939","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550939","url":null,"abstract":"Subject of this paper is an integrated transceiver frontend MMIC that was designed for millimeter-wave wideband radar systems operating at a center frequency of 240 GHz. The MMIC was implemented using a 35 nm InAIAs/InGaAs based metamorphic HEMT technology. The key RF parameters of transmit power, receiver conversion gain and noise figure, are achieved over a 1-dB defined bandwidth of 40 GHz. The MMIC was also packaged and tested in a WR-3 waveguide module. Between 220 and 260 GHz, an output power of 6 dBm with a flatness of better than 1 dB was measured, as well as an average receiver noise figure of 7 dB and a conversion gain of 10 dB. The on-wafer measured output power of the transceiver MMIC reached 8 dBm applying an increased dc drain voltage. Several breakout circuits were manufactured for additional separate on-wafer characterization of sub-functions of the transceiver MMIC. For example, the power amplifier of the transmit path achieved a saturated output power of 10 dBm at 240 GHz while consuming a chip area of only $mathbf{500} mathbf{x} mathbf{225} mu text{m}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/bcicts.2018.8551036
A. Arabhavi, W. Quan, O. Ostinelli, C. Bolognesi
The scaling behavior of Type-II InP/GaAsSb double heterojunction bipolar transistors (DHBTs) is studied and a 10 μm long emitter with cutoff frequencies of $f_{text{T}}/f_{text{MAX}}=463/829$ GHz and is demonstrated. Such a high $f_{text{MAX}}$ was made possible by aggressive lateral scaling of the base-collector (BC) mesa which helps to reduce the extrinsic BC capacitance. The limitations in furthering the lateral scaling for these devices are examined. The present transistors show the highest $f_{text{MAX}}$ for a $10 mutext{m}$ long emitter for any HBT, indicating the excellent scaling properties of Type-II DHBTs.
{"title":"Scaling of InP/GaAsSb DHBTs: A Simultaneous $f_{text{T}}/f_{text{MAX}}=463/829$ GHz in a $10 mu text{m}$ Long Emitter","authors":"A. Arabhavi, W. Quan, O. Ostinelli, C. Bolognesi","doi":"10.1109/bcicts.2018.8551036","DOIUrl":"https://doi.org/10.1109/bcicts.2018.8551036","url":null,"abstract":"The scaling behavior of Type-II InP/GaAsSb double heterojunction bipolar transistors (DHBTs) is studied and a 10 μm long emitter with cutoff frequencies of $f_{text{T}}/f_{text{MAX}}=463/829$ GHz and is demonstrated. Such a high $f_{text{MAX}}$ was made possible by aggressive lateral scaling of the base-collector (BC) mesa which helps to reduce the extrinsic BC capacitance. The limitations in furthering the lateral scaling for these devices are examined. The present transistors show the highest $f_{text{MAX}}$ for a $10 mutext{m}$ long emitter for any HBT, indicating the excellent scaling properties of Type-II DHBTs.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133239585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551154
M. Lundstrom
The continued down-scaling of transistor dimensions demands a deeper and deeper understanding of semiclassical and quantum transport in transistors. By discussing several examples, this talk summarizes the physics of semiclassical transport relevant to bipolar transistors. The goal is to review the comprehensive understanding of transport that has been developed over the decades and to do so in a way that provides a starting point for those who wish to dive deeper and for those who want to be knowledgeable users of TCAD tools.
{"title":"Carrier Transport in BJTs: from Ballistic to Diffusive and Off-Equilibrium","authors":"M. Lundstrom","doi":"10.1109/BCICTS.2018.8551154","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551154","url":null,"abstract":"The continued down-scaling of transistor dimensions demands a deeper and deeper understanding of semiclassical and quantum transport in transistors. By discussing several examples, this talk summarizes the physics of semiclassical transport relevant to bipolar transistors. The goal is to review the comprehensive understanding of transport that has been developed over the decades and to do so in a way that provides a starting point for those who wish to dive deeper and for those who want to be knowledgeable users of TCAD tools.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115220219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550922
D. Manger, W. Liebl, S. Boguth, B. Binder, K. Aufinger, C. Dahl, C. Hengst, A. Pribil, J. Oestreich, S. Rohmfeld, S. Rothenhaeusser, D. Tschumakow, J. Boeck
In this paper the successful implementation of a SiGe-HBT process module with an $mathbf{f}_{max}$ of 537GHz and an $mathbf{f}_{text{T}}$ of 305GHz in a 130nm BiCMOS technology is reported. A modified Epitaxial-Base-Link process, based on previous work done at IHP, was chosen for HBT device architecture, due to its proven performance potential. Ring oscillator gate-delays in current-mode-logic (CML) with a wafer mean value of 1.83ps and a standard deviation of 0.02ps were achieved. Integration options with a 90nm CMOS technology are discussed, with focus on the interaction of the HBT and CMOS process modules in terms of CMOS device parameter shift and potential remedies.
{"title":"Integration of SiGe HBT with $text{f}_{text{T}}=305 text{GHz}, text{f}_{max}=537 text{GHz}$ in 130nm and 90nm CMOS","authors":"D. Manger, W. Liebl, S. Boguth, B. Binder, K. Aufinger, C. Dahl, C. Hengst, A. Pribil, J. Oestreich, S. Rohmfeld, S. Rothenhaeusser, D. Tschumakow, J. Boeck","doi":"10.1109/BCICTS.2018.8550922","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550922","url":null,"abstract":"In this paper the successful implementation of a SiGe-HBT process module with an $mathbf{f}_{max}$ of 537GHz and an $mathbf{f}_{text{T}}$ of 305GHz in a 130nm BiCMOS technology is reported. A modified Epitaxial-Base-Link process, based on previous work done at IHP, was chosen for HBT device architecture, due to its proven performance potential. Ring oscillator gate-delays in current-mode-logic (CML) with a wafer mean value of 1.83ps and a standard deviation of 0.02ps were achieved. Integration options with a 90nm CMOS technology are discussed, with focus on the interaction of the HBT and CMOS process modules in terms of CMOS device parameter shift and potential remedies.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129754505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551123
Abdurrahman H. Aliuhani, T. Kanar, Gabriel M. Rebeiz
This paper presents a packaged single-ended three-stage K-band low noise amplifier (LNA) using Jazz SBC18H3 SiGe process technology. The LNA consists of three common emitter (CE) stages to achieve a stable packaged amplifier with low noise figure (NF) and high gain. The measured $mathbf{S}_{mathbf{21}}$ is 20.3 dB with a 3-dB bandwidth of 7 GHz (14.4 – 21.4 GHz). The measured mean NF is 2.14 dB at 18.4 GHz and it is $< 2.3$ at (17.1-19.7 GHz). At 18 GHz, the measured $mathbf{IPi}_{mathbf{1dB}},mathbf{OP}_{mathbf{1dB}},mathbf{IIP}_{3}$, and $mathbf{OIP}_{3}$ are −23.7, −4.9, −15.3, and 5.1 dBm, respectively. This is achieved at a power consumption of 18-mW. To our knowledge, this represents state-of-the-art packaged K-band LNAs in term of gain, NF, and power consumption in SiGe and CMOS processes.
{"title":"A Packaged Single-Ended K-Band SiGe LNA with 2.14 dB Mean Noise Figure","authors":"Abdurrahman H. Aliuhani, T. Kanar, Gabriel M. Rebeiz","doi":"10.1109/BCICTS.2018.8551123","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551123","url":null,"abstract":"This paper presents a packaged single-ended three-stage K-band low noise amplifier (LNA) using Jazz SBC18H3 SiGe process technology. The LNA consists of three common emitter (CE) stages to achieve a stable packaged amplifier with low noise figure (NF) and high gain. The measured $mathbf{S}_{mathbf{21}}$ is 20.3 dB with a 3-dB bandwidth of 7 GHz (14.4 – 21.4 GHz). The measured mean NF is 2.14 dB at 18.4 GHz and it is $< 2.3$ at (17.1-19.7 GHz). At 18 GHz, the measured $mathbf{IPi}_{mathbf{1dB}},mathbf{OP}_{mathbf{1dB}},mathbf{IIP}_{3}$, and $mathbf{OIP}_{3}$ are −23.7, −4.9, −15.3, and 5.1 dBm, respectively. This is achieved at a power consumption of 18-mW. To our knowledge, this represents state-of-the-art packaged K-band LNAs in term of gain, NF, and power consumption in SiGe and CMOS processes.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121353346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551087
Brian R. Wier, Rafael Perez Martinez, Uppili S. Raghunathar, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler
This paper presents and validates a physics-based compact aging model for predictive simulation of hot-carrier degradation in SiGe HBTs. Separate aging functions model the effects of high-field mixed-mode and high-current Auger-hot-carrier stresses and are integrated together to provide predictive capability across a wide bias range. The variation of aging rate with device geometry and the incorporation of multiple parameter shifts due to hot carrier polysilicon degradation are explored. Additionally, aging simulation results of a driver circuit are presented to begin to demonstrate how such models may be incorporated as part of the circuit design process.
{"title":"Revisiting Safe Operating Area: SiGe HBT Aging Models for Reliability-Aware Circuit Design","authors":"Brian R. Wier, Rafael Perez Martinez, Uppili S. Raghunathar, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler","doi":"10.1109/BCICTS.2018.8551087","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551087","url":null,"abstract":"This paper presents and validates a physics-based compact aging model for predictive simulation of hot-carrier degradation in SiGe HBTs. Separate aging functions model the effects of high-field mixed-mode and high-current Auger-hot-carrier stresses and are integrated together to provide predictive capability across a wide bias range. The variation of aging rate with device geometry and the incorporation of multiple parameter shifts due to hot carrier polysilicon degradation are explored. Additionally, aging simulation results of a driver circuit are presented to begin to demonstrate how such models may be incorporated as part of the circuit design process.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128952814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550911
P. Thomas, M. Buck, M. Grözing, M. Berroth, J. Rauscher, M. Epp, M. Schlumpp
This paper presents a track-and-hold amplifier based on a switched emitter follower with demonstrated sampling rates from 6.4 GS/s to 32 GS/s and an analog bandwidth of up to 19 GHz in the hold-mode. Linearity measurements in the first Nyquist zone show 4.9 - 7.9 bits of accuracy for the highest sampling rate, more than 6 bits for up to 25.6 GS/s, more than 7 bits for up to 12.8 GS/s and a maximum of 8.9 bits at 6.4 GS/s, all calculated from the SNDR values. Most comparable circuits use only the THD value to calculate ENOBs, since achieving high SNR is difficult for low signal power circuits. The measurement results of the proposed track-and-hold amplifier were obtained at a high differential input voltage swing of 2.0 Vpp while they can reach even higher values at 1.0 Vpp. The 1-dB compression point is even higher, at 18.9 dBm. This makes the circuit suitable for high signal or noise power applications that demand high data rates and high linearity at the same time, including radio frequency instrumentation and receivers in radar and satellite communications. Designed as the front-end of a folding ADC, an additional benefit is the track-mode masking, recovering the common-mode level of the outputs during the input track-mode, which can be important when working with high input voltages. The third-order intercept point of 27.4 dBm at 25.6 GS/s and up to 34.7 dBm at 6.4 GS/s shows the unique combination of high signal power and high linearity in a sampling circuit above 10 GHz. This is made possible by the modern 55 nm SiGe-BiCMOS technology with high-performance HBTs.
{"title":"An Adaptable 6.4 - 32 GS/s Track-and-Hold Amplifier with Track-Mode Masking for High Signal Power Applications in 55 nm SiGe-BiCMOS","authors":"P. Thomas, M. Buck, M. Grözing, M. Berroth, J. Rauscher, M. Epp, M. Schlumpp","doi":"10.1109/BCICTS.2018.8550911","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550911","url":null,"abstract":"This paper presents a track-and-hold amplifier based on a switched emitter follower with demonstrated sampling rates from 6.4 GS/s to 32 GS/s and an analog bandwidth of up to 19 GHz in the hold-mode. Linearity measurements in the first Nyquist zone show 4.9 - 7.9 bits of accuracy for the highest sampling rate, more than 6 bits for up to 25.6 GS/s, more than 7 bits for up to 12.8 GS/s and a maximum of 8.9 bits at 6.4 GS/s, all calculated from the SNDR values. Most comparable circuits use only the THD value to calculate ENOBs, since achieving high SNR is difficult for low signal power circuits. The measurement results of the proposed track-and-hold amplifier were obtained at a high differential input voltage swing of 2.0 Vpp while they can reach even higher values at 1.0 Vpp. The 1-dB compression point is even higher, at 18.9 dBm. This makes the circuit suitable for high signal or noise power applications that demand high data rates and high linearity at the same time, including radio frequency instrumentation and receivers in radar and satellite communications. Designed as the front-end of a folding ADC, an additional benefit is the track-mode masking, recovering the common-mode level of the outputs during the input track-mode, which can be important when working with high input voltages. The third-order intercept point of 27.4 dBm at 25.6 GS/s and up to 34.7 dBm at 6.4 GS/s shows the unique combination of high signal power and high linearity in a sampling circuit above 10 GHz. This is made possible by the modern 55 nm SiGe-BiCMOS technology with high-performance HBTs.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132728427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550842
Alireza Zandieh, Naftali Weiss, Thelinh Nguyen, David Haranne, S. Voinigescu
The analog front-end of a 6-to-8 bit 128-GS/s SAR ADC architecture with record 60-GHz input bandwidth is presented. It includes the data path, 25% duty-cycle dc-32 GHz quadrature clock generator, 4 master, and 32 slave track-and-hold (T&H) circuits formed with CMOS series switches. Each of the 32 slave CMOS T&Hs drives either a $pmb{50}-Omega$ output buffer (for testing) or a 30-fF hold capacitor, representative of the load provided by each of the 32 SAR sub-ADCs. To achieve record bandwidth and sampling rate, the data distribution network and the single-ended-to-differential clock amplifier use novel 0.8-V n-MOS and 1.2-V p-MOS Cherry-Hooper buffers with good common-mode and supply rejection beyond 100 GHz, validated through small-and large-signal measurements. The 32-GHz quadrature clock generator is realized with a novel 80-GHz input bandwidth, 0.8- V quasi-CML static divider, followed by inductively-peaked CMOS logic circuits. The total power consumption of the analog frontend is 320 mW of which 120 mWare consumed by the data sampling interleaver and 200 mW bv the clock generation unit. It occupies a total die area of $mathbf{0.65} mathbf{mm}times mathbf{0.37} mathbf{mm}$.
提出了一种输入带宽为60ghz的6 ~ 8位128-GS/s SAR ADC结构的模拟前端。它包括数据路径、25%占空比dc- 32ghz正交时钟发生器、4个主电路和32个从电路，由CMOS系列开关组成。32个从CMOS t&h中的每一个驱动$pmb{50}-Omega$输出缓冲器(用于测试)或30-fF保持电容器，代表32个SAR子adc中的每一个提供的负载。为了实现创纪录的带宽和采样率，数据分配网络和单端差分时钟放大器使用新颖的0.8 v n-MOS和1.2 v p-MOS Cherry-Hooper缓冲器，具有良好的共模和100 GHz以上的电源抑制，通过小信号和大信号测量验证。32ghz正交时钟发生器采用新颖的80ghz输入带宽、0.8 V准cml静态分频器和感应峰值CMOS逻辑电路实现。模拟前端的总功耗为320兆瓦，其中数据采样交织器消耗120兆瓦，时钟产生单元消耗200兆瓦。它占用的总模具面积为$mathbf{0.65} mathbf{mm}乘以mathbf{0.37} mathbf{mm}$。
{"title":"128-GS/s ADC Front-End with Over 60-GHz Input Bandwidth in 22-nm Si/SiGe FDSOI CMOS","authors":"Alireza Zandieh, Naftali Weiss, Thelinh Nguyen, David Haranne, S. Voinigescu","doi":"10.1109/BCICTS.2018.8550842","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550842","url":null,"abstract":"The analog front-end of a 6-to-8 bit 128-GS/s SAR ADC architecture with record 60-GHz input bandwidth is presented. It includes the data path, 25% duty-cycle dc-32 GHz quadrature clock generator, 4 master, and 32 slave track-and-hold (T&H) circuits formed with CMOS series switches. Each of the 32 slave CMOS T&Hs drives either a $pmb{50}-Omega$ output buffer (for testing) or a 30-fF hold capacitor, representative of the load provided by each of the 32 SAR sub-ADCs. To achieve record bandwidth and sampling rate, the data distribution network and the single-ended-to-differential clock amplifier use novel 0.8-V n-MOS and 1.2-V p-MOS Cherry-Hooper buffers with good common-mode and supply rejection beyond 100 GHz, validated through small-and large-signal measurements. The 32-GHz quadrature clock generator is realized with a novel 80-GHz input bandwidth, 0.8- V quasi-CML static divider, followed by inductively-peaked CMOS logic circuits. The total power consumption of the analog frontend is 320 mW of which 120 mWare consumed by the data sampling interleaver and 200 mW bv the clock generation unit. It occupies a total die area of $mathbf{0.65} mathbf{mm}times mathbf{0.37} mathbf{mm}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132137332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550963
P. Chevalier, W. Liebl, H. Rücker, A. Gauthier, D. Manger, B. Heinemann, G. Avenier, J. Böck
This paper reviews the advantages of SiGe BiCMOS technologies and their applications in the millimeterwave to terahertz domains. The state-of-the-art covering both the Si/SiGe HBTs and the CMOS nodes is shown. Future perspectives and related main challenges are discussed with a focus on the ongoing European research activities through the presentation of the TARANTO project, whose main objective is to help developing 600 GHz $pmb{f}_{mathbf{MAX}}$ nanoscale SiGe BiCMOS platforms.
{"title":"SiGe BiCMOS Current Status and Future Trends in Europe","authors":"P. Chevalier, W. Liebl, H. Rücker, A. Gauthier, D. Manger, B. Heinemann, G. Avenier, J. Böck","doi":"10.1109/BCICTS.2018.8550963","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550963","url":null,"abstract":"This paper reviews the advantages of SiGe BiCMOS technologies and their applications in the millimeterwave to terahertz domains. The state-of-the-art covering both the Si/SiGe HBTs and the CMOS nodes is shown. Future perspectives and related main challenges are discussed with a focus on the ongoing European research activities through the presentation of the TARANTO project, whose main objective is to help developing 600 GHz $pmb{f}_{mathbf{MAX}}$ nanoscale SiGe BiCMOS platforms.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"37 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114039390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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