Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550893
Badou Sene, V. Issakov
In this paper a low-power Low Noise Amplifier (LNA) with ultra broad bandwidth is presented. We propose a novel circuit-level technique using a triple feedback loop to optimize simultaneously gain, bandwidth and impedance matching without the penalty of added DC power dissipation. The circuit has been fabricated using a 130 nm silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The LNA has a peak gain of 9.3 dB, a minimum noise figure of 4.6 dB and an input compression point (IP1dB) higher than −9.9 dBm. It consumes only 5.4 mW using a single 1.5 V supply voltage, while working over a bandwidth from 14 to 58 GHz and occupying an area of $mathbf{0.6}times mathbf{0.48} mathbf{mm}^{2}$ including pads.
{"title":"A Low-Power Triple-Loop Feedback Broadband LNA in a 130 nm SiGe BiCMOS Technology","authors":"Badou Sene, V. Issakov","doi":"10.1109/BCICTS.2018.8550893","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550893","url":null,"abstract":"In this paper a low-power Low Noise Amplifier (LNA) with ultra broad bandwidth is presented. We propose a novel circuit-level technique using a triple feedback loop to optimize simultaneously gain, bandwidth and impedance matching without the penalty of added DC power dissipation. The circuit has been fabricated using a 130 nm silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The LNA has a peak gain of 9.3 dB, a minimum noise figure of 4.6 dB and an input compression point (IP1dB) higher than −9.9 dBm. It consumes only 5.4 mW using a single 1.5 V supply voltage, while working over a bandwidth from 14 to 58 GHz and occupying an area of $mathbf{0.6}times mathbf{0.48} mathbf{mm}^{2}$ including pads.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551148
Eugene A. Fitzgerald
Materials and processes to create monolithic 111-V+CMOS circuits have been developed iteratively with inputs from potential market application needs and semiconductor industry infrastructure. The GaN LED and III-V HEMT platforms are earliest to develop and driven by currently anticipated market needs. The developed process flow involves conventional 200mm CMOS front-end processing in a CMOS foundry, merging the CMOS wafer with a III-V/Si wafer, processing III-V devices in a silicon fabrication environment, and final interconnection via returning the wafer to a CMOS foundry for back-end interconnection. III-V+CMOS silicon ICs are designed in a Cadence environment using foundry PDKs modified with insertion of the integrated III-V device models. The overall method described above is invariant for the different III-V's that are integrated into silicon ICs. Circuits have been designed using GaN LED+CMOS, GaN HEMT+CMOS, InGaAs HEMT+CMOS, and InGaP LED+CMOS platforms.
{"title":"Materials, Processes, and Markets for Monolithic III-V Devices in Silicon Integrated Circuits","authors":"Eugene A. Fitzgerald","doi":"10.1109/BCICTS.2018.8551148","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551148","url":null,"abstract":"Materials and processes to create monolithic 111-V+CMOS circuits have been developed iteratively with inputs from potential market application needs and semiconductor industry infrastructure. The GaN LED and III-V HEMT platforms are earliest to develop and driven by currently anticipated market needs. The developed process flow involves conventional 200mm CMOS front-end processing in a CMOS foundry, merging the CMOS wafer with a III-V/Si wafer, processing III-V devices in a silicon fabrication environment, and final interconnection via returning the wafer to a CMOS foundry for back-end interconnection. III-V+CMOS silicon ICs are designed in a Cadence environment using foundry PDKs modified with insertion of the integrated III-V device models. The overall method described above is invariant for the different III-V's that are integrated into silicon ICs. Circuits have been designed using GaN LED+CMOS, GaN HEMT+CMOS, InGaAs HEMT+CMOS, and InGaP LED+CMOS platforms.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134336545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551075
M. Roberg, Thi Ri Mya Kywe, Matthew Irvine, O. Marrufo, S. Nayak
This paper presents single and dual output 40 W Ka-Band GaN MMIC PAs fabricated on $mathbf{50} mu text{m}$ SiC using Qorvo's QGaN15 released process. The single output PA produces approximately 40 W of output power over the 27.5 - 29.5 GHz band and greater than 30W over the 26.5 - 31 GHz band with greater than 20 % PAE. A balanced PA architecture is selected resulting in return losses greater than 15 dB in fixture. The PA exhibits less than 0.3 dB power droop over a 5 ms pulse width. Design choices minimizing the performance degradation due to process variation are discussed. A dual output PA integrated with an input SPDT switch and output isolation circuitry is also detailed. This variant allowing the output signal to be routed to one of two selectable outputs without requiring large output switch devices is presented with preliminary measured results.
{"title":"40 W Ka-Band Single and Dual Output GaN MMIC Power Amplifiers on SiC","authors":"M. Roberg, Thi Ri Mya Kywe, Matthew Irvine, O. Marrufo, S. Nayak","doi":"10.1109/BCICTS.2018.8551075","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551075","url":null,"abstract":"This paper presents single and dual output 40 W Ka-Band GaN MMIC PAs fabricated on $mathbf{50} mu text{m}$ SiC using Qorvo's QGaN15 released process. The single output PA produces approximately 40 W of output power over the 27.5 - 29.5 GHz band and greater than 30W over the 26.5 - 31 GHz band with greater than 20 % PAE. A balanced PA architecture is selected resulting in return losses greater than 15 dB in fixture. The PA exhibits less than 0.3 dB power droop over a 5 ms pulse width. Design choices minimizing the performance degradation due to process variation are discussed. A dual output PA integrated with an input SPDT switch and output isolation circuitry is also detailed. This variant allowing the output signal to be routed to one of two selectable outputs without requiring large output switch devices is presented with preliminary measured results.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125023696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551045
Hiroshi Yamamoto, K. Kikuchi, N. Ui, Kazutaka Inoue, V. Vadalà, G. Bosi, A. Raffo, G. Vannini
This paper describes the influence of gate-voltage clipping behavior on drain efficiency in case of class-F and inverse class-F $(mathbf{F}^{-1})$ operations under saturated regime. Numerical analysis using a simplified transistor model was carried out. As a result, we have demonstrated that the limiting factor for $mathbf{class}-mathbf{F}^{-1}$ operation is the gate-diode conduction rather than knee voltage. On the other hand, class-F PA is restricted by the knee voltage effects. Furthermore, nonlinear measurements carried out on a GaN HEMT support our analytical results.
{"title":"Analysis of Gate-Voltage Clipping Behavior on Class-F and Inverse Class-F Amplifiers","authors":"Hiroshi Yamamoto, K. Kikuchi, N. Ui, Kazutaka Inoue, V. Vadalà, G. Bosi, A. Raffo, G. Vannini","doi":"10.1109/BCICTS.2018.8551045","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551045","url":null,"abstract":"This paper describes the influence of gate-voltage clipping behavior on drain efficiency in case of class-F and inverse class-F $(mathbf{F}^{-1})$ operations under saturated regime. Numerical analysis using a simplified transistor model was carried out. As a result, we have demonstrated that the limiting factor for $mathbf{class}-mathbf{F}^{-1}$ operation is the gate-diode conduction rather than knee voltage. On the other hand, class-F PA is restricted by the knee voltage effects. Furthermore, nonlinear measurements carried out on a GaN HEMT support our analytical results.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551068
U. Pfeiffer, R. Jain, J. Grzyb, S. Malz, P. Hillger, Pedro Rodríguez-Vázquez
Despite its several applications, terahertz (THz) radiation has posed a particular challenge for hardware design. Several expensive and bulky laser or III-V semiconductor based solutions have been employed for THz systems. However, over the last decade, there has been a tremendous research into the design of THz integrated circuits in commercial silicon CMOS and SiGe HBT BiCMOS process technologies. Silicon based systems primarily benefit from the mixed signal integration capabilities of the technology, which enable a new set of possibilities and applications in the THz domain. In this paper, we review the current status of THz integrated circuits. We discuss trends in silicon based THz sources and receivers, as well as different THz on-chip systems that have been reported so far for different application areas.
{"title":"Current Status of Terahertz Integrated Circuits - From Components to Systems","authors":"U. Pfeiffer, R. Jain, J. Grzyb, S. Malz, P. Hillger, Pedro Rodríguez-Vázquez","doi":"10.1109/BCICTS.2018.8551068","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551068","url":null,"abstract":"Despite its several applications, terahertz (THz) radiation has posed a particular challenge for hardware design. Several expensive and bulky laser or III-V semiconductor based solutions have been employed for THz systems. However, over the last decade, there has been a tremendous research into the design of THz integrated circuits in commercial silicon CMOS and SiGe HBT BiCMOS process technologies. Silicon based systems primarily benefit from the mixed signal integration capabilities of the technology, which enable a new set of possibilities and applications in the THz domain. In this paper, we review the current status of THz integrated circuits. We discuss trends in silicon based THz sources and receivers, as well as different THz on-chip systems that have been reported so far for different application areas.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115509697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551146
J. Žilak, M. Koričić, Željko Osrečki, M. Simic, T. Suligoj
Noise parameters of the Horizontal Current Bipolar Transistor (HCBT) Technology are examined for the first time. Impact of technological parameters (i.e., three different collector doping profiles) on the noise performance is analyzed and explained. The HCBT with the uniform n-collector profile has the smallest minimum noise figure $(pmb{N}F_{min})$ of 0.91 dB at $pmb{f}=mathbf{0.9}$ GHz and 1.09 dB at $pmb{f}=pmb{1.5}$ GHz, while the HCBT with the low-doped n-collector has the highest associated gain implying the best noise-gain tradeoff. All three HCBTs have the optimum collector current $(pmb{I}_{text{Copt}})$ at the lowest $pmb{NF}_{min}$ of around 5 mA and 10 mA at 0.9 GHz and 1.5 GHz, respectively, as well as the optimum impedance $pmb{Z}_{text{opt}}$ close to $mathbf{50} Omega$. Several low-noise amplifiers are fabricated with $pmb{NF}=mathbf{1.22} mathbf{dB}$ and power gain up to 17.2 dB at 0.9 GHz.
{"title":"Noise Figure Characterization of Horizontal Current Bipolar Transistor (HCBT)","authors":"J. Žilak, M. Koričić, Željko Osrečki, M. Simic, T. Suligoj","doi":"10.1109/BCICTS.2018.8551146","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551146","url":null,"abstract":"Noise parameters of the Horizontal Current Bipolar Transistor (HCBT) Technology are examined for the first time. Impact of technological parameters (i.e., three different collector doping profiles) on the noise performance is analyzed and explained. The HCBT with the uniform n-collector profile has the smallest minimum noise figure $(pmb{N}F_{min})$ of 0.91 dB at $pmb{f}=mathbf{0.9}$ GHz and 1.09 dB at $pmb{f}=pmb{1.5}$ GHz, while the HCBT with the low-doped n-collector has the highest associated gain implying the best noise-gain tradeoff. All three HCBTs have the optimum collector current $(pmb{I}_{text{Copt}})$ at the lowest $pmb{NF}_{min}$ of around 5 mA and 10 mA at 0.9 GHz and 1.5 GHz, respectively, as well as the optimum impedance $pmb{Z}_{text{opt}}$ close to $mathbf{50} Omega$. Several low-noise amplifiers are fabricated with $pmb{NF}=mathbf{1.22} mathbf{dB}$ and power gain up to 17.2 dB at 0.9 GHz.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128800266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551138
Sunil G. Rao, Tianyu Chang, I. Song, Moon-Kyu Cho, J. Cressler
This paper presents a wideband distributed power amplifier that operates from 1–20 GHz. The peak output power is 19.5 dBm, with a peak PAE of 28% at 1 GHz. The power amplifier utilizes a distributed amplifier topology with artificial transmission lines, as well as transistor stacking, to achieve high output power and wide bandwidth. For the amplifier core power cells, a stack-up of four SiGe HBTs was used to distribute the maximum voltage swing across the amplifier. This power amplifier, designed in a 90 nm SiGe BiCMOS platform, occupies an area of $mathbf{1.95}times mathbf{1.3}mathbf{mm}^{2}$.
{"title":"A 1–20 GHz Distributed, Stacked SiGe Power Amplifier","authors":"Sunil G. Rao, Tianyu Chang, I. Song, Moon-Kyu Cho, J. Cressler","doi":"10.1109/BCICTS.2018.8551138","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551138","url":null,"abstract":"This paper presents a wideband distributed power amplifier that operates from 1–20 GHz. The peak output power is 19.5 dBm, with a peak PAE of 28% at 1 GHz. The power amplifier utilizes a distributed amplifier topology with artificial transmission lines, as well as transistor stacking, to achieve high output power and wide bandwidth. For the amplifier core power cells, a stack-up of four SiGe HBTs was used to distribute the maximum voltage swing across the amplifier. This power amplifier, designed in a 90 nm SiGe BiCMOS platform, occupies an area of $mathbf{1.95}times mathbf{1.3}mathbf{mm}^{2}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550954
A. Simsek, Seong-Kyun Kim, M. Rodwell
This paper demonstrates a 140 GHz QPSK transceiver, designed as part of a 4-channel MIMO (multi input multi output) system using 45 nm CMOS SOI technology. A direct conversion architecture is implemented. In the receiver, low noise amplifier (LNA) is followed by a passive double balanced down conversion mixer and baseband amplifier; in the transmitter, an active Gilbert cell IQ modulator is followed by a driver amplifier. The 140 GHz local oscillator (LO) is generated by a $times 9$ multiplier. The measured receiver conversion gain is 18 dB with a 12 GHz 3-dB bandwidth; a narrowband 145 GHz gain notch, unfortunately, limits the usable bandwidth. 3-dB modulation bandwidth of the transmitter is 6–8 GHz. Total power consumption of the 4-channel receiver is 495 mW from a 1 V supply. The 4-channel transmitter consumes 463 mW power from a 1 V supply. We show preliminary single-channel link measurements at an instrument-limited 800 Mb/s data rate.
{"title":"A 140 GHz MIMO Transceiver in 45 nm SOI CMOS","authors":"A. Simsek, Seong-Kyun Kim, M. Rodwell","doi":"10.1109/BCICTS.2018.8550954","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550954","url":null,"abstract":"This paper demonstrates a 140 GHz QPSK transceiver, designed as part of a 4-channel MIMO (multi input multi output) system using 45 nm CMOS SOI technology. A direct conversion architecture is implemented. In the receiver, low noise amplifier (LNA) is followed by a passive double balanced down conversion mixer and baseband amplifier; in the transmitter, an active Gilbert cell IQ modulator is followed by a driver amplifier. The 140 GHz local oscillator (LO) is generated by a $times 9$ multiplier. The measured receiver conversion gain is 18 dB with a 12 GHz 3-dB bandwidth; a narrowband 145 GHz gain notch, unfortunately, limits the usable bandwidth. 3-dB modulation bandwidth of the transmitter is 6–8 GHz. Total power consumption of the 4-channel receiver is 495 mW from a 1 V supply. The 4-channel transmitter consumes 463 mW power from a 1 V supply. We show preliminary single-channel link measurements at an instrument-limited 800 Mb/s data rate.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551096
K. Nakamura, H. Hanawa, K. Horio
Two-dimensional analysis of off-state drain current-drain voltage characteristics in AIGaN/GaN high electron mobility transistors is performed; where two cases with a single passivation layer (SiN or high- $k$ dielectric) and double passivation layers (SiN and high- $k$ dielectric) are compared. It is shown that in the case of double passivation layers, the breakdown voltage is enhanced significantly as compared to the case of SiN single passivation layer when comparing at the same insulator thickness. This is because the electric field around the drain edge of gate is weakened. However, it is lowered remarkably as compared to the case with a high- $k$ single passivation layer even if the first SiN layer is rather thin. Also, in the case of double passivation layers, the breakdown voltage is shown to become close to the case with high- $k$ passivation layer when the relative permittivity of the second passivation layer becomes high and the SiN layer is thin.
{"title":"Analysis of Breakdown Characteristics of AIGaN/GaN HEMTs with Low- $k$ IHigh- $k$ Double Passivation Layers Paper Title","authors":"K. Nakamura, H. Hanawa, K. Horio","doi":"10.1109/BCICTS.2018.8551096","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551096","url":null,"abstract":"Two-dimensional analysis of off-state drain current-drain voltage characteristics in AIGaN/GaN high electron mobility transistors is performed; where two cases with a single passivation layer (SiN or high- $k$ dielectric) and double passivation layers (SiN and high- $k$ dielectric) are compared. It is shown that in the case of double passivation layers, the breakdown voltage is enhanced significantly as compared to the case of SiN single passivation layer when comparing at the same insulator thickness. This is because the electric field around the drain edge of gate is weakened. However, it is lowered remarkably as compared to the case with a high- $k$ single passivation layer even if the first SiN layer is rather thin. Also, in the case of double passivation layers, the breakdown voltage is shown to become close to the case with high- $k$ passivation layer when the relative permittivity of the second passivation layer becomes high and the SiN layer is thin.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128069819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550897
Dylan F. Williams, J. Cheron, B. Jamroz, R. Chamberlin
We review approaches developed at the National Institute of Standards and Technology for on-wafer transistor characterization and model parameter extraction at submillimeter wavelengths and compare them to more common approaches developed for use at lower frequencies. We discuss important improvements in accuracy, approaches to estimating the uncertainty of the procedure, and recent research on further improving these methods.
{"title":"On-Wafer Transistor Characterization to 750 GHz – the Approach, Results, and Pitfalls","authors":"Dylan F. Williams, J. Cheron, B. Jamroz, R. Chamberlin","doi":"10.1109/BCICTS.2018.8550897","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550897","url":null,"abstract":"We review approaches developed at the National Institute of Standards and Technology for on-wafer transistor characterization and model parameter extraction at submillimeter wavelengths and compare them to more common approaches developed for use at lower frequencies. We discuss important improvements in accuracy, approaches to estimating the uncertainty of the procedure, and recent research on further improving these methods.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130329335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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