Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550883
Milad Frounchi, C. Coen, Clifford D. Y. Cheon, N. Lourenco, Wyman Williams, J. Cressler
This paper presents a V-band receiver front-end for spaceborne atmospheric remote sensing. The receiver is implemented in a $mathbf{0.13}mumathbf{m}$ SiGe BiCMOS technology with $f_{T}/f_{MAX}$ of 250/330 GHz and consists of a Dicke switch, an LNA, an image-reject mixer, a frequency multiplier, and an IF amplifier. Across 56–69 GHz, the receiver achieves a mean conversion gain of 65 dB, a minimum noise figure of 4.3/6.1 dB without/with the Dicke switch, and a mean image rejection ratio of 31dB. The high-gain frequency quadrupler allows operation with an LO power as low as −18 dBm. This chip consumes a total DC power of 180 mW and occupies an active area of 3.1 mm2. This is the first reported monolithic receiver front-end for atmospheric measurements across the 60 GHz oxygen spectrum and it achieves the lowest noise figure among similar Si-based Dicke radiometers.
{"title":"A V-Band SiGe Image-Reject Receiver Front-End for Atmospheric Remote Sensing","authors":"Milad Frounchi, C. Coen, Clifford D. Y. Cheon, N. Lourenco, Wyman Williams, J. Cressler","doi":"10.1109/BCICTS.2018.8550883","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550883","url":null,"abstract":"This paper presents a V-band receiver front-end for spaceborne atmospheric remote sensing. The receiver is implemented in a $mathbf{0.13}mumathbf{m}$ SiGe BiCMOS technology with $f_{T}/f_{MAX}$ of 250/330 GHz and consists of a Dicke switch, an LNA, an image-reject mixer, a frequency multiplier, and an IF amplifier. Across 56–69 GHz, the receiver achieves a mean conversion gain of 65 dB, a minimum noise figure of 4.3/6.1 dB without/with the Dicke switch, and a mean image rejection ratio of 31dB. The high-gain frequency quadrupler allows operation with an LO power as low as −18 dBm. This chip consumes a total DC power of 180 mW and occupies an active area of 3.1 mm2. This is the first reported monolithic receiver front-end for atmospheric measurements across the 60 GHz oxygen spectrum and it achieves the lowest noise figure among similar Si-based Dicke radiometers.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121177729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550837
U. Raghunathan, Brian R. Wier, Zachary E. Fleetwood, Michael A. Oakley, V. Jain, J. Cressler
We explore different vertical profile designs with optimized emitter-base (EB) junctions targeting both constant current gain $(beta)$ across temperature and broadened $mathbf{f}_{mathbf{T}}/mathbf{f}_{max}$ curves for improved large-signal linearity. This work explicitly examines achieving a temperature-independent $beta$ via profile design in SiGe HBTs, and explores the limitations using triangular and ledge-based Ge profiles at the EB junction. The effects of base width and the EB junction separation length are also investigated for reduced parasitic capacitance and improved frequency response at low-bias currents. This work presents the underlying theory, along with the measured results for the two optimization targets, both of which should aid in designing circuits with better linearity and stability across bias and temperature corners.
{"title":"Emitter-Base Profile Optimization of SiGe HBTs for Improved Thermal Stability and Frequency Response at Low-Bias Currents","authors":"U. Raghunathan, Brian R. Wier, Zachary E. Fleetwood, Michael A. Oakley, V. Jain, J. Cressler","doi":"10.1109/BCICTS.2018.8550837","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550837","url":null,"abstract":"We explore different vertical profile designs with optimized emitter-base (EB) junctions targeting both constant current gain $(beta)$ across temperature and broadened $mathbf{f}_{mathbf{T}}/mathbf{f}_{max}$ curves for improved large-signal linearity. This work explicitly examines achieving a temperature-independent $beta$ via profile design in SiGe HBTs, and explores the limitations using triangular and ledge-based Ge profiles at the EB junction. The effects of base width and the EB junction separation length are also investigated for reduced parasitic capacitance and improved frequency response at low-bias currents. This work presents the underlying theory, along with the measured results for the two optimization targets, both of which should aid in designing circuits with better linearity and stability across bias and temperature corners.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128646774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551037
Yasuo Saito, T. Aizawa, K. Wasa, Yoshiro Nogami
Plastic mold packaging is proposed as the first solution to make leak proof joinability between the heat spreader and plastic mold by optimization of micro-textures on the spreader. No leaks were detected after gross-leak testing. Vertically-aligned graphitic substrate (VGS) provided the second solution to control thermal spreading and transients from GaN to the spreader. A Copper-laminated VGS with stacking graphene planes in Y and Z-axes significantly reduced the channel temperature and Thermal resistance (Rth) by 40 K and 0.28 K/W than those in Cu-based composite substrate (CCS) even for the same spreader thickness of 1 mm. Since thermal diffusivity for VGS is ten times faster than CCS., temperature difference during ON/OFF intervals was reduced by 18 K between Cu-laminated VGS-packaged and CCS-packaged GaN HEMTs. The time constant of Cu-laminated VGS-packaged GaN HEMT was 2.5 ms, much longer than 0.2 ms.
{"title":"Leak-Proof Packaging for GaN Chip with Controlled Thermal Spreading and Transients","authors":"Yasuo Saito, T. Aizawa, K. Wasa, Yoshiro Nogami","doi":"10.1109/BCICTS.2018.8551037","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551037","url":null,"abstract":"Plastic mold packaging is proposed as the first solution to make leak proof joinability between the heat spreader and plastic mold by optimization of micro-textures on the spreader. No leaks were detected after gross-leak testing. Vertically-aligned graphitic substrate (VGS) provided the second solution to control thermal spreading and transients from GaN to the spreader. A Copper-laminated VGS with stacking graphene planes in Y and Z-axes significantly reduced the channel temperature and Thermal resistance (Rth) by 40 K and 0.28 K/W than those in Cu-based composite substrate (CCS) even for the same spreader thickness of 1 mm. Since thermal diffusivity for VGS is ten times faster than CCS., temperature difference during ON/OFF intervals was reduced by 18 K between Cu-laminated VGS-packaged and CCS-packaged GaN HEMTs. The time constant of Cu-laminated VGS-packaged GaN HEMT was 2.5 ms, much longer than 0.2 ms.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116106527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551151
Venkata N. K. Malladi, Mike Fraser, J. Staudinger, M. Bokatius, Monte Miller
This paper presents a T/R switch with 45 dBm peak power handling capability aimed at 5G massive MIMO RF front end applications. The switch achieves high power handling by using multi-gate FETs in a stacked fashion and by compensating parasitic capacitances that cause imbalanced voltage distribution across the stack. The switch operates from 2–6 GHz and achieves 45 dBm peak power handling, 0.75 dB IL, 30 dB of isolation at 3.5 GHz.
{"title":"A 2–6 GHz, 45 dBm Peak Power T/R SPDT Switch for 5G mMIMO Applications","authors":"Venkata N. K. Malladi, Mike Fraser, J. Staudinger, M. Bokatius, Monte Miller","doi":"10.1109/BCICTS.2018.8551151","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551151","url":null,"abstract":"This paper presents a T/R switch with 45 dBm peak power handling capability aimed at 5G massive MIMO RF front end applications. The switch achieves high power handling by using multi-gate FETs in a stacked fashion and by compensating parasitic capacitances that cause imbalanced voltage distribution across the stack. The switch operates from 2–6 GHz and achieves 45 dBm peak power handling, 0.75 dB IL, 30 dB of isolation at 3.5 GHz.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550923
M. Sakalas, N. Joram, F. Ellinger
This paper presents a 1.5 – 54 GHz high dynamic range low noise amplifier (LNA) and mixer combination MMIC, which is the core component of a monostatic multiple input, multiple output (MIMO) imaging radar receiver system. The circuit is implemented in a $mathbf{0.13} mumathbf{m}$ SiGe BiCMOS process from IHP and occupies a core area of only 0.6 mm2, Controlled feedback, common-base mixer inputs, patterned transmission line grounds and a folded differential distributed amplifier topology were employed to optimize the performance. Ultra-wideband operation from 1.5 to 54 GHz, low noise of $mathbf{NF}_{mathbf{dsb}}=mathbf{4.8 dB}$, high linearity of $mathbf{P}_{mathbf{in},mathbf{1dB}}=-mathbf{1 dBm}$, controlled conversion gain in the range of 0 - 12 dB and a +20 dBm survivability were measured at a DC power consumption of 194 mW. With respect to these core design parameters, the proposed LNA and mixer combination outperforms the state of the art of its class.
{"title":"1.5-54 GHz High Dynamic Range LNA and Mixer Combination for a MIMO Radar Application","authors":"M. Sakalas, N. Joram, F. Ellinger","doi":"10.1109/BCICTS.2018.8550923","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550923","url":null,"abstract":"This paper presents a 1.5 – 54 GHz high dynamic range low noise amplifier (LNA) and mixer combination MMIC, which is the core component of a monostatic multiple input, multiple output (MIMO) imaging radar receiver system. The circuit is implemented in a $mathbf{0.13} mumathbf{m}$ SiGe BiCMOS process from IHP and occupies a core area of only 0.6 mm2, Controlled feedback, common-base mixer inputs, patterned transmission line grounds and a folded differential distributed amplifier topology were employed to optimize the performance. Ultra-wideband operation from 1.5 to 54 GHz, low noise of $mathbf{NF}_{mathbf{dsb}}=mathbf{4.8 dB}$, high linearity of $mathbf{P}_{mathbf{in},mathbf{1dB}}=-mathbf{1 dBm}$, controlled conversion gain in the range of 0 - 12 dB and a +20 dBm survivability were measured at a DC power consumption of 194 mW. With respect to these core design parameters, the proposed LNA and mixer combination outperforms the state of the art of its class.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133927114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550974
S. Khandelwal, Y. Chauhan, Jason Hodges, S. Albahrani
In this paper, we present nonlinear radiofrequency (RF) modeling of Gallium Nitride based high electron mobility transistors (GaN HEMTs) using recently selected industry standard surface-potential-based Advance SPICE Model (ASM) for GaN HEMTs. We describe the key features of ASM GaN model from user perspective. Non-linear RF modeling flow from DC to small-signal to large-signal characteristics is presented for GaN HEMTs.
{"title":"Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited)","authors":"S. Khandelwal, Y. Chauhan, Jason Hodges, S. Albahrani","doi":"10.1109/BCICTS.2018.8550974","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550974","url":null,"abstract":"In this paper, we present nonlinear radiofrequency (RF) modeling of Gallium Nitride based high electron mobility transistors (GaN HEMTs) using recently selected industry standard surface-potential-based Advance SPICE Model (ASM) for GaN HEMTs. We describe the key features of ASM GaN model from user perspective. Non-linear RF modeling flow from DC to small-signal to large-signal characteristics is presented for GaN HEMTs.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123492703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550924
Ahmed S. H. Ahmed, A. Simsek, M. Urteaga, M. Rodwell
We report two 325 GHz series-connected power amplifiers (PAs) using 130 nm InP HBT technology. The unit cell, using two series-connected transistors, produces 8.6 mW at 325 GHz and consumes 243 mW DC power. The PA has a 4.3 dB compressed gain and 2.2% power added efficiency (PAE). Two of these cells are then power-combined, and two further cells are used as driver stages, to form the second design, which produces 11.36 mW at 325 GHz with 9.4 dB compressed gain and 1.09% PAE. The peak small signal gain is 16.6 dB at 325 GHz, and the 3-dB bandwidth is 9 GHz. The total power consumed is 1.12 W and the dimensions including the pads are $0.98 mathbf{mm} times 0.98 mathbf{mm}$.
{"title":"8.6-13.6 mW Series-Connected Power Amplifiers Designed at 325 GHz Using 130 nm InP HBT Technology","authors":"Ahmed S. H. Ahmed, A. Simsek, M. Urteaga, M. Rodwell","doi":"10.1109/BCICTS.2018.8550924","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550924","url":null,"abstract":"We report two 325 GHz series-connected power amplifiers (PAs) using 130 nm InP HBT technology. The unit cell, using two series-connected transistors, produces 8.6 mW at 325 GHz and consumes 243 mW DC power. The PA has a 4.3 dB compressed gain and 2.2% power added efficiency (PAE). Two of these cells are then power-combined, and two further cells are used as driver stages, to form the second design, which produces 11.36 mW at 325 GHz with 9.4 dB compressed gain and 1.09% PAE. The peak small signal gain is 16.6 dB at 325 GHz, and the 3-dB bandwidth is 9 GHz. The total power consumed is 1.12 W and the dimensions including the pads are $0.98 mathbf{mm} times 0.98 mathbf{mm}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125487325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550970
G. Wedel, T. Nardmanrr, M. Schröter
In simulations of III-V devices, convergence issues are often observed when using drift-diffusion and hydrodynamic transport in conjunction with the negative differential mobility model. This paper explains the cause of the problem for each of the two transport models. Furthermore, known measures for achieving convergence and their implications are discussed.
{"title":"On the use of Drift-Diffusion and Hydrodynamic Transport Models for Simulating the Negative Differential Mobility Effect","authors":"G. Wedel, T. Nardmanrr, M. Schröter","doi":"10.1109/BCICTS.2018.8550970","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550970","url":null,"abstract":"In simulations of III-V devices, convergence issues are often observed when using drift-diffusion and hydrodynamic transport in conjunction with the negative differential mobility model. This paper explains the cause of the problem for each of the two transport models. Furthermore, known measures for achieving convergence and their implications are discussed.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121361808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550832
Kang Ning, J. Buckwalter
A single stage, millimeter-wave 2-stack FET power amplifier operates with a peak saturated power of 18.2 dBm and peak PAE of 48.2%. The high PAE results from a proposed $C_{gd}$ neutralization through coupled inductor feedback between the drains of the stacked FETs. The technique reuses the interstage matching shunt inductor to reduce the loss and chip area while improving the PA gain. The PA achieves 13.6 dB gain with a 3 dB bandwidth of 12 GHz at a 2.4-V power supply. The PA is implemented in a 4S-nm SOI CMOS technology using a trap-rich substrate and has an area of $mathbf{520} mumathbf{m}times mathbf{530} mumathbf{m}$. To the author's knowledge, this work demonstrates the highest gain and power added efficiency (PAE) for a single-stage Si-based PA at 28 GHz.
单级毫米波2堆叠FET功率放大器的峰值饱和功率为18.2 dBm，峰值PAE为48.2%。高PAE是通过在堆叠场效应管漏极之间的耦合电感反馈来中和的。该技术采用级间匹配分流电感，在提高增益的同时减小损耗和芯片面积。该放大器在2.4 v电源下实现13.6 dB增益，3db带宽为12 GHz。该PA采用富含陷阱的基板，采用4snm SOI CMOS技术实现，面积为$mathbf{520} mumathbf{m}乘以mathbf{530} mumathbf{m}$。据作者所知，这项工作展示了28ghz单级si基PA的最高增益和功率附加效率(PAE)。
{"title":"A 28-GHz, 18-dBm, 48% PAE Stacked-FET Power Amplifier with Coupled-Inductor Neutralization in 45-nm SOI CMOS","authors":"Kang Ning, J. Buckwalter","doi":"10.1109/BCICTS.2018.8550832","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550832","url":null,"abstract":"A single stage, millimeter-wave 2-stack FET power amplifier operates with a peak saturated power of 18.2 dBm and peak PAE of 48.2%. The high PAE results from a proposed $C_{gd}$ neutralization through coupled inductor feedback between the drains of the stacked FETs. The technique reuses the interstage matching shunt inductor to reduce the loss and chip area while improving the PA gain. The PA achieves 13.6 dB gain with a 3 dB bandwidth of 12 GHz at a 2.4-V power supply. The PA is implemented in a 4S-nm SOI CMOS technology using a trap-rich substrate and has an area of $mathbf{520} mumathbf{m}times mathbf{530} mumathbf{m}$. To the author's knowledge, this work demonstrates the highest gain and power added efficiency (PAE) for a single-stage Si-based PA at 28 GHz.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122631783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551153
Haedong Jang, Z. Mokhti, Björn Herrmann, Richard Wilson
The nonlinear parasitic components of high-power FET devices require tremendous amount of device characterization efforts. The recent nonlinear embedding technique can significantly expedite the design process by removing the time-consuming source/loadpull measurements. This technique is demonstrated using the Angelov model for a 15 W peak power gallium nitride device. The power amplifier design starts from the intrinsic conceptual design and then the external conditions to maintain the intended operation are directly calculated using the nonlinear embedding. This technique is applied to a 9.54 dB back-off asymmetric Doherty power amplifier. 71 % drain efficiency at the peak power of 41.8 dBm and 62.7 % at 32.8 dBm (9 dB back-off) were measured. This technique is further investigated for the linear broadband design space identification. The linearization of the nonlinear intrinsic current source is proposed for the nonlinear embedding. The two dimensional design space is identified by applying the nonlinear embedding to the load modulated continuous-classF3 mode waveforms. The identified design space is applied to the manufacturer model and then the intrinsic waveforms are observed for the intended operation verification.
{"title":"Nonlinear Embedding of FET Devices for High Efficiency Power Amplifier Design","authors":"Haedong Jang, Z. Mokhti, Björn Herrmann, Richard Wilson","doi":"10.1109/BCICTS.2018.8551153","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551153","url":null,"abstract":"The nonlinear parasitic components of high-power FET devices require tremendous amount of device characterization efforts. The recent nonlinear embedding technique can significantly expedite the design process by removing the time-consuming source/loadpull measurements. This technique is demonstrated using the Angelov model for a 15 W peak power gallium nitride device. The power amplifier design starts from the intrinsic conceptual design and then the external conditions to maintain the intended operation are directly calculated using the nonlinear embedding. This technique is applied to a 9.54 dB back-off asymmetric Doherty power amplifier. 71 % drain efficiency at the peak power of 41.8 dBm and 62.7 % at 32.8 dBm (9 dB back-off) were measured. This technique is further investigated for the linear broadband design space identification. The linearization of the nonlinear intrinsic current source is proposed for the nonlinear embedding. The two dimensional design space is identified by applying the nonlinear embedding to the load modulated continuous-classF3 mode waveforms. The identified design space is applied to the manufacturer model and then the intrinsic waveforms are observed for the intended operation verification.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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