Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551062
A. Valdes-Garcia, B. Sadhu, X. Gu, J. Plouchart, M. Yeck, D. Friedman
This paper motivates the need for scaled phased arrays and outlines key challenges for their implementation. Design trade-offs are discussed for important aspects such as beamforming architecture, module-level realization with antennas and packaging, and digital control. Two recently introduced scaled 64-element dual polarized phased array designs are reviewed as implementation examples. (1) A phased array transceiver module operating at 28-GHz supporting 5G applications, and (2) TX and RX phased arrays operating at 94-GHz suitable for backhaul and imaging applications. An outlook for future opportunities with phased array scaling is provided.
{"title":"Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions","authors":"A. Valdes-Garcia, B. Sadhu, X. Gu, J. Plouchart, M. Yeck, D. Friedman","doi":"10.1109/BCICTS.2018.8551062","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551062","url":null,"abstract":"This paper motivates the need for scaled phased arrays and outlines key challenges for their implementation. Design trade-offs are discussed for important aspects such as beamforming architecture, module-level realization with antennas and packaging, and digital control. Two recently introduced scaled 64-element dual polarized phased array designs are reviewed as implementation examples. (1) A phased array transceiver module operating at 28-GHz supporting 5G applications, and (2) TX and RX phased arrays operating at 94-GHz suitable for backhaul and imaging applications. An outlook for future opportunities with phased array scaling is provided.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131709477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550845
P. Parikh, YiFeng Wu, Likun Shen, J. Gritters, T. Hosoda, R. Barr, Kurt V. Smith, K. Shono, J. McKay, H. Clement, S. Chowdhury, S. Yea, Peter Smith, L. McCarthy, R. Birkhahn, P. Zuk, Y. Asai
After successful qualification under JEDEC requirements as well as Automotive (Q101) requirements [1], [2], along with the establishment of intrinsic lifetimes with associated failure modes [2], high voltage GaN is now ramping in converter/inverter applications. Among the key applications, compact & high efficiency (including Titanium class) Power supplies for uses such as high performance gaming & cryptocurrency mining as well as data center power are leading the way [3]. Automotive uses including onboard chargers (uni/bi-directional), dc-dc converters and pole chargers are being designed in. Finally industrial users have adopted GaN for compact Servo drives and PV inverters [4]. This paper will review the design, performance and manufacturability of high voltage GaN, establishment of the highest level of quality and reliability standards and key features that led to market ramp.
{"title":"650 Volt GaN: Highest Quality-Highest Performance Drives Market Ramp","authors":"P. Parikh, YiFeng Wu, Likun Shen, J. Gritters, T. Hosoda, R. Barr, Kurt V. Smith, K. Shono, J. McKay, H. Clement, S. Chowdhury, S. Yea, Peter Smith, L. McCarthy, R. Birkhahn, P. Zuk, Y. Asai","doi":"10.1109/BCICTS.2018.8550845","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550845","url":null,"abstract":"After successful qualification under JEDEC requirements as well as Automotive (Q101) requirements [1], [2], along with the establishment of intrinsic lifetimes with associated failure modes [2], high voltage GaN is now ramping in converter/inverter applications. Among the key applications, compact & high efficiency (including Titanium class) Power supplies for uses such as high performance gaming & cryptocurrency mining as well as data center power are leading the way [3]. Automotive uses including onboard chargers (uni/bi-directional), dc-dc converters and pole chargers are being designed in. Finally industrial users have adopted GaN for compact Servo drives and PV inverters [4]. This paper will review the design, performance and manufacturability of high voltage GaN, establishment of the highest level of quality and reliability standards and key features that led to market ramp.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133592730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551058
J. Weiss
Radio astronomy faces very specific, systematic and environmental challenges regarding signal transport from individual antenna elements to the signal processing station. Here we present how with analog optical links these requirements can be met, specifically for the low-frequency receiver of the Square Kilometre Array (SKA), which will be the world's largest radio telescope when finished. It will comprise more than 100'000 individual antennas, which need to be connected over a distance of up to 10 kilometers.
{"title":"Analog Optical RF-Links for Large Radio Telescopes","authors":"J. Weiss","doi":"10.1109/BCICTS.2018.8551058","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551058","url":null,"abstract":"Radio astronomy faces very specific, systematic and environmental challenges regarding signal transport from individual antenna elements to the signal processing station. Here we present how with analog optical links these requirements can be met, specifically for the low-frequency receiver of the Square Kilometre Array (SKA), which will be the world's largest radio telescope when finished. It will comprise more than 100'000 individual antennas, which need to be connected over a distance of up to 10 kilometers.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551095
S. Schafer, M. Roberg
A novel attenuator/limiter circuit that uses nonlinear GaN epitaxial resistors is presented. The circuit is small, broadband as it does not use any reactive elements, does not use DC bias, and can be integrated on GaN or GaAs with other microwave elements and/or circuits. GaN epitaxial resistors have a saturation current limit which provides a limiting function. Resistive T-and Pi-network attenuators are implemented using GaN epitaxial resistors to limit the total power through the attenuator. A first-order equation of the trade-off between attenuation and flat leakage power is derived. Fabricated circuits show flat leakage powers 0.4 - 10 W with input powers $> mathbf{30 W}$, No noticeable spike-leakage is observed. The limiting attenuator is implemented at the input of an S-band 32 W PA for radar applications, and is shown to protect the input from overdrive while delivering consistent output power after limiter saturation.
{"title":"Monolithic Attenuator/Limiter Using Nonlinear Resistors","authors":"S. Schafer, M. Roberg","doi":"10.1109/BCICTS.2018.8551095","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551095","url":null,"abstract":"A novel attenuator/limiter circuit that uses nonlinear GaN epitaxial resistors is presented. The circuit is small, broadband as it does not use any reactive elements, does not use DC bias, and can be integrated on GaN or GaAs with other microwave elements and/or circuits. GaN epitaxial resistors have a saturation current limit which provides a limiting function. Resistive T-and Pi-network attenuators are implemented using GaN epitaxial resistors to limit the total power through the attenuator. A first-order equation of the trade-off between attenuation and flat leakage power is derived. Fabricated circuits show flat leakage powers 0.4 - 10 W with input powers $> mathbf{30 W}$, No noticeable spike-leakage is observed. The limiting attenuator is implemented at the input of an S-band 32 W PA for radar applications, and is shown to protect the input from overdrive while delivering consistent output power after limiter saturation.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551070
T. Satoh, Ken Osawa, Atsushi Nitta
This paper describes GaN HEMT which was qualified for space applications. For P/L/S-band applications, we have developed high power and high efficiency GaN HEMT which can be used for communication satellite or navigation satellite. The highest power of them is 200W under CW conditions. We also developed high power/gain GaN IM HEMT for X-band applications such as deep space probe satellites or earth observation satellites. These GaN HEMT devices were submitted to space qualification tests that comply with the MIL standard and were confirmed to have sufficient reliability for space applications. We also conducted radiation hardness tests. Radiation resistance is of concern in space applications. Our GaN HEMT was confirmed to have enough robustness for radiation hardness.
本文介绍了适合空间应用的氮化镓HEMT。针对P/L/ s波段的应用，我们开发了高功率，高效率的GaN HEMT，可用于通信卫星或导航卫星。在连续波条件下，其最高功率为200W。我们还开发了用于x波段应用的高功率/增益GaN IM HEMT，如深空探测卫星或地球观测卫星。这些GaN HEMT装置已提交进行符合MIL标准的空间资格测试，并被确认具有足够的空间应用可靠性。我们还进行了辐射硬度测试。在空间应用中，抗辐射是一个值得关注的问题。我们的GaN HEMT被证实具有足够的辐射硬度稳健性。
{"title":"GaN HEMT for Space Applications","authors":"T. Satoh, Ken Osawa, Atsushi Nitta","doi":"10.1109/BCICTS.2018.8551070","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551070","url":null,"abstract":"This paper describes GaN HEMT which was qualified for space applications. For P/L/S-band applications, we have developed high power and high efficiency GaN HEMT which can be used for communication satellite or navigation satellite. The highest power of them is 200W under CW conditions. We also developed high power/gain GaN IM HEMT for X-band applications such as deep space probe satellites or earth observation satellites. These GaN HEMT devices were submitted to space qualification tests that comply with the MIL standard and were confirmed to have sufficient reliability for space applications. We also conducted radiation hardness tests. Radiation resistance is of concern in space applications. Our GaN HEMT was confirmed to have enough robustness for radiation hardness.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134054494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551102
Sri Navaneeth Easwaran, A. Chen, T. Duryea, D. Rollman
Controlling ElectroMagnetic Interference (EMI) is critical in analog circuits. Specifically in transceivers high slew rates of voltages and currents can interfere with other nearby electronics. On one such emerging automotive standard viz. the Peripheral Sensor Interface (PSI5), the electromagnetic emission from the SYNC pulse generated by the PSI5 transceiver can interfere during communication with the sensor. Known techniques of adding external filters or using Spread Spectrum methods to reduce EMI are not applicable due to cost over head and strict timing requirements. Hence a digitally assisted pulse shaping technique to generate a SYNC pulse with different slopes along with an induced analog ramp at the start of the SYNC pulse to meet timing requirement is proposed in order to reduce the EMI. BiCMOS process is the best choice for speed, accuracy and protection at 40V. This design is implemented and successfully validated on a 40V BiCMOS process. The conducted emission limit is $65text{dB}mu text{V}$ at 200KHz, fully operational for 6V to 40V battery and 100mA current limitation during short to ground conditions at the output.
{"title":"40V High Side PSI5 Transceiver with $65text{dB}mu text{V}$ Conducted Emission Level in a BiCMOS Process","authors":"Sri Navaneeth Easwaran, A. Chen, T. Duryea, D. Rollman","doi":"10.1109/BCICTS.2018.8551102","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551102","url":null,"abstract":"Controlling ElectroMagnetic Interference (EMI) is critical in analog circuits. Specifically in transceivers high slew rates of voltages and currents can interfere with other nearby electronics. On one such emerging automotive standard viz. the Peripheral Sensor Interface (PSI5), the electromagnetic emission from the SYNC pulse generated by the PSI5 transceiver can interfere during communication with the sensor. Known techniques of adding external filters or using Spread Spectrum methods to reduce EMI are not applicable due to cost over head and strict timing requirements. Hence a digitally assisted pulse shaping technique to generate a SYNC pulse with different slopes along with an induced analog ramp at the start of the SYNC pulse to meet timing requirement is proposed in order to reduce the EMI. BiCMOS process is the best choice for speed, accuracy and protection at 40V. This design is implemented and successfully validated on a 40V BiCMOS process. The conducted emission limit is $65text{dB}mu text{V}$ at 200KHz, fully operational for 6V to 40V battery and 100mA current limitation during short to ground conditions at the output.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115363406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551057
A. Gauthier, J. Borrel, P. Chevalier, G. Avenier, A. Montagne, M. Juhel, R. Duru, L. Clément, C. Borowiak, M. Buczko, C. Gaquière
This paper deals with the optimization of a Si/SiGe HBT featuring an implanted collector and a DPSA-SEG emitter-base architecture. Arsenic and phosphorous doping species are studied. On the one hand, both silicon defects and dopants profiles control are evaluated and on the other hand, hf performances are presented. Carbon-phosphorous co-implantation is also investigated and a state-of-the-art 450 GHz $f_{text{T}}$ HBT compatible with 55-nm MOSFETs is demonstrated through a device layout study.
{"title":"450 GHz $f_{text{T}}$ SiGe:C HBT Featuring an Implanted Collector in a 55-nm CMOS Node","authors":"A. Gauthier, J. Borrel, P. Chevalier, G. Avenier, A. Montagne, M. Juhel, R. Duru, L. Clément, C. Borowiak, M. Buczko, C. Gaquière","doi":"10.1109/BCICTS.2018.8551057","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551057","url":null,"abstract":"This paper deals with the optimization of a Si/SiGe HBT featuring an implanted collector and a DPSA-SEG emitter-base architecture. Arsenic and phosphorous doping species are studied. On the one hand, both silicon defects and dopants profiles control are evaluated and on the other hand, hf performances are presented. Carbon-phosphorous co-implantation is also investigated and a state-of-the-art 450 GHz $f_{text{T}}$ HBT compatible with 55-nm MOSFETs is demonstrated through a device layout study.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123879297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550990
Alireza Zandieh, P. Schvan, S. Voinigescu
We report the highest sampling-rate single-chip ADC in any semiconductor technology. The circuit uses a 2x time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. The digital outputs of the two sub-ADCs feed an on-die 128-GS/s thermometer-coded DAC whose sole purpose is for testing the ADC. The performance of the ADC-DAC combo, including the SFDR, and the ENOB of 4.1 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128-GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-CML MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to $mathbf{10}mumathbf{m 70}mumathbf{m}$. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is $mathbf{1.1}mathbf{mm}timesmathbf{1.9}mathbf{mm}$.
{"title":"A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications","authors":"Alireza Zandieh, P. Schvan, S. Voinigescu","doi":"10.1109/BCICTS.2018.8550990","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550990","url":null,"abstract":"We report the highest sampling-rate single-chip ADC in any semiconductor technology. The circuit uses a 2x time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. The digital outputs of the two sub-ADCs feed an on-die 128-GS/s thermometer-coded DAC whose sole purpose is for testing the ADC. The performance of the ADC-DAC combo, including the SFDR, and the ENOB of 4.1 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128-GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-CML MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to $mathbf{10}mumathbf{m 70}mumathbf{m}$. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is $mathbf{1.1}mathbf{mm}timesmathbf{1.9}mathbf{mm}$.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127680330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8551125
Steven Callender, W. Shin, Hyung-Jin Lee, S. Pellerano, C. Hull
As next-generation communication systems continue to push to higher operating frequencies, one thing that has grown more uncertain is the technology node which is most suitable for implementing these systems. FinFET CMOS is a viable candidate, offering high-density and low-leakage digital transistors. However, the millimeter-wave (mmWave) capabilities of these devices remain relatively unknown by many. In this paper, we assess the mmWave performance of a FinFET process and discuss the key challenges to mmWave design in deeply-scaled technologies along with design techniques and insight to overcome such challenges. We also demonstrate the suitability of modern FinFET devices for the design of energy-efficient mmWave systems as demonstrated by a 75GHz LNA and PA implemented in Intel's 22FFL process which achieve state-of-art performance.
{"title":"FinFET for mm Wave - Technology and Circuit Design Challenges","authors":"Steven Callender, W. Shin, Hyung-Jin Lee, S. Pellerano, C. Hull","doi":"10.1109/BCICTS.2018.8551125","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8551125","url":null,"abstract":"As next-generation communication systems continue to push to higher operating frequencies, one thing that has grown more uncertain is the technology node which is most suitable for implementing these systems. FinFET CMOS is a viable candidate, offering high-density and low-leakage digital transistors. However, the millimeter-wave (mmWave) capabilities of these devices remain relatively unknown by many. In this paper, we assess the mmWave performance of a FinFET process and discuss the key challenges to mmWave design in deeply-scaled technologies along with design techniques and insight to overcome such challenges. We also demonstrate the suitability of modern FinFET devices for the design of energy-efficient mmWave systems as demonstrated by a 75GHz LNA and PA implemented in Intel's 22FFL process which achieve state-of-art performance.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"89 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129780160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/BCICTS.2018.8550856
Paul Stärke, V. Riess, C. Carta, F. Ellinger
This work presents an amplifier for mm-wave applications reaching a peak gain of 26 dB with a usable bandwidth of up to 98 GHz. The design is optimized for an operating frequency between 100 GHz to 200 GHz and can deliver medium output power levels up to 3 dBm. The total dc power consumption is 70mW. To allow the use in ultra wideband communication systems the group delay variation is kept below 5 ps. As additional feature a power detector with a large dynamic range, covering the linear region of the amplifier, is integrated at the output to allow a direct measurement of the outgoing signal levels. The circuit is fabricated in a 130 nm SiGe BiCMOS process with $mathbf{f}_{max}$ of 500 GHz and covers a core area of only 0.15 mm2.
{"title":"Wideband Amplifier with Integrated Power Detector for 100 GHz to 200 GHz mm-Wave Applications","authors":"Paul Stärke, V. Riess, C. Carta, F. Ellinger","doi":"10.1109/BCICTS.2018.8550856","DOIUrl":"https://doi.org/10.1109/BCICTS.2018.8550856","url":null,"abstract":"This work presents an amplifier for mm-wave applications reaching a peak gain of 26 dB with a usable bandwidth of up to 98 GHz. The design is optimized for an operating frequency between 100 GHz to 200 GHz and can deliver medium output power levels up to 3 dBm. The total dc power consumption is 70mW. To allow the use in ultra wideband communication systems the group delay variation is kept below 5 ps. As additional feature a power detector with a large dynamic range, covering the linear region of the amplifier, is integrated at the output to allow a direct measurement of the outgoing signal levels. The circuit is fabricated in a 130 nm SiGe BiCMOS process with $mathbf{f}_{max}$ of 500 GHz and covers a core area of only 0.15 mm2.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129957393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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