Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118049
Ishita Bansal, S. K. Roy, K. Basu, P. Sen
Imaging of microparticles or biological entities inside microchannels provide informative data, given that the image quality is good and at par with the speed of the moving object. High-speed camera has been a boon for decades to capture fast moving objects, both in macro as well as micro world. This work reports a flash imaging system developed to image moving particles, thereby removing the need of conventional high-speed camera systems.
{"title":"Flash imaging for microfluidics","authors":"Ishita Bansal, S. K. Roy, K. Basu, P. Sen","doi":"10.1109/ICEE56203.2022.10118049","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118049","url":null,"abstract":"Imaging of microparticles or biological entities inside microchannels provide informative data, given that the image quality is good and at par with the speed of the moving object. High-speed camera has been a boon for decades to capture fast moving objects, both in macro as well as micro world. This work reports a flash imaging system developed to image moving particles, thereby removing the need of conventional high-speed camera systems.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117754
Divya Dubey, M. Goswami, Kavindra Kandpal
This work presents a 5T −2C pixel circuit based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) for flexible displays utilizing improved stacked voltage-programmed pixel circuit topology. Due to a low operating voltage of 5 V and reduced programming time of 8 $mumathrm{s}$, the proposed circuit finds its application in large screen HD displays as it can provide a very high frame rate of 120 Hz. Moreover, a good compensation ability of the proposed circuit against the threshold voltage variations of the driving TFT in the range of −0.2 volts to 2 volts from the nominal voltage of 0.7 volts, makes it suitable for flexible AMOLED displays. The error in organic light emitting diode (OLE D) current is within 0.4% over the range of data voltage (3.8 V to 6 V) when the substrate is subjected to both compressive and tensile strains of $pm 0.3$ % and within 10% due to threshold voltage variations under electrical stress. The adapted SPICE level-3 flexible TFT model efficiently captures the variations in threshold voltage due to mechanical as well as electrical stress. As a result, the proposed 5$T$2C pixel circuit reveals good performance for applications in low-voltage flexible displays.
{"title":"Design of a Low-Voltage and Reduced Programming cycle AMOLED Pixel Circuit using IGZO TFTs","authors":"Divya Dubey, M. Goswami, Kavindra Kandpal","doi":"10.1109/ICEE56203.2022.10117754","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117754","url":null,"abstract":"This work presents a 5T −2C pixel circuit based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) for flexible displays utilizing improved stacked voltage-programmed pixel circuit topology. Due to a low operating voltage of 5 V and reduced programming time of 8 $mumathrm{s}$, the proposed circuit finds its application in large screen HD displays as it can provide a very high frame rate of 120 Hz. Moreover, a good compensation ability of the proposed circuit against the threshold voltage variations of the driving TFT in the range of −0.2 volts to 2 volts from the nominal voltage of 0.7 volts, makes it suitable for flexible AMOLED displays. The error in organic light emitting diode (OLE D) current is within 0.4% over the range of data voltage (3.8 V to 6 V) when the substrate is subjected to both compressive and tensile strains of $pm 0.3$ % and within 10% due to threshold voltage variations under electrical stress. The adapted SPICE level-3 flexible TFT model efficiently captures the variations in threshold voltage due to mechanical as well as electrical stress. As a result, the proposed 5$T$2C pixel circuit reveals good performance for applications in low-voltage flexible displays.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115636689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118202
K. Yadav, N. Ray
We use first-principles Density Functional Theory (DFT) to investigate the hydrogen adsorption on and diffusion through a metallic monolayer of Aluminum, also referred to as Aluminene. The lowest energy structure is a buckled honeycomb lattice, and the electronic band structure reveals the metallic nature of this monolayer. We establish the dynamical stability of free-standing buckled Aluminene using phonon dispersion, which shows no instabilities. We show that the hydrogen atom prefers to adsorb at the centre of the honeycomb ring, or the H -site. A small stabilizing effect (~0.00 e V) is observed with slight off-centering and bond tilting. The monolayer can block the diffusion of hydrogen molecule from one side to the other with a weak energy barrier (0.68 e V). However, the atom encounters two barriers of same height separated by a metastable state. The Aluminum monolayer may thus find applications in hydrogen storage as well as sensors to detect hydrogen,
我们使用第一性原理密度泛函理论(DFT)来研究氢在金属单层铝(也称为铝烯)上的吸附和扩散。能量最低的结构是一个弯曲的蜂窝晶格，电子能带结构揭示了这种单层的金属性质。利用声子色散建立了独立屈曲铝烯的动力学稳定性，证明其不存在不稳定性。我们发现氢原子更倾向于吸附在蜂窝环的中心或H位。在轻微偏离中心和键倾斜的情况下，观察到一个小的稳定效应(~0.00 e V)。单分子层可以用弱能垒(0.68 e V)阻止氢分子从一侧向另一侧扩散，但原子会遇到两个以亚稳态分隔的相同高度的能垒。因此，铝单分子层可能会在储氢和检测氢的传感器中找到应用，
{"title":"Hydrogen Adsorption on Two Dimensional Aluminene","authors":"K. Yadav, N. Ray","doi":"10.1109/ICEE56203.2022.10118202","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118202","url":null,"abstract":"We use first-principles Density Functional Theory (DFT) to investigate the hydrogen adsorption on and diffusion through a metallic monolayer of Aluminum, also referred to as Aluminene. The lowest energy structure is a buckled honeycomb lattice, and the electronic band structure reveals the metallic nature of this monolayer. We establish the dynamical stability of free-standing buckled Aluminene using phonon dispersion, which shows no instabilities. We show that the hydrogen atom prefers to adsorb at the centre of the honeycomb ring, or the H -site. A small stabilizing effect (~0.00 e V) is observed with slight off-centering and bond tilting. The monolayer can block the diffusion of hydrogen molecule from one side to the other with a weak energy barrier (0.68 e V). However, the atom encounters two barriers of same height separated by a metastable state. The Aluminum monolayer may thus find applications in hydrogen storage as well as sensors to detect hydrogen,","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123326745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117750
Samik Mallik, S. P. Verma, Subharthi Saha, Richeek Nayak, P. K. Guha, D. Goswami
This paper emphasized the charge transport mechanism of a low-powered OFET fabricated using barium titanate (BaTi03) nanocrystal as the dielectric material. These OFET -based devices are highly stable in the air and exhibited significantly much higher carrier mobility. In general, the high temperature processing of BaTi03 proclaims excellent ferro electricity due to the AB03-type perovskite structure. However, the approach towards the very low temperature synthesis of BaTi03 displayed a hexagonal phase in an amorphous matrix. The inclusion of hexagonal barium titanate nanocrystals significantly lowered the surface roughness of the entire bi-Iayer dielectric system. An extensive temperature- dependent study ranging from 50 K to 350 K has been carried out, and the variation of carrier mobility follows the Arrhenius behavior over the temperature range, supporting the hopping assisted charge carrier transport. Interestingly, two distinct regions are seen over the Arrhenius plot. This phenomenon has been explained by the structural phase change of hexagonal barium titanate at around 138 K, reflected in the large threshold voltage shift with temperature. Furthermore, we have calculated the activation energies for the temperature ranging from 150 K to 300 K and obtained the value of 9.47 meV, which reduces to 3.44 meV for the temperature ranging from 25 K to 125 K. Such observation has been explained in terms of different charge transport mechanism at the grain boundaries.
{"title":"Effect of measurement temperature on the charge transport behavior in temperature sensitive ferroelectric dielectric-based organic field-effect transistors","authors":"Samik Mallik, S. P. Verma, Subharthi Saha, Richeek Nayak, P. K. Guha, D. Goswami","doi":"10.1109/ICEE56203.2022.10117750","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117750","url":null,"abstract":"This paper emphasized the charge transport mechanism of a low-powered OFET fabricated using barium titanate (BaTi03) nanocrystal as the dielectric material. These OFET -based devices are highly stable in the air and exhibited significantly much higher carrier mobility. In general, the high temperature processing of BaTi03 proclaims excellent ferro electricity due to the AB03-type perovskite structure. However, the approach towards the very low temperature synthesis of BaTi03 displayed a hexagonal phase in an amorphous matrix. The inclusion of hexagonal barium titanate nanocrystals significantly lowered the surface roughness of the entire bi-Iayer dielectric system. An extensive temperature- dependent study ranging from 50 K to 350 K has been carried out, and the variation of carrier mobility follows the Arrhenius behavior over the temperature range, supporting the hopping assisted charge carrier transport. Interestingly, two distinct regions are seen over the Arrhenius plot. This phenomenon has been explained by the structural phase change of hexagonal barium titanate at around 138 K, reflected in the large threshold voltage shift with temperature. Furthermore, we have calculated the activation energies for the temperature ranging from 150 K to 300 K and obtained the value of 9.47 meV, which reduces to 3.44 meV for the temperature ranging from 25 K to 125 K. Such observation has been explained in terms of different charge transport mechanism at the grain boundaries.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121567008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117789
Jyoti Patel, N. Bagga, Shashank Banchhor, S. Dasgupta
In FinFETs, the source/drain (S/D) extension regions play a vital role in the device's performance as it modulates the overall parasitic capacitance. Thus, placing a symmetric/asymmetric spacer in the FinFET changes the overall capacitance. This paper demonstrated the impact of putting the symmetric and asymmetric spacer in multi-fin FinFET. We kept the same fin length while changing the source-side and drain-side spacer lengths. The impact of an asymmetric spacer is investigated on the device characteristics, such as ON current, gate capacitance, transconductance, etc., for single and multi-fin configurations. Further, we designed a basic common source (CS) amplifier with resistive load and investigated the circuit level performance using spacer optimization through extensive TCAD simulations. The optimum device performance is observed for asymmetric source and drain spacer length (LDSP 16nm and Lssp = 4nm) for three fins FinFET.
{"title":"Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation","authors":"Jyoti Patel, N. Bagga, Shashank Banchhor, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10117789","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117789","url":null,"abstract":"In FinFETs, the source/drain (S/D) extension regions play a vital role in the device's performance as it modulates the overall parasitic capacitance. Thus, placing a symmetric/asymmetric spacer in the FinFET changes the overall capacitance. This paper demonstrated the impact of putting the symmetric and asymmetric spacer in multi-fin FinFET. We kept the same fin length while changing the source-side and drain-side spacer lengths. The impact of an asymmetric spacer is investigated on the device characteristics, such as ON current, gate capacitance, transconductance, etc., for single and multi-fin configurations. Further, we designed a basic common source (CS) amplifier with resistive load and investigated the circuit level performance using spacer optimization through extensive TCAD simulations. The optimum device performance is observed for asymmetric source and drain spacer length (LDSP 16nm and Lssp = 4nm) for three fins FinFET.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117915
C. Jha, Alireza Mahzoon, R. Drechsler
Adders are implemented using a wide variety of architectures. These architectures have been extensively studied for digital IC-based implementations. In recent years, in-memory computing has gained interest owing to the benefits it provides in terms of both energy and performance as compared to conventional von Neumann computing. In this work, we for the first time investigate various adder architectures for in-memory computing using the memristor aided logic (MAGIC) design style for memristors. We analyze seven different adder architectures for bit-widths: 8-bit, 16-bit, 32-bit, and 64-bit. We have used the state-of-the-art SIMPLER tool for performing the mapping of these adders to memristor crossbars. We show that serial prefix adders are better suitable for IMC using the MAGIC design style as compared to the widely used ripple carry adder. The adder designs and the mapping will be made open source at https://github.com/agra-uni-bremen/icee2022-magic-adder-lib, to promote further research in the direction.
{"title":"Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style","authors":"C. Jha, Alireza Mahzoon, R. Drechsler","doi":"10.1109/ICEE56203.2022.10117915","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117915","url":null,"abstract":"Adders are implemented using a wide variety of architectures. These architectures have been extensively studied for digital IC-based implementations. In recent years, in-memory computing has gained interest owing to the benefits it provides in terms of both energy and performance as compared to conventional von Neumann computing. In this work, we for the first time investigate various adder architectures for in-memory computing using the memristor aided logic (MAGIC) design style for memristors. We analyze seven different adder architectures for bit-widths: 8-bit, 16-bit, 32-bit, and 64-bit. We have used the state-of-the-art SIMPLER tool for performing the mapping of these adders to memristor crossbars. We show that serial prefix adders are better suitable for IMC using the MAGIC design style as compared to the widely used ripple carry adder. The adder designs and the mapping will be made open source at https://github.com/agra-uni-bremen/icee2022-magic-adder-lib, to promote further research in the direction.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117629
Vidur Rai, Yi Zhu, K. Vora, L. Fu, H. Tan, C. Jagadish
Nanowire devices have long been proposed as an efficient alternative to their planar counterparts for different optoelectronic applications. Unfortunately, challenges related to the growth and characterization of doping and p-n junction formation in nanowire devices (along axial or radial axis) have significantly impeded their development. The problems are further amplified if a p-n junction has to be implemented radially. Therefore, even though radial junction devices are expected to be on par with their axial junction counterparts, there are minimal reports on high-performance radial junction nanowire optoelectronic devices. This paper summarizes our recent results on the simulation and fabrication of radial junction nanowire solar cells and photodetectors, which have shown unprecedented performance and clearly demonstrate the importance of radial junction for optoelectronic applications. Our simulation results show that the proposed radial junction device is both optically and electrically optimal for solar cell and photodetector applications, especially if the absorber quality is extremely low. The radial junction nanowire solar cells could achieve a 17.2% efficiency, whereas the unbiased radial junction photodetector could show sensitivity down to a single photon level using an absorber with a lifetime of less than 50 ps. In comparison, the axial junction planar device made using same substrate as absorber showed less than 1 % solar cell efficiency and almost no photodetection at 0 V. This study is conclusive experimental proof of the superiority of radial junction nanowire devices over their thin film or axial junction counterparts, especially when absorber lifetime is extremely low. The proposed device holds huge promise for III-V based photovoltaics and photodetectors.
{"title":"Pushing limits of photovoltaics and photodetection using radial junction nanowire devices","authors":"Vidur Rai, Yi Zhu, K. Vora, L. Fu, H. Tan, C. Jagadish","doi":"10.1109/ICEE56203.2022.10117629","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117629","url":null,"abstract":"Nanowire devices have long been proposed as an efficient alternative to their planar counterparts for different optoelectronic applications. Unfortunately, challenges related to the growth and characterization of doping and p-n junction formation in nanowire devices (along axial or radial axis) have significantly impeded their development. The problems are further amplified if a p-n junction has to be implemented radially. Therefore, even though radial junction devices are expected to be on par with their axial junction counterparts, there are minimal reports on high-performance radial junction nanowire optoelectronic devices. This paper summarizes our recent results on the simulation and fabrication of radial junction nanowire solar cells and photodetectors, which have shown unprecedented performance and clearly demonstrate the importance of radial junction for optoelectronic applications. Our simulation results show that the proposed radial junction device is both optically and electrically optimal for solar cell and photodetector applications, especially if the absorber quality is extremely low. The radial junction nanowire solar cells could achieve a 17.2% efficiency, whereas the unbiased radial junction photodetector could show sensitivity down to a single photon level using an absorber with a lifetime of less than 50 ps. In comparison, the axial junction planar device made using same substrate as absorber showed less than 1 % solar cell efficiency and almost no photodetection at 0 V. This study is conclusive experimental proof of the superiority of radial junction nanowire devices over their thin film or axial junction counterparts, especially when absorber lifetime is extremely low. The proposed device holds huge promise for III-V based photovoltaics and photodetectors.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117683
Sunil Rathore, Shashank Banchhor, Rajeewa Kumar Jaisawal, Ankit Dixit, P. Kondekar, N. Bagga
The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(mathrm{R}_{text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.
{"title":"Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET","authors":"Sunil Rathore, Shashank Banchhor, Rajeewa Kumar Jaisawal, Ankit Dixit, P. Kondekar, N. Bagga","doi":"10.1109/ICEE56203.2022.10117683","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117683","url":null,"abstract":"The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(mathrm{R}_{text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129582018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117997
S. K. Mondal, S. Dasgupta
Two dimensional (2D) semiconductors combine the advantages of both oxide and organic semiconductor world, namely, high carrier mobility, environmental stability, as well as room temperature processability, flexibility and the availability of both high carrier mobility n- and p-type semiconductor variants. However, for their realization in flexible, wearable electronics, high throughput solution processing techniques, such as printing is essential. However, when solution processed, the performance of the devices deteriorates substantially due to huge inter-flake resistance. To overcome this challenge, here we propose and demonstrate an unconventional thin film transistor (TFT) device architecture which can circumvent the shortcoming of large inter-flake resistance by transforming the TFTs into predominantly intra-flake transport edge-FETs. Using this edge-FET device architecture, here we present TFTs printed from chemically exfoliated WS2 and MoSe2 inks, with 106 µA/µm and 25 µA/µm width-normalized, On-state current density, respectively. On the other hand, the maximum On-Off ratio observed in these printed TFTs have also been large, as high as 107 has been recorded, which is surely a rarity in solution-processed 2D electronics. In addition, a tunable channel capacitance mediated subthermionic transport with minimum subthreshold slope of 36 mV/dec has also been observed.
{"title":"Inkjet-printed WS2 and MoSe2 transistors with edge-FET architecture and near-vertical electronic transport","authors":"S. K. Mondal, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10117997","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117997","url":null,"abstract":"Two dimensional (2D) semiconductors combine the advantages of both oxide and organic semiconductor world, namely, high carrier mobility, environmental stability, as well as room temperature processability, flexibility and the availability of both high carrier mobility n- and p-type semiconductor variants. However, for their realization in flexible, wearable electronics, high throughput solution processing techniques, such as printing is essential. However, when solution processed, the performance of the devices deteriorates substantially due to huge inter-flake resistance. To overcome this challenge, here we propose and demonstrate an unconventional thin film transistor (TFT) device architecture which can circumvent the shortcoming of large inter-flake resistance by transforming the TFTs into predominantly intra-flake transport edge-FETs. Using this edge-FET device architecture, here we present TFTs printed from chemically exfoliated WS2 and MoSe2 inks, with 106 µA/µm and 25 µA/µm width-normalized, On-state current density, respectively. On the other hand, the maximum On-Off ratio observed in these printed TFTs have also been large, as high as 107 has been recorded, which is surely a rarity in solution-processed 2D electronics. In addition, a tunable channel capacitance mediated subthermionic transport with minimum subthreshold slope of 36 mV/dec has also been observed.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117787
Utkarsh Pandey, Nilashis Pal, B. Pal
Li-Alumina (LA) Ion-conducting dielectric thin film has been prepared through the low-cost sol-gel method and is prosperously use to fabricate the metal-oxide based thin-film transistor (MOTFT). This MOTFT shows the high device performance at very low operating voltage (2V). Li-Alumina thin film shows a very high insulating nature due to the high band-gap of the material. Furthermore, because of the Li+ ion conduction a thin film LA, can be has a very high areal capacitance and may be used as a gate dielectric for low operating voltage metal oxide TFTs. Besides, thin film of LA gives low surface roughness due to its amorphous nature resulting decrease in the gate leakage current in TFT. Also, Li-Alumina dielectric has strong compatibility with the SnO2 semiconducting channel in TFT. A SnO2 thin film has been deposited on the top of the Li-Alumina dielectric layer by the solution-processed technique in the top contact bottom gate TFT architecture that works as semiconductor channel of the device. To saturate the drain current in this TFT, only 2.0 V or less drain voltage (VD) is required, with a gate bias of 2.0 V. The obtained value of threshold voltage Vth), carrier mobility (μ) and On/Off ratio of this device are 0.9 V, 1 cm2V-1s-1 and 1.1 x 102. For the application of this TFT as pressure sensor, a piezoelectric material (PVDF-HFP) thin film has been fabricated on the top of the device, that works as a back gate in the device. Channel current of this TFT can be modulated by applying pressure on the PVDF-HFP thin film. Hence, this device works as piezoelectric back-contacted TFT that can also be considered TFT as a pressure sensor. Additionally, this metal oxide based pressure sensor shows excellent performance in terms of the sensitivity, linearity and response time of the device.
{"title":"Low voltage metal oxide TFT with back-contacted piezoelectric PVDF-HFP coating for pressure sensing applications","authors":"Utkarsh Pandey, Nilashis Pal, B. Pal","doi":"10.1109/ICEE56203.2022.10117787","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117787","url":null,"abstract":"Li-Alumina (LA) Ion-conducting dielectric thin film has been prepared through the low-cost sol-gel method and is prosperously use to fabricate the metal-oxide based thin-film transistor (MOTFT). This MOTFT shows the high device performance at very low operating voltage (2V). Li-Alumina thin film shows a very high insulating nature due to the high band-gap of the material. Furthermore, because of the Li+ ion conduction a thin film LA, can be has a very high areal capacitance and may be used as a gate dielectric for low operating voltage metal oxide TFTs. Besides, thin film of LA gives low surface roughness due to its amorphous nature resulting decrease in the gate leakage current in TFT. Also, Li-Alumina dielectric has strong compatibility with the SnO2 semiconducting channel in TFT. A SnO2 thin film has been deposited on the top of the Li-Alumina dielectric layer by the solution-processed technique in the top contact bottom gate TFT architecture that works as semiconductor channel of the device. To saturate the drain current in this TFT, only 2.0 V or less drain voltage (VD) is required, with a gate bias of 2.0 V. The obtained value of threshold voltage Vth), carrier mobility (μ) and On/Off ratio of this device are 0.9 V, 1 cm2V-1s-1 and 1.1 x 102. For the application of this TFT as pressure sensor, a piezoelectric material (PVDF-HFP) thin film has been fabricated on the top of the device, that works as a back gate in the device. Channel current of this TFT can be modulated by applying pressure on the PVDF-HFP thin film. Hence, this device works as piezoelectric back-contacted TFT that can also be considered TFT as a pressure sensor. Additionally, this metal oxide based pressure sensor shows excellent performance in terms of the sensitivity, linearity and response time of the device.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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