Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117750
Samik Mallik, S. P. Verma, Subharthi Saha, Richeek Nayak, P. K. Guha, D. Goswami
This paper emphasized the charge transport mechanism of a low-powered OFET fabricated using barium titanate (BaTi03) nanocrystal as the dielectric material. These OFET -based devices are highly stable in the air and exhibited significantly much higher carrier mobility. In general, the high temperature processing of BaTi03 proclaims excellent ferro electricity due to the AB03-type perovskite structure. However, the approach towards the very low temperature synthesis of BaTi03 displayed a hexagonal phase in an amorphous matrix. The inclusion of hexagonal barium titanate nanocrystals significantly lowered the surface roughness of the entire bi-Iayer dielectric system. An extensive temperature- dependent study ranging from 50 K to 350 K has been carried out, and the variation of carrier mobility follows the Arrhenius behavior over the temperature range, supporting the hopping assisted charge carrier transport. Interestingly, two distinct regions are seen over the Arrhenius plot. This phenomenon has been explained by the structural phase change of hexagonal barium titanate at around 138 K, reflected in the large threshold voltage shift with temperature. Furthermore, we have calculated the activation energies for the temperature ranging from 150 K to 300 K and obtained the value of 9.47 meV, which reduces to 3.44 meV for the temperature ranging from 25 K to 125 K. Such observation has been explained in terms of different charge transport mechanism at the grain boundaries.
{"title":"Effect of measurement temperature on the charge transport behavior in temperature sensitive ferroelectric dielectric-based organic field-effect transistors","authors":"Samik Mallik, S. P. Verma, Subharthi Saha, Richeek Nayak, P. K. Guha, D. Goswami","doi":"10.1109/ICEE56203.2022.10117750","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117750","url":null,"abstract":"This paper emphasized the charge transport mechanism of a low-powered OFET fabricated using barium titanate (BaTi03) nanocrystal as the dielectric material. These OFET -based devices are highly stable in the air and exhibited significantly much higher carrier mobility. In general, the high temperature processing of BaTi03 proclaims excellent ferro electricity due to the AB03-type perovskite structure. However, the approach towards the very low temperature synthesis of BaTi03 displayed a hexagonal phase in an amorphous matrix. The inclusion of hexagonal barium titanate nanocrystals significantly lowered the surface roughness of the entire bi-Iayer dielectric system. An extensive temperature- dependent study ranging from 50 K to 350 K has been carried out, and the variation of carrier mobility follows the Arrhenius behavior over the temperature range, supporting the hopping assisted charge carrier transport. Interestingly, two distinct regions are seen over the Arrhenius plot. This phenomenon has been explained by the structural phase change of hexagonal barium titanate at around 138 K, reflected in the large threshold voltage shift with temperature. Furthermore, we have calculated the activation energies for the temperature ranging from 150 K to 300 K and obtained the value of 9.47 meV, which reduces to 3.44 meV for the temperature ranging from 25 K to 125 K. Such observation has been explained in terms of different charge transport mechanism at the grain boundaries.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121567008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117837
Eklavy Vashist, Souvik Ghosh, Ambarish Ghosh
In addition to the nanoscale electric field enhancement in plasmonic structures, there is an increase in the local temperature at the nanoparticle surface due to light absorption at resonance, resulting in Thermoplasmonics effects. Therefore, understanding and quantifying the local heating and resultant effects with nanoscale spatial resolution is crucial for engineering plasmonic devices for various applications. Here we report plasmonic heating of Au nanoparticles using a resonant light illumination and an estimation of associated temperature rise using Nitrogen-Vacancy (NV) centers in nanodiamonds (NDs). A custom-built wide field measurement setup detects and analyses the modulation of fluorescence spectra from the NDs close to the plasmonic hotspots. The plasmonic resonance absorption in Au nanoparticles and associated local heating is also studied using COMSOL Multiphysics which matches closely with our experimental results and validates our measurement system. This setup allows to make a thermal map of the system without being limited by diffraction and can be extended to other systems.
{"title":"Quantum sensing of temperature increase due to thermoplasmonic effects using fluorescent nanodiamonds","authors":"Eklavy Vashist, Souvik Ghosh, Ambarish Ghosh","doi":"10.1109/ICEE56203.2022.10117837","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117837","url":null,"abstract":"In addition to the nanoscale electric field enhancement in plasmonic structures, there is an increase in the local temperature at the nanoparticle surface due to light absorption at resonance, resulting in Thermoplasmonics effects. Therefore, understanding and quantifying the local heating and resultant effects with nanoscale spatial resolution is crucial for engineering plasmonic devices for various applications. Here we report plasmonic heating of Au nanoparticles using a resonant light illumination and an estimation of associated temperature rise using Nitrogen-Vacancy (NV) centers in nanodiamonds (NDs). A custom-built wide field measurement setup detects and analyses the modulation of fluorescence spectra from the NDs close to the plasmonic hotspots. The plasmonic resonance absorption in Au nanoparticles and associated local heating is also studied using COMSOL Multiphysics which matches closely with our experimental results and validates our measurement system. This setup allows to make a thermal map of the system without being limited by diffraction and can be extended to other systems.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128378754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117683
Sunil Rathore, Shashank Banchhor, Rajeewa Kumar Jaisawal, Ankit Dixit, P. Kondekar, N. Bagga
The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(mathrm{R}_{text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.
{"title":"Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET","authors":"Sunil Rathore, Shashank Banchhor, Rajeewa Kumar Jaisawal, Ankit Dixit, P. Kondekar, N. Bagga","doi":"10.1109/ICEE56203.2022.10117683","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117683","url":null,"abstract":"The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances $(mathrm{R}_{text{th DSG}})$. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129582018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118117
Debaleena Majumder, Ambarish Ghosh
The highly lossy nature of the conventional noble metals in the infrared region limits their implementation to the UV-Vis part of the electromagnetic spectrum. Hence, the necessity for a lossless alternate plasmonic material having large negative permittivity in the IR regime has paved the way for the exploration of transparent conducting oxides such as Aluminium doped Zinc Oxide. The mid-IR plasmonic response has a strong dependence on diverse tuneable parameters, the most efficient and flexible being the geometrical parameters. Detailed theoretical investigations using COMSOL Multiphysics can obliterate the requirement of complex fabrication efforts to understand the dynamic tunability of the optical signal. This study is motivated by the systematic investigation of the effect of shape factors on the linear optical properties of three different AZO based plasmonic planar nanostructures namely Nonamer, Dipole, and BowTie nanoantennas. A comparative matrix for various configuration sensitive optical modes investigated by this work provides a unique possibility to encompass the idea for exploration and design of mid-IR photodetection and sensor-based devices.
{"title":"Optical tunability of mid-IR based AZO nano geometries through the characterisation of plasmon induced resonance modes","authors":"Debaleena Majumder, Ambarish Ghosh","doi":"10.1109/ICEE56203.2022.10118117","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118117","url":null,"abstract":"The highly lossy nature of the conventional noble metals in the infrared region limits their implementation to the UV-Vis part of the electromagnetic spectrum. Hence, the necessity for a lossless alternate plasmonic material having large negative permittivity in the IR regime has paved the way for the exploration of transparent conducting oxides such as Aluminium doped Zinc Oxide. The mid-IR plasmonic response has a strong dependence on diverse tuneable parameters, the most efficient and flexible being the geometrical parameters. Detailed theoretical investigations using COMSOL Multiphysics can obliterate the requirement of complex fabrication efforts to understand the dynamic tunability of the optical signal. This study is motivated by the systematic investigation of the effect of shape factors on the linear optical properties of three different AZO based plasmonic planar nanostructures namely Nonamer, Dipole, and BowTie nanoantennas. A comparative matrix for various configuration sensitive optical modes investigated by this work provides a unique possibility to encompass the idea for exploration and design of mid-IR photodetection and sensor-based devices.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127920680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117997
S. K. Mondal, S. Dasgupta
Two dimensional (2D) semiconductors combine the advantages of both oxide and organic semiconductor world, namely, high carrier mobility, environmental stability, as well as room temperature processability, flexibility and the availability of both high carrier mobility n- and p-type semiconductor variants. However, for their realization in flexible, wearable electronics, high throughput solution processing techniques, such as printing is essential. However, when solution processed, the performance of the devices deteriorates substantially due to huge inter-flake resistance. To overcome this challenge, here we propose and demonstrate an unconventional thin film transistor (TFT) device architecture which can circumvent the shortcoming of large inter-flake resistance by transforming the TFTs into predominantly intra-flake transport edge-FETs. Using this edge-FET device architecture, here we present TFTs printed from chemically exfoliated WS2 and MoSe2 inks, with 106 µA/µm and 25 µA/µm width-normalized, On-state current density, respectively. On the other hand, the maximum On-Off ratio observed in these printed TFTs have also been large, as high as 107 has been recorded, which is surely a rarity in solution-processed 2D electronics. In addition, a tunable channel capacitance mediated subthermionic transport with minimum subthreshold slope of 36 mV/dec has also been observed.
{"title":"Inkjet-printed WS2 and MoSe2 transistors with edge-FET architecture and near-vertical electronic transport","authors":"S. K. Mondal, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10117997","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117997","url":null,"abstract":"Two dimensional (2D) semiconductors combine the advantages of both oxide and organic semiconductor world, namely, high carrier mobility, environmental stability, as well as room temperature processability, flexibility and the availability of both high carrier mobility n- and p-type semiconductor variants. However, for their realization in flexible, wearable electronics, high throughput solution processing techniques, such as printing is essential. However, when solution processed, the performance of the devices deteriorates substantially due to huge inter-flake resistance. To overcome this challenge, here we propose and demonstrate an unconventional thin film transistor (TFT) device architecture which can circumvent the shortcoming of large inter-flake resistance by transforming the TFTs into predominantly intra-flake transport edge-FETs. Using this edge-FET device architecture, here we present TFTs printed from chemically exfoliated WS2 and MoSe2 inks, with 106 µA/µm and 25 µA/µm width-normalized, On-state current density, respectively. On the other hand, the maximum On-Off ratio observed in these printed TFTs have also been large, as high as 107 has been recorded, which is surely a rarity in solution-processed 2D electronics. In addition, a tunable channel capacitance mediated subthermionic transport with minimum subthreshold slope of 36 mV/dec has also been observed.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117629
Vidur Rai, Yi Zhu, K. Vora, L. Fu, H. Tan, C. Jagadish
Nanowire devices have long been proposed as an efficient alternative to their planar counterparts for different optoelectronic applications. Unfortunately, challenges related to the growth and characterization of doping and p-n junction formation in nanowire devices (along axial or radial axis) have significantly impeded their development. The problems are further amplified if a p-n junction has to be implemented radially. Therefore, even though radial junction devices are expected to be on par with their axial junction counterparts, there are minimal reports on high-performance radial junction nanowire optoelectronic devices. This paper summarizes our recent results on the simulation and fabrication of radial junction nanowire solar cells and photodetectors, which have shown unprecedented performance and clearly demonstrate the importance of radial junction for optoelectronic applications. Our simulation results show that the proposed radial junction device is both optically and electrically optimal for solar cell and photodetector applications, especially if the absorber quality is extremely low. The radial junction nanowire solar cells could achieve a 17.2% efficiency, whereas the unbiased radial junction photodetector could show sensitivity down to a single photon level using an absorber with a lifetime of less than 50 ps. In comparison, the axial junction planar device made using same substrate as absorber showed less than 1 % solar cell efficiency and almost no photodetection at 0 V. This study is conclusive experimental proof of the superiority of radial junction nanowire devices over their thin film or axial junction counterparts, especially when absorber lifetime is extremely low. The proposed device holds huge promise for III-V based photovoltaics and photodetectors.
{"title":"Pushing limits of photovoltaics and photodetection using radial junction nanowire devices","authors":"Vidur Rai, Yi Zhu, K. Vora, L. Fu, H. Tan, C. Jagadish","doi":"10.1109/ICEE56203.2022.10117629","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117629","url":null,"abstract":"Nanowire devices have long been proposed as an efficient alternative to their planar counterparts for different optoelectronic applications. Unfortunately, challenges related to the growth and characterization of doping and p-n junction formation in nanowire devices (along axial or radial axis) have significantly impeded their development. The problems are further amplified if a p-n junction has to be implemented radially. Therefore, even though radial junction devices are expected to be on par with their axial junction counterparts, there are minimal reports on high-performance radial junction nanowire optoelectronic devices. This paper summarizes our recent results on the simulation and fabrication of radial junction nanowire solar cells and photodetectors, which have shown unprecedented performance and clearly demonstrate the importance of radial junction for optoelectronic applications. Our simulation results show that the proposed radial junction device is both optically and electrically optimal for solar cell and photodetector applications, especially if the absorber quality is extremely low. The radial junction nanowire solar cells could achieve a 17.2% efficiency, whereas the unbiased radial junction photodetector could show sensitivity down to a single photon level using an absorber with a lifetime of less than 50 ps. In comparison, the axial junction planar device made using same substrate as absorber showed less than 1 % solar cell efficiency and almost no photodetection at 0 V. This study is conclusive experimental proof of the superiority of radial junction nanowire devices over their thin film or axial junction counterparts, especially when absorber lifetime is extremely low. The proposed device holds huge promise for III-V based photovoltaics and photodetectors.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118336
J. Jatin, M. Monishmurali, S. K. Gautam, M. Shrivastava
In this work, for the first time, Drain-Extended vertically stacked Nanosheet-based HV device has been studied in the context of System-On-Chip (SoC) integration. Physical insights into the device performance and ESD reliability are elaborated using 3D TCAD process simulations. Finally, the performance and reliability co-design guidelines related to HV devices in Nanosheets technology have been discussed comprehensively.
{"title":"Performance and Reliability Co-Design of HV devices in Vertically Stacked Nanosheet Technology","authors":"J. Jatin, M. Monishmurali, S. K. Gautam, M. Shrivastava","doi":"10.1109/ICEE56203.2022.10118336","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118336","url":null,"abstract":"In this work, for the first time, Drain-Extended vertically stacked Nanosheet-based HV device has been studied in the context of System-On-Chip (SoC) integration. Physical insights into the device performance and ESD reliability are elaborated using 3D TCAD process simulations. Finally, the performance and reliability co-design guidelines related to HV devices in Nanosheets technology have been discussed comprehensively.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126848555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118015
Radhika Varshney, P. N, Simranjeet Singh, T. Naik, Praveen C Ramamurthy
Cadmium (Cd), popularly used in electroplating, batteries, and paints, is a well-recognized carcinogen and a toxic non-essential element for the human body. Hence, developing an effective sensor for detecting Cd (II) from water is a critical requirement. In this work, an electrochemical sensor based on green synthesized sulphur-doped carbon nanospheres (S-CNs) modified carbon paste electrode (S-CNs/CPE) has been developed that demonstrates a limit of detection (LOD) of ~14.4 μM towards Cd (II) in water using differential pulse voltammetry (DPV) technique. Interference studies and real sample analysis reveal the effectiveness of the developed S-CNs/CPE.
{"title":"Sulphur-Doped Carbon Nanospheres Based Sensor for the Electrochemical Detection of Cadmium","authors":"Radhika Varshney, P. N, Simranjeet Singh, T. Naik, Praveen C Ramamurthy","doi":"10.1109/ICEE56203.2022.10118015","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118015","url":null,"abstract":"Cadmium (Cd), popularly used in electroplating, batteries, and paints, is a well-recognized carcinogen and a toxic non-essential element for the human body. Hence, developing an effective sensor for detecting Cd (II) from water is a critical requirement. In this work, an electrochemical sensor based on green synthesized sulphur-doped carbon nanospheres (S-CNs) modified carbon paste electrode (S-CNs/CPE) has been developed that demonstrates a limit of detection (LOD) of ~14.4 μM towards Cd (II) in water using differential pulse voltammetry (DPV) technique. Interference studies and real sample analysis reveal the effectiveness of the developed S-CNs/CPE.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"549 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118295
C. Mukherjee, Nikhil Gangwar, Somil Maheshwari, S. Mukhopadhyay
Electric heating is essential for many research and industrial applications, including multi-chamber furnaces for heat treatment and plasma vacuum chambers. Heating elements, such as heating tapes, coils, etc., are conveniently used for these kinds of heating operations. Variable auto-transformers, also known as Variacs, are used to regulate the power input to these heating components because of their versatility. With the use of auto-transformers, the user can change the input voltage to the heater, which in turn changes the input current to the heaters, thus changing the input power (hence the process temperature). In many processes, a constant power input needs to be supplied to these heaters through out the operation. The user must continuously monitor the process power input and manually adjust the auto-transformer voltage as necessary. This is a tedious and error prone task. In this work the automation for supplying constant power to heating element utilizing a stepper motor controller to regulate a variable auto transformer is described in detailed. The design has the provision of setting desired power input by the user and the control system will achieve and maintain it accordingly. The system utilizes both programmable logic control and an algorithm to achieve efficient control. The design uses the ATmega328P micro-controller based Arduino UNO for control and operating purposes. The code development is done in the Arduino Integrated Development Environment (IDE). Experimental findings have confirmed the better controlling of the auto-transformer's power output. The auto-transformer controlling mechanism described in this paper is power-efficient, less expensive (in terms of components' total cost), and best suited for all resistance heaters and motors' speed control and other similar applications. Project files available at: https://github.com/Nikhil-Gangwar/SPARS
{"title":"Development of Stepper Motor-Based Programmable Autotransformer Output Power Regulating System","authors":"C. Mukherjee, Nikhil Gangwar, Somil Maheshwari, S. Mukhopadhyay","doi":"10.1109/ICEE56203.2022.10118295","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118295","url":null,"abstract":"Electric heating is essential for many research and industrial applications, including multi-chamber furnaces for heat treatment and plasma vacuum chambers. Heating elements, such as heating tapes, coils, etc., are conveniently used for these kinds of heating operations. Variable auto-transformers, also known as Variacs, are used to regulate the power input to these heating components because of their versatility. With the use of auto-transformers, the user can change the input voltage to the heater, which in turn changes the input current to the heaters, thus changing the input power (hence the process temperature). In many processes, a constant power input needs to be supplied to these heaters through out the operation. The user must continuously monitor the process power input and manually adjust the auto-transformer voltage as necessary. This is a tedious and error prone task. In this work the automation for supplying constant power to heating element utilizing a stepper motor controller to regulate a variable auto transformer is described in detailed. The design has the provision of setting desired power input by the user and the control system will achieve and maintain it accordingly. The system utilizes both programmable logic control and an algorithm to achieve efficient control. The design uses the ATmega328P micro-controller based Arduino UNO for control and operating purposes. The code development is done in the Arduino Integrated Development Environment (IDE). Experimental findings have confirmed the better controlling of the auto-transformer's power output. The auto-transformer controlling mechanism described in this paper is power-efficient, less expensive (in terms of components' total cost), and best suited for all resistance heaters and motors' speed control and other similar applications. Project files available at: https://github.com/Nikhil-Gangwar/SPARS","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122341801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117915
C. Jha, Alireza Mahzoon, R. Drechsler
Adders are implemented using a wide variety of architectures. These architectures have been extensively studied for digital IC-based implementations. In recent years, in-memory computing has gained interest owing to the benefits it provides in terms of both energy and performance as compared to conventional von Neumann computing. In this work, we for the first time investigate various adder architectures for in-memory computing using the memristor aided logic (MAGIC) design style for memristors. We analyze seven different adder architectures for bit-widths: 8-bit, 16-bit, 32-bit, and 64-bit. We have used the state-of-the-art SIMPLER tool for performing the mapping of these adders to memristor crossbars. We show that serial prefix adders are better suitable for IMC using the MAGIC design style as compared to the widely used ripple carry adder. The adder designs and the mapping will be made open source at https://github.com/agra-uni-bremen/icee2022-magic-adder-lib, to promote further research in the direction.
{"title":"Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style","authors":"C. Jha, Alireza Mahzoon, R. Drechsler","doi":"10.1109/ICEE56203.2022.10117915","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117915","url":null,"abstract":"Adders are implemented using a wide variety of architectures. These architectures have been extensively studied for digital IC-based implementations. In recent years, in-memory computing has gained interest owing to the benefits it provides in terms of both energy and performance as compared to conventional von Neumann computing. In this work, we for the first time investigate various adder architectures for in-memory computing using the memristor aided logic (MAGIC) design style for memristors. We analyze seven different adder architectures for bit-widths: 8-bit, 16-bit, 32-bit, and 64-bit. We have used the state-of-the-art SIMPLER tool for performing the mapping of these adders to memristor crossbars. We show that serial prefix adders are better suitable for IMC using the MAGIC design style as compared to the widely used ripple carry adder. The adder designs and the mapping will be made open source at https://github.com/agra-uni-bremen/icee2022-magic-adder-lib, to promote further research in the direction.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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