Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117789
Jyoti Patel, N. Bagga, Shashank Banchhor, S. Dasgupta
In FinFETs, the source/drain (S/D) extension regions play a vital role in the device's performance as it modulates the overall parasitic capacitance. Thus, placing a symmetric/asymmetric spacer in the FinFET changes the overall capacitance. This paper demonstrated the impact of putting the symmetric and asymmetric spacer in multi-fin FinFET. We kept the same fin length while changing the source-side and drain-side spacer lengths. The impact of an asymmetric spacer is investigated on the device characteristics, such as ON current, gate capacitance, transconductance, etc., for single and multi-fin configurations. Further, we designed a basic common source (CS) amplifier with resistive load and investigated the circuit level performance using spacer optimization through extensive TCAD simulations. The optimum device performance is observed for asymmetric source and drain spacer length (LDSP 16nm and Lssp = 4nm) for three fins FinFET.
{"title":"Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation","authors":"Jyoti Patel, N. Bagga, Shashank Banchhor, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10117789","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117789","url":null,"abstract":"In FinFETs, the source/drain (S/D) extension regions play a vital role in the device's performance as it modulates the overall parasitic capacitance. Thus, placing a symmetric/asymmetric spacer in the FinFET changes the overall capacitance. This paper demonstrated the impact of putting the symmetric and asymmetric spacer in multi-fin FinFET. We kept the same fin length while changing the source-side and drain-side spacer lengths. The impact of an asymmetric spacer is investigated on the device characteristics, such as ON current, gate capacitance, transconductance, etc., for single and multi-fin configurations. Further, we designed a basic common source (CS) amplifier with resistive load and investigated the circuit level performance using spacer optimization through extensive TCAD simulations. The optimum device performance is observed for asymmetric source and drain spacer length (LDSP 16nm and Lssp = 4nm) for three fins FinFET.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117752
A. P., Y. Chauhan, Amit Verma
Vanadium dioxide (V02) has been exploited in steep subthreshold slope switches, coupled oscillators for neuromorphic computing, and selectors for RRAM due to its intrinsic insulator to metal phase transition properties. The thin-film synthesis of V02 needs a high-temperature process or long annealing duration, which increases the thermal budget and is difficult to integrate with the back-end of line CMOS technology process. In this work, we use a low thermal budget process to fabricate and characterize both horizontal and vertical V02 devices. In both configurations, V02 devices show voltage induced reversible switching beyond a threshold voltage. The threshold voltage of devices decreases monotonically as a function of decreasing channel length of the devices. The vertical device shows the lowest threshold voltage compared to the horizontal structure due to significantly smaller channel length. Finally, we demonstrate a relaxation oscillator using the fabricated V02 devices which shows stable oscillations over half a million cycles with an oscillation frequency of 1.75 kHz. We also demonstrate voltage-controlled tuning of the oscillation frequency in the range of ~1.3-2 kHz. This demonstration of V02 devices with a low-thermal budget process will be helpful for integrating V02-based phase transition devices with CMOS technology
{"title":"Experimental Demonstration of $text{VO}_{2}$ based Lateral/Vertical Devices and Relaxation Oscillator with an Ultra-low Thermal Budget Process","authors":"A. P., Y. Chauhan, Amit Verma","doi":"10.1109/ICEE56203.2022.10117752","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117752","url":null,"abstract":"Vanadium dioxide (V02) has been exploited in steep subthreshold slope switches, coupled oscillators for neuromorphic computing, and selectors for RRAM due to its intrinsic insulator to metal phase transition properties. The thin-film synthesis of V02 needs a high-temperature process or long annealing duration, which increases the thermal budget and is difficult to integrate with the back-end of line CMOS technology process. In this work, we use a low thermal budget process to fabricate and characterize both horizontal and vertical V02 devices. In both configurations, V02 devices show voltage induced reversible switching beyond a threshold voltage. The threshold voltage of devices decreases monotonically as a function of decreasing channel length of the devices. The vertical device shows the lowest threshold voltage compared to the horizontal structure due to significantly smaller channel length. Finally, we demonstrate a relaxation oscillator using the fabricated V02 devices which shows stable oscillations over half a million cycles with an oscillation frequency of 1.75 kHz. We also demonstrate voltage-controlled tuning of the oscillation frequency in the range of ~1.3-2 kHz. This demonstration of V02 devices with a low-thermal budget process will be helpful for integrating V02-based phase transition devices with CMOS technology","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127813880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117787
Utkarsh Pandey, Nilashis Pal, B. Pal
Li-Alumina (LA) Ion-conducting dielectric thin film has been prepared through the low-cost sol-gel method and is prosperously use to fabricate the metal-oxide based thin-film transistor (MOTFT). This MOTFT shows the high device performance at very low operating voltage (2V). Li-Alumina thin film shows a very high insulating nature due to the high band-gap of the material. Furthermore, because of the Li+ ion conduction a thin film LA, can be has a very high areal capacitance and may be used as a gate dielectric for low operating voltage metal oxide TFTs. Besides, thin film of LA gives low surface roughness due to its amorphous nature resulting decrease in the gate leakage current in TFT. Also, Li-Alumina dielectric has strong compatibility with the SnO2 semiconducting channel in TFT. A SnO2 thin film has been deposited on the top of the Li-Alumina dielectric layer by the solution-processed technique in the top contact bottom gate TFT architecture that works as semiconductor channel of the device. To saturate the drain current in this TFT, only 2.0 V or less drain voltage (VD) is required, with a gate bias of 2.0 V. The obtained value of threshold voltage Vth), carrier mobility (μ) and On/Off ratio of this device are 0.9 V, 1 cm2V-1s-1 and 1.1 x 102. For the application of this TFT as pressure sensor, a piezoelectric material (PVDF-HFP) thin film has been fabricated on the top of the device, that works as a back gate in the device. Channel current of this TFT can be modulated by applying pressure on the PVDF-HFP thin film. Hence, this device works as piezoelectric back-contacted TFT that can also be considered TFT as a pressure sensor. Additionally, this metal oxide based pressure sensor shows excellent performance in terms of the sensitivity, linearity and response time of the device.
{"title":"Low voltage metal oxide TFT with back-contacted piezoelectric PVDF-HFP coating for pressure sensing applications","authors":"Utkarsh Pandey, Nilashis Pal, B. Pal","doi":"10.1109/ICEE56203.2022.10117787","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117787","url":null,"abstract":"Li-Alumina (LA) Ion-conducting dielectric thin film has been prepared through the low-cost sol-gel method and is prosperously use to fabricate the metal-oxide based thin-film transistor (MOTFT). This MOTFT shows the high device performance at very low operating voltage (2V). Li-Alumina thin film shows a very high insulating nature due to the high band-gap of the material. Furthermore, because of the Li+ ion conduction a thin film LA, can be has a very high areal capacitance and may be used as a gate dielectric for low operating voltage metal oxide TFTs. Besides, thin film of LA gives low surface roughness due to its amorphous nature resulting decrease in the gate leakage current in TFT. Also, Li-Alumina dielectric has strong compatibility with the SnO2 semiconducting channel in TFT. A SnO2 thin film has been deposited on the top of the Li-Alumina dielectric layer by the solution-processed technique in the top contact bottom gate TFT architecture that works as semiconductor channel of the device. To saturate the drain current in this TFT, only 2.0 V or less drain voltage (VD) is required, with a gate bias of 2.0 V. The obtained value of threshold voltage Vth), carrier mobility (μ) and On/Off ratio of this device are 0.9 V, 1 cm2V-1s-1 and 1.1 x 102. For the application of this TFT as pressure sensor, a piezoelectric material (PVDF-HFP) thin film has been fabricated on the top of the device, that works as a back gate in the device. Channel current of this TFT can be modulated by applying pressure on the PVDF-HFP thin film. Hence, this device works as piezoelectric back-contacted TFT that can also be considered TFT as a pressure sensor. Additionally, this metal oxide based pressure sensor shows excellent performance in terms of the sensitivity, linearity and response time of the device.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118127
B. U, Bidisha Nath, Nagahanumaiah, Praveen C Ramamurthy
The Tin-based perovskite is an encouraging material in the development of non-toxic solar cell application, but its performance is limited by the poor chemical stability against oxygen and moisture. Therefore, tin-based perovskite solar cells are mostly fabricated in inverted planar device structures and the selection of underlying hole transport material plays a significant role in device stability. In this work, we report the comparison study between a metal oxide, nickel oxide, and polymeric poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT: PSS) as a hole transport layer on device efficiency and stability of tin-based PSC. We obtained comparatively higher power conversion efficiency (PCE) with NiOx than others, however, the solar cell with PEDOT: PSS is more stable rather than NiOx for the duration of 900 hrs in a nitrogen ambient, without encapsulation.
{"title":"Comparison of polymeric and metal oxide hole transport material on the stability of FASnI3 perovskite solar cell","authors":"B. U, Bidisha Nath, Nagahanumaiah, Praveen C Ramamurthy","doi":"10.1109/ICEE56203.2022.10118127","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118127","url":null,"abstract":"The Tin-based perovskite is an encouraging material in the development of non-toxic solar cell application, but its performance is limited by the poor chemical stability against oxygen and moisture. Therefore, tin-based perovskite solar cells are mostly fabricated in inverted planar device structures and the selection of underlying hole transport material plays a significant role in device stability. In this work, we report the comparison study between a metal oxide, nickel oxide, and polymeric poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT: PSS) as a hole transport layer on device efficiency and stability of tin-based PSC. We obtained comparatively higher power conversion efficiency (PCE) with NiOx than others, however, the solar cell with PEDOT: PSS is more stable rather than NiOx for the duration of 900 hrs in a nitrogen ambient, without encapsulation.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117639
Vinod Naik Bhukya, Rik Dey, Y. Chauhan
A micromagnetic simulation study has been performed to analyze the magnetization switching dynamics of a ferromagnet on a topological insulator surface. The micromagnetic simulation is based on an analytical solution obtained for the spin-orbit torque which is position-dependent due to current shunting in the bilayer. The micromagnetic simulation is carried out using Ubermag, which is a python-language-based interface and uses OOMMF as the computational backend. From the simulations, switching times are extracted for the position-dependent case as well as various limiting cases. It is found that the switching time for the position-dependent case approaches the parallel transport limit for large values of the normalized tunneling rate and large length of the device, and the spin-orbit torque efficiency can be greater than 1 in those cases.
{"title":"Micromagnetic Simulations of Magnetization Dynamics Due to Position-dependent Spin-Orbit Torque From Topological Insulator","authors":"Vinod Naik Bhukya, Rik Dey, Y. Chauhan","doi":"10.1109/ICEE56203.2022.10117639","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117639","url":null,"abstract":"A micromagnetic simulation study has been performed to analyze the magnetization switching dynamics of a ferromagnet on a topological insulator surface. The micromagnetic simulation is based on an analytical solution obtained for the spin-orbit torque which is position-dependent due to current shunting in the bilayer. The micromagnetic simulation is carried out using Ubermag, which is a python-language-based interface and uses OOMMF as the computational backend. From the simulations, switching times are extracted for the position-dependent case as well as various limiting cases. It is found that the switching time for the position-dependent case approaches the parallel transport limit for large values of the normalized tunneling rate and large length of the device, and the spin-orbit torque efficiency can be greater than 1 in those cases.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129053864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117969
Sonalie Ahirwar, T. Pramanik
Magnetic immunity is an important reliability metric for spin-transfer-torque random-access memory (STT-RAM). The presence of an external magnetic field may cause retention fails in stand-by mode or switching fails during the write operation. Specifically, active write mode magnetic immunity has not been well explored although it was reported to be the limiter in deciding the magnetic immunity metrics. Here, we present a simulation study of stand-by bit error rates (BER) and write error rates (WER) under the influence of external magnetic field perturbation. Results show that the effect of the external magnetic field is more pronounced when it is applied along a direction non-collinear to the easy axis of the magnet. Variation in the stand-by BER is found to follow the Stoner-Wohlfarth model. It is also observed that the active write mode BER may increase by orders of magnitude for specific directions of applied fields depending on the applied write current and magnetic field strength. The variation in WER is explained by the formation of additional zero-torque “stagnation points” on the magnetization unit sphere. The results show the need for careful characterization of both the stand-by mode and the active write mode while measuring the magnetic immunity of the STT-RAM cell.
{"title":"A simulation study of stand-by and active write mode magnetic immunity of perpendicular spin-transfer-torque random-access memory","authors":"Sonalie Ahirwar, T. Pramanik","doi":"10.1109/ICEE56203.2022.10117969","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117969","url":null,"abstract":"Magnetic immunity is an important reliability metric for spin-transfer-torque random-access memory (STT-RAM). The presence of an external magnetic field may cause retention fails in stand-by mode or switching fails during the write operation. Specifically, active write mode magnetic immunity has not been well explored although it was reported to be the limiter in deciding the magnetic immunity metrics. Here, we present a simulation study of stand-by bit error rates (BER) and write error rates (WER) under the influence of external magnetic field perturbation. Results show that the effect of the external magnetic field is more pronounced when it is applied along a direction non-collinear to the easy axis of the magnet. Variation in the stand-by BER is found to follow the Stoner-Wohlfarth model. It is also observed that the active write mode BER may increase by orders of magnitude for specific directions of applied fields depending on the applied write current and magnetic field strength. The variation in WER is explained by the formation of additional zero-torque “stagnation points” on the magnetization unit sphere. The results show the need for careful characterization of both the stand-by mode and the active write mode while measuring the magnetic immunity of the STT-RAM cell.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129068882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117996
Gargi Konwar, Sachin Rahi, S. P. Tiwari
Flexible electronics utilizing emerging edible natural materials as device components lead a path towards the development of cost-effective, renewable, sustainable, and eco-friendly smart systems. Here, an edible and natural biopolymer egg albumen was explored with a thin high-k HfO2 layer to form a hybrid gate dielectric layer for the demonstration of flexible organic transistors. The thin high-k dielectric layer enables the devices to be operated at low voltage while the biopolymer layer helps in forming a better dielectric semiconductor interface. The fabricated devices have shown excellent p-channel characteristics at a low operating voltage of -5 V. Moreover, these devices exhibited good electrical and operational stability to be used in practical applications. These findings suggest that this proposed gate dielectric combination can be an interesting and potential component for flexible organic devices.
{"title":"Flexible Organic Transistors with Hybrid Gate Dielectric Consisting Albumen as an Edible Component","authors":"Gargi Konwar, Sachin Rahi, S. P. Tiwari","doi":"10.1109/ICEE56203.2022.10117996","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117996","url":null,"abstract":"Flexible electronics utilizing emerging edible natural materials as device components lead a path towards the development of cost-effective, renewable, sustainable, and eco-friendly smart systems. Here, an edible and natural biopolymer egg albumen was explored with a thin high-k HfO2 layer to form a hybrid gate dielectric layer for the demonstration of flexible organic transistors. The thin high-k dielectric layer enables the devices to be operated at low voltage while the biopolymer layer helps in forming a better dielectric semiconductor interface. The fabricated devices have shown excellent p-channel characteristics at a low operating voltage of -5 V. Moreover, these devices exhibited good electrical and operational stability to be used in practical applications. These findings suggest that this proposed gate dielectric combination can be an interesting and potential component for flexible organic devices.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118107
S. Chakraborty, V. Awasthi, R. Goel, S. Dubey
In this work, we present a simple, economically viable technique of chemically synthesizing silver-decorated reduced graphene (Ag-rG) and its application in SERS analyte detection. We detected R6G (20 µL) up to 10–6 M using Ag-rG as a SERS-active substrate. R6G, a dye, is irradiated by a laser source (λ =785nm) and Raman spectra are acquired using integrated Raman setup (Renishaw). Ag-rG can be used for in-situ explosive detection, food/water adulterant detection, bio-diagnostics, narco-analysis, etc.
{"title":"Chemical Synthesis and Application of Silver Decorated Reduced Graphene as an Economically Viable Surface Enhanced Raman Scattering Based Substrate for Detection of Analytes in Trace Quantities","authors":"S. Chakraborty, V. Awasthi, R. Goel, S. Dubey","doi":"10.1109/ICEE56203.2022.10118107","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118107","url":null,"abstract":"In this work, we present a simple, economically viable technique of chemically synthesizing silver-decorated reduced graphene (Ag-rG) and its application in SERS analyte detection. We detected R6G (20 µL) up to 10–6 M using Ag-rG as a SERS-active substrate. R6G, a dye, is irradiated by a laser source (λ =785nm) and Raman spectra are acquired using integrated Raman setup (Renishaw). Ag-rG can be used for in-situ explosive detection, food/water adulterant detection, bio-diagnostics, narco-analysis, etc.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117759
Aneesh M. Joseph
The design of T -Gate is crucial for the performance of AlGaN/GaN power amplifiers. Optimizing aT-gate reproducibly is a challenge on Gallium Nitride (GaN) on Silicon Carbide (SiC) due to the charging of the substrate. Single-step electron-beam lithography (EBL) has been demonstrated by engineering by dose and photoresist parameters.
{"title":"Fabrication and optimization of T -gate for high performance HEMT and MMIC devices","authors":"Aneesh M. Joseph","doi":"10.1109/ICEE56203.2022.10117759","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117759","url":null,"abstract":"The design of T -Gate is crucial for the performance of AlGaN/GaN power amplifiers. Optimizing aT-gate reproducibly is a challenge on Gallium Nitride (GaN) on Silicon Carbide (SiC) due to the charging of the substrate. Single-step electron-beam lithography (EBL) has been demonstrated by engineering by dose and photoresist parameters.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117799
R. Chakraborty, Nilashis Pal, B. Pal
An ideal ferroelectric gate dielectric based thin film transistor (FeTFT) can offer a memory device of random access, high speed, low power, high density and nonvolatility. Lithium niobate (LiNbO3) being a well-known ferroelectric material, but its implementation in FeTFT has not been explored much. This work is reporting a methodology of LiNbO3 based FeTFT device fabrication by solution processed technique. The carrier mobility of 9.6 cm2V-1s-1 and current ON/OFF ratio of 1.9x103 are attained with this LiNbO3 ferroelectric gate dielectric based FeTFT device. This work also demonstrates a reasonably good memory retention time of a ferroelectric thin film transistor.
{"title":"Solution-Processed LiNbO3 Thin Film as a Gate Dielectric of a Ferroelectric Thin Film Transistor","authors":"R. Chakraborty, Nilashis Pal, B. Pal","doi":"10.1109/ICEE56203.2022.10117799","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117799","url":null,"abstract":"An ideal ferroelectric gate dielectric based thin film transistor (FeTFT) can offer a memory device of random access, high speed, low power, high density and nonvolatility. Lithium niobate (LiNbO<inf>3</inf>) being a well-known ferroelectric material, but its implementation in FeTFT has not been explored much. This work is reporting a methodology of LiNbO<inf>3</inf> based FeTFT device fabrication by solution processed technique. The carrier mobility of 9.6 cm<sup>2</sup>V<sup>-1</sup>s<sup>-1</sup> and current ON/OFF ratio of 1.9x10<sup>3</sup> are attained with this LiNbO<inf>3</inf> ferroelectric gate dielectric based FeTFT device. This work also demonstrates a reasonably good memory retention time of a ferroelectric thin film transistor.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125581264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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