Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008244
S. Fujiwara, M. Harada, Y. Fujita, T. Hachiya, M. Muramatsu
The flip-chip technique, in which a bare chip is directly connected to a substrate, has become a key technology in producing compact electronic products, including cellular phones. In particular, the technique of using Au bumps to connect the bare chip with the substrate, with the aid of an anisotropic conductive film (ACF), is one of the most useful technologies. The most serious problem with ACF bonding technology today is that the deterioration mechanism of interconnections is not clear. This study is motivated to clarify the mechanism of deterioration and to establish the method of obtaining reliability in the design of interconnections for which ACF is used.
{"title":"Deterioration mechanism of flip chip attachment using an anisotropic conductive film and design technology for high reliability","authors":"S. Fujiwara, M. Harada, Y. Fujita, T. Hachiya, M. Muramatsu","doi":"10.1109/ECTC.2002.1008244","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008244","url":null,"abstract":"The flip-chip technique, in which a bare chip is directly connected to a substrate, has become a key technology in producing compact electronic products, including cellular phones. In particular, the technique of using Au bumps to connect the bare chip with the substrate, with the aid of an anisotropic conductive film (ACF), is one of the most useful technologies. The most serious problem with ACF bonding technology today is that the deterioration mechanism of interconnections is not clear. This study is motivated to clarify the mechanism of deterioration and to establish the method of obtaining reliability in the design of interconnections for which ACF is used.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134160187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008197
H. Fan, P. Chung, M. Yuen, P. Chan
The propensity and significance of interfacial delamination as a crucial failure mechanism in electronic packaging have been well documented in many papers. Many of the failure criteria were used to solve 2-dimensional problem with a pre-crack. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3-D delamination problems. The potential delamination interface of copper leadframe/Epoxy Molding Compound (EMC) was selected in the study. The stresses of the interface were evaluated by the Button Shear Test. A series of Button Shear Tests was conducted to evaluate the adhesion properties of Epoxy Molding Compounds (EMCs) on copper substrate. In each of the tests, the critical load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the interface between the mold compound and the copper substrate. In this paper, an energy-based method is proposed by deriving the energy to initiate each of the tensile and shear modes of failure across the interfaces of the button shear test samples for the chosen EMC/leadframe material system. Component stresses were extracted from the numerical simulation in order to compute the distortional strain energy density, (U/sub d/), and the hydrostatic strain energy density, (U/sub h/), relating respectively to the shear and tensile mode. (U/sub d/) and (U/sub h/) were calculated from the Young's modulus of EMC and the average stresses within a selected region of the finite element model where it exhibits high stress values.
{"title":"An energy-based method to predict delamination in electronic packaging","authors":"H. Fan, P. Chung, M. Yuen, P. Chan","doi":"10.1109/ECTC.2002.1008197","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008197","url":null,"abstract":"The propensity and significance of interfacial delamination as a crucial failure mechanism in electronic packaging have been well documented in many papers. Many of the failure criteria were used to solve 2-dimensional problem with a pre-crack. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3-D delamination problems. The potential delamination interface of copper leadframe/Epoxy Molding Compound (EMC) was selected in the study. The stresses of the interface were evaluated by the Button Shear Test. A series of Button Shear Tests was conducted to evaluate the adhesion properties of Epoxy Molding Compounds (EMCs) on copper substrate. In each of the tests, the critical load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the interface between the mold compound and the copper substrate. In this paper, an energy-based method is proposed by deriving the energy to initiate each of the tensile and shear modes of failure across the interfaces of the button shear test samples for the chosen EMC/leadframe material system. Component stresses were extracted from the numerical simulation in order to compute the distortional strain energy density, (U/sub d/), and the hydrostatic strain energy density, (U/sub h/), relating respectively to the shear and tensile mode. (U/sub d/) and (U/sub h/) were calculated from the Young's modulus of EMC and the average stresses within a selected region of the finite element model where it exhibits high stress values.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008264
G. Grossmann, G. Nicoletti, U. Soler
The use of lead-free solder brings up concerns regarding the reliability of the new alloys to be used. In a European project (LEADFREE) SnAg, SnAgCu, SnAgCuSb, SnZn and SnPbAg have been tested in order to evaluate comparative data of the growth of cracks in solder joints. Reliability tests performed in other projects use accelerated tests proposed for tin-lead solders and showed a superior reliability of lead free solder over tin-lead alloys. The validity of these tests has to be questioned since they do not allow full relaxation of the stresses in solder joints. Thus each alloy is subject to another amount of strain. LEADFREE tests are run with slow temperature ramps and long dwell times to account for this fact. As a result a faster growth of cracks has been observed in lead free solder joints compared to Sn62Pb36Ag2.
{"title":"Results of comparative reliability tests on lead-free solder alloys","authors":"G. Grossmann, G. Nicoletti, U. Soler","doi":"10.1109/ECTC.2002.1008264","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008264","url":null,"abstract":"The use of lead-free solder brings up concerns regarding the reliability of the new alloys to be used. In a European project (LEADFREE) SnAg, SnAgCu, SnAgCuSb, SnZn and SnPbAg have been tested in order to evaluate comparative data of the growth of cracks in solder joints. Reliability tests performed in other projects use accelerated tests proposed for tin-lead solders and showed a superior reliability of lead free solder over tin-lead alloys. The validity of these tests has to be questioned since they do not allow full relaxation of the stresses in solder joints. Thus each alloy is subject to another amount of strain. LEADFREE tests are run with slow temperature ramps and long dwell times to account for this fact. As a result a faster growth of cracks has been observed in lead free solder joints compared to Sn62Pb36Ag2.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122468338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008236
B. Zhong, S. Dvorak, J. Prince
A new hybrid phase-pole macromodel (HPPM) was recently developed for modeling lossless interconnects. Now this HPPM is applied for the transient simulation of interconnects. First, the time-domain waveform is expanded in terms of triangular expansion functions. A knowledge of the triangle impulse response (TIR), which is represented in the form of a HPPM, then allows for the time domain simulation of the line voltage. A recursive convolution algorithm is adopted to carry out the required convolutions efficiently in the transient simulator. Combining this transient simulator with an HPPM extractor yields an efficient transient interconnect signal analysis tool. Work is ongoing to extend the technique to lossy interconnects.
{"title":"Development of a time-domain simulation methodology for the hybrid phase-pole interconnect macromodel","authors":"B. Zhong, S. Dvorak, J. Prince","doi":"10.1109/ECTC.2002.1008236","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008236","url":null,"abstract":"A new hybrid phase-pole macromodel (HPPM) was recently developed for modeling lossless interconnects. Now this HPPM is applied for the transient simulation of interconnects. First, the time-domain waveform is expanded in terms of triangular expansion functions. A knowledge of the triangle impulse response (TIR), which is represented in the form of a HPPM, then allows for the time domain simulation of the line voltage. A recursive convolution algorithm is adopted to carry out the required convolutions efficiently in the transient simulator. Combining this transient simulator with an HPPM extractor yields an efficient transient interconnect signal analysis tool. Work is ongoing to extend the technique to lossy interconnects.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008077
H. T. Vo, C. Davidson, F. Shi
The existing CAD formulae are complicated and inaccurate at high frequencies. In particular, no closed-form expression has been obtained for the effective dielectric constant of microstrip lines on multi-layed dielectric substrate by considering the line-substrate interphase effect, although attempts have been made to study the finite thickness effect of the conductor and dielectric substrate. The present work represents the first attempt to obtain a closed-form CAD formula for the effective dielectric constant of microstrip lines on dielectric substrates by considering the effect of conductor-substrate interphase, in addition to the skin effect losses, dielectric loss, dispersion and radiation losses based on the quasi-TEM assumption and the superposition of partial capacitance. The model is verified by experimental observations on the effective dielectric constant and its dependence on microstrip dimension and frequency.
{"title":"New effective dielectric constant model for ultra-high speed microstrip lines on multilayer dielectric substrates: effect of conductor-dielectric interphase","authors":"H. T. Vo, C. Davidson, F. Shi","doi":"10.1109/ECTC.2002.1008077","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008077","url":null,"abstract":"The existing CAD formulae are complicated and inaccurate at high frequencies. In particular, no closed-form expression has been obtained for the effective dielectric constant of microstrip lines on multi-layed dielectric substrate by considering the line-substrate interphase effect, although attempts have been made to study the finite thickness effect of the conductor and dielectric substrate. The present work represents the first attempt to obtain a closed-form CAD formula for the effective dielectric constant of microstrip lines on dielectric substrates by considering the effect of conductor-substrate interphase, in addition to the skin effect losses, dielectric loss, dispersion and radiation losses based on the quasi-TEM assumption and the superposition of partial capacitance. The model is verified by experimental observations on the effective dielectric constant and its dependence on microstrip dimension and frequency.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008072
A. Jancura, Guang Chen
This paper presents simulation and experimental results for gridded power/ground plane structures in LTCC-modules. The approach of using different simulation techniques for power/ground structures is discussed and a wire-trace model for solid-gridded plane pair based on the transmission line model is derived and verified with measurements.
{"title":"Frequency domain behavior of solid and gridded reference power/ground planes in LTCC modules","authors":"A. Jancura, Guang Chen","doi":"10.1109/ECTC.2002.1008072","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008072","url":null,"abstract":"This paper presents simulation and experimental results for gridded power/ground plane structures in LTCC-modules. The approach of using different simulation techniques for power/ground structures is discussed and a wire-trace model for solid-gridded plane pair based on the transmission line model is derived and verified with measurements.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129125528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008099
Seong Joon Ok, J. Neysmith, D. Baldwin
Micro-Electro-Mechanical-Systems (MEMS) are integrated systems combining electrical and mechanical components, which are fabricated using integrated circuit (IC) batch processing techniques. The influence of MEMS is made possible through their benefits in functionality, size, and reliability. In spite of these remarkable and promising achievements in the field of microsystem fabrication, the commercialization of proven devices are lagged far behind expectations, considerably due to high packaging cost, improper packaging design solution and high testing cost. This paper is focused on suggesting and demonstrating a promising generic, modular, Direct-Chip-Attach (DCA), low cost and high reliable MEMS packaging design strategy and solution applying with high aspect ratio Through-Wafer Electrical Interconnect (TWEI). Fabrication of TWEI using dry etching is relatively new technology that can create more and better packaging options than any other conventional packaging design. The various techniques that can make through-wafer vias conductive are demonstrated and analyzed with advantages and drawbacks.
{"title":"Generic, Direct-Chip-Attach MEMS packaging design with high density and aspect ratio Through-Wafer Electrical Interconnect","authors":"Seong Joon Ok, J. Neysmith, D. Baldwin","doi":"10.1109/ECTC.2002.1008099","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008099","url":null,"abstract":"Micro-Electro-Mechanical-Systems (MEMS) are integrated systems combining electrical and mechanical components, which are fabricated using integrated circuit (IC) batch processing techniques. The influence of MEMS is made possible through their benefits in functionality, size, and reliability. In spite of these remarkable and promising achievements in the field of microsystem fabrication, the commercialization of proven devices are lagged far behind expectations, considerably due to high packaging cost, improper packaging design solution and high testing cost. This paper is focused on suggesting and demonstrating a promising generic, modular, Direct-Chip-Attach (DCA), low cost and high reliable MEMS packaging design strategy and solution applying with high aspect ratio Through-Wafer Electrical Interconnect (TWEI). Fabrication of TWEI using dry etching is relatively new technology that can create more and better packaging options than any other conventional packaging design. The various techniques that can make through-wafer vias conductive are demonstrated and analyzed with advantages and drawbacks.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129220644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008275
Jian Chen, I. De Wolf
In the paper, RS (Raman Spectroscopy) is discussed as a stress sensor in packaging. This paper discusses the measurement of thermo-mechanical stress introduced in the Si chip by packaging. Examples are shown for Si on Cu substrate, flip-chip and PSGA samples. It is shown that the relation between the Raman shift and the stress tensor components depends on the crystallographic orientation of the surface of the sample, i.e. Raman measurements on a [001] surface of a chip give different results than measurements on a cross-section ((1-10) surface). The Raman data are compared with finite element calculations.
本文讨论了拉曼光谱在包装中的应力传感器应用。本文讨论了用封装的方法测量硅片中引入的热机械应力。示例显示了Si on Cu衬底，倒装芯片和PSGA样品。结果表明，拉曼位移和应力张量分量之间的关系取决于样品表面的晶体取向，即在芯片[001]表面上的拉曼测量结果与在截面((1-10)表面上的拉曼测量结果不同。拉曼数据与有限元计算结果进行了比较。
{"title":"Raman spectroscopy as a stress sensor in packaging: correct formulae for different sample surfaces","authors":"Jian Chen, I. De Wolf","doi":"10.1109/ECTC.2002.1008275","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008275","url":null,"abstract":"In the paper, RS (Raman Spectroscopy) is discussed as a stress sensor in packaging. This paper discusses the measurement of thermo-mechanical stress introduced in the Si chip by packaging. Examples are shown for Si on Cu substrate, flip-chip and PSGA samples. It is shown that the relation between the Raman shift and the stress tensor components depends on the crystallographic orientation of the surface of the sample, i.e. Raman measurements on a [001] surface of a chip give different results than measurements on a cross-section ((1-10) surface). The Raman data are compared with finite element calculations.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008163
M. Joodaki, G. Kompa, H. Hillmer
A new technology for integration of high frequency active devices into low cost silicon substrates has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermal stress than the earlier QMIT concepts (Wasige et al., 1999; Joodaki et al., 2001 and 2002). This highly improves the packaging life-time and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of low-loss and high-Q passive elements. Successful integration of low-loss high-Q passive elements on low resistivity Si-substrates in this technology has been achieved for the first time (Joodaki et al., 2002). In comparison to the old concept of QMIT, the elimination of air-bridges in this technology not only reduces the parasitics but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible.
介绍了一种将高频有源器件集成到低成本硅衬底上的新技术。这种新颖的制造工艺具有优异的优点，如极低的热阻，以及比早期QMIT概念低得多的热应力(Wasige等人，1999;Joodaki等人，2001年和2002年)。这大大提高了封装寿命和有源器件的电气特性。制造工艺简单，可用于制造低损耗、高q的无源元件。该技术首次成功地将低损耗高q的无源元件集成到低电阻硅衬底上(Joodaki et al.， 2002)。与QMIT的旧概念相比，该技术中消除了空气桥，不仅减少了寄生，而且可以在测量嵌入式有源器件的微波特性后制作其余电路。这使得非常精确的微波和毫米波设计成为可能。使用新的制造工艺，包含功率器件的微波和毫米波电路(包括共面和微带线)首次成为可能。
{"title":"New generation quasi-monolithic integration technology (QMIT)","authors":"M. Joodaki, G. Kompa, H. Hillmer","doi":"10.1109/ECTC.2002.1008163","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008163","url":null,"abstract":"A new technology for integration of high frequency active devices into low cost silicon substrates has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermal stress than the earlier QMIT concepts (Wasige et al., 1999; Joodaki et al., 2001 and 2002). This highly improves the packaging life-time and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of low-loss and high-Q passive elements. Successful integration of low-loss high-Q passive elements on low resistivity Si-substrates in this technology has been achieved for the first time (Joodaki et al., 2002). In comparison to the old concept of QMIT, the elimination of air-bridges in this technology not only reduces the parasitics but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008173
L. Martin, J. Frei
Statistical tools and methodologies were used in a process development application to develop the alignment process for high density substrate fabrication. Improved. capability of the alignment process was realized by reducing variation of the scale alignment mode. First, the data range of interest was determined for scale alignment mode. Then, over the determined data range of interest, the measurement capabilities of the measurement systems used in the work were determined by MSA (measurement system analysis). By use of a DOE (design of experiment), the measurement systems were determined to give significantly different measurements, indicating algorithms were necessary to translate available data from one measurement system to the reference measurement system for reducing scaling variation in the alignment process. The available data was found to highly correlate to the reference measurement system. Subsequently, using regression modeling techniques, algorithms were developed that translated available data to scale factors for compensation of the placement of through-vias and outermetal in relation to the microvias, the identified limiting factor to alignment capability.
{"title":"Application of statistical tools and methods for high density substrate process development [printed circuit board fabrication]","authors":"L. Martin, J. Frei","doi":"10.1109/ECTC.2002.1008173","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008173","url":null,"abstract":"Statistical tools and methodologies were used in a process development application to develop the alignment process for high density substrate fabrication. Improved. capability of the alignment process was realized by reducing variation of the scale alignment mode. First, the data range of interest was determined for scale alignment mode. Then, over the determined data range of interest, the measurement capabilities of the measurement systems used in the work were determined by MSA (measurement system analysis). By use of a DOE (design of experiment), the measurement systems were determined to give significantly different measurements, indicating algorithms were necessary to translate available data from one measurement system to the reference measurement system for reducing scaling variation in the alignment process. The available data was found to highly correlate to the reference measurement system. Subsequently, using regression modeling techniques, algorithms were developed that translated available data to scale factors for compensation of the placement of through-vias and outermetal in relation to the microvias, the identified limiting factor to alignment capability.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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