Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008329
M. O. Alam, Y. Chan, K. Hung
Detailed microstructural studies were carried out to compare the reaction kinetics of Pb-Sn solder and Sn-Ag solder with electroless Ni-P layer for different reflow times. It was found that Sn-Ag solder reacts at a faster rate with the electroless Ni-P layer to form a Ni-Sn intermetallic compound (IMC) and hence a P-rich layer is formed quickly by expellation of the P from the reacting Ni-P layer. The Ni-Sn reaction at the interface of molten Sn-Ag solder with electroless Ni-P is so much quicker, resulting in the entrapment of some P in the Ni-Sn IMC. The initial P content in the electroless Ni-P layer is around 20 at%. However, as high as 38 at% P is detected in the dark Ni-P layer at the Sn-Ag solder interface. After 180 minutes reflow of the Sn-Ag solder joint, the Ni-P layer is found to disappear, leading to the full conversion of the 15 /spl mu/m Cu pad to Cu-Sn IMC. On the contrary, Ni-Sn IMC growth rate in the Pb-Sn solder interface is slower as well as more adherent. For 180 minutes reflow of the Pb-Sn solder interface, the electroless Ni-P layer is found to act as a diffusion barrier for Sri towards the Cu pad. Its implications for lead-free soldering are highlighted.
研究了不同回流时间下Pb-Sn焊料和Sn-Ag钎料与化学Ni-P层的反应动力学。结果表明，Sn-Ag焊料与化学镀Ni-P层反应速度更快，形成Ni-Sn金属间化合物(IMC)，从而使反应的Ni-P层中的P析出，快速形成富P层。熔态Sn-Ag钎料与化学镀Ni-P界面的Ni-Sn反应速度较快，导致Ni-Sn IMC中有部分P被包裹。化学镀Ni-P层的初始P含量约为20% at%。然而，在Sn-Ag钎料界面处的暗Ni-P层中检测到高达38 at% P。Sn-Ag焊点回流180分钟后，发现Ni-P层消失，导致15 /spl mu/m的Cu焊盘完全转化为Cu- sn IMC。相反，Ni-Sn IMC在Pb-Sn钎料界面的生长速度较慢，附着力更强。在Pb-Sn焊料界面回流180分钟后，发现化学镀Ni-P层充当了Sri向Cu焊盘扩散的屏障。强调了其对无铅焊接的影响。
{"title":"Reaction kinetics of Pb-Sn and Sn-Ag solder balls with electroless Ni-P/Cu pad during reflow soldering in microelectronic packaging","authors":"M. O. Alam, Y. Chan, K. Hung","doi":"10.1109/ECTC.2002.1008329","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008329","url":null,"abstract":"Detailed microstructural studies were carried out to compare the reaction kinetics of Pb-Sn solder and Sn-Ag solder with electroless Ni-P layer for different reflow times. It was found that Sn-Ag solder reacts at a faster rate with the electroless Ni-P layer to form a Ni-Sn intermetallic compound (IMC) and hence a P-rich layer is formed quickly by expellation of the P from the reacting Ni-P layer. The Ni-Sn reaction at the interface of molten Sn-Ag solder with electroless Ni-P is so much quicker, resulting in the entrapment of some P in the Ni-Sn IMC. The initial P content in the electroless Ni-P layer is around 20 at%. However, as high as 38 at% P is detected in the dark Ni-P layer at the Sn-Ag solder interface. After 180 minutes reflow of the Sn-Ag solder joint, the Ni-P layer is found to disappear, leading to the full conversion of the 15 /spl mu/m Cu pad to Cu-Sn IMC. On the contrary, Ni-Sn IMC growth rate in the Pb-Sn solder interface is slower as well as more adherent. For 180 minutes reflow of the Pb-Sn solder interface, the electroless Ni-P layer is found to act as a diffusion barrier for Sri towards the Cu pad. Its implications for lead-free soldering are highlighted.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"56 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008305
Johan Liu, Liqiang Cao, Xitao Wang, J. Morris
The authors have developed a course on electrically conductive adhesives for Internet delivery from multiple sites. The paper lays out detailed lecture by lecture content, and details of the experimental sequences, which include both high end analytical techniques and experiments which would be adaptable to any basic undergraduate laboratory environment. Today the course is now installed in an Internet server for easy access. The course starts with a general introduction of conductive adhesive joining technology, followed by a section on ICA part. The course ends with the ACA part of the conductive adhesive technology. Both audio and video techniques are used to facilitate the study.
{"title":"Implementation of the Internet course on conductive adhesives for electronics packaging","authors":"Johan Liu, Liqiang Cao, Xitao Wang, J. Morris","doi":"10.1109/ECTC.2002.1008305","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008305","url":null,"abstract":"The authors have developed a course on electrically conductive adhesives for Internet delivery from multiple sites. The paper lays out detailed lecture by lecture content, and details of the experimental sequences, which include both high end analytical techniques and experiments which would be adaptable to any basic undergraduate laboratory environment. Today the course is now installed in an Internet server for easy access. The course starts with a general introduction of conductive adhesive joining technology, followed by a section on ICA part. The course ends with the ACA part of the conductive adhesive technology. Both audio and video techniques are used to facilitate the study.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008264
G. Grossmann, G. Nicoletti, U. Soler
The use of lead-free solder brings up concerns regarding the reliability of the new alloys to be used. In a European project (LEADFREE) SnAg, SnAgCu, SnAgCuSb, SnZn and SnPbAg have been tested in order to evaluate comparative data of the growth of cracks in solder joints. Reliability tests performed in other projects use accelerated tests proposed for tin-lead solders and showed a superior reliability of lead free solder over tin-lead alloys. The validity of these tests has to be questioned since they do not allow full relaxation of the stresses in solder joints. Thus each alloy is subject to another amount of strain. LEADFREE tests are run with slow temperature ramps and long dwell times to account for this fact. As a result a faster growth of cracks has been observed in lead free solder joints compared to Sn62Pb36Ag2.
{"title":"Results of comparative reliability tests on lead-free solder alloys","authors":"G. Grossmann, G. Nicoletti, U. Soler","doi":"10.1109/ECTC.2002.1008264","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008264","url":null,"abstract":"The use of lead-free solder brings up concerns regarding the reliability of the new alloys to be used. In a European project (LEADFREE) SnAg, SnAgCu, SnAgCuSb, SnZn and SnPbAg have been tested in order to evaluate comparative data of the growth of cracks in solder joints. Reliability tests performed in other projects use accelerated tests proposed for tin-lead solders and showed a superior reliability of lead free solder over tin-lead alloys. The validity of these tests has to be questioned since they do not allow full relaxation of the stresses in solder joints. Thus each alloy is subject to another amount of strain. LEADFREE tests are run with slow temperature ramps and long dwell times to account for this fact. As a result a faster growth of cracks has been observed in lead free solder joints compared to Sn62Pb36Ag2.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122468338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008236
B. Zhong, S. Dvorak, J. Prince
A new hybrid phase-pole macromodel (HPPM) was recently developed for modeling lossless interconnects. Now this HPPM is applied for the transient simulation of interconnects. First, the time-domain waveform is expanded in terms of triangular expansion functions. A knowledge of the triangle impulse response (TIR), which is represented in the form of a HPPM, then allows for the time domain simulation of the line voltage. A recursive convolution algorithm is adopted to carry out the required convolutions efficiently in the transient simulator. Combining this transient simulator with an HPPM extractor yields an efficient transient interconnect signal analysis tool. Work is ongoing to extend the technique to lossy interconnects.
{"title":"Development of a time-domain simulation methodology for the hybrid phase-pole interconnect macromodel","authors":"B. Zhong, S. Dvorak, J. Prince","doi":"10.1109/ECTC.2002.1008236","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008236","url":null,"abstract":"A new hybrid phase-pole macromodel (HPPM) was recently developed for modeling lossless interconnects. Now this HPPM is applied for the transient simulation of interconnects. First, the time-domain waveform is expanded in terms of triangular expansion functions. A knowledge of the triangle impulse response (TIR), which is represented in the form of a HPPM, then allows for the time domain simulation of the line voltage. A recursive convolution algorithm is adopted to carry out the required convolutions efficiently in the transient simulator. Combining this transient simulator with an HPPM extractor yields an efficient transient interconnect signal analysis tool. Work is ongoing to extend the technique to lossy interconnects.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008077
H. T. Vo, C. Davidson, F. Shi
The existing CAD formulae are complicated and inaccurate at high frequencies. In particular, no closed-form expression has been obtained for the effective dielectric constant of microstrip lines on multi-layed dielectric substrate by considering the line-substrate interphase effect, although attempts have been made to study the finite thickness effect of the conductor and dielectric substrate. The present work represents the first attempt to obtain a closed-form CAD formula for the effective dielectric constant of microstrip lines on dielectric substrates by considering the effect of conductor-substrate interphase, in addition to the skin effect losses, dielectric loss, dispersion and radiation losses based on the quasi-TEM assumption and the superposition of partial capacitance. The model is verified by experimental observations on the effective dielectric constant and its dependence on microstrip dimension and frequency.
{"title":"New effective dielectric constant model for ultra-high speed microstrip lines on multilayer dielectric substrates: effect of conductor-dielectric interphase","authors":"H. T. Vo, C. Davidson, F. Shi","doi":"10.1109/ECTC.2002.1008077","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008077","url":null,"abstract":"The existing CAD formulae are complicated and inaccurate at high frequencies. In particular, no closed-form expression has been obtained for the effective dielectric constant of microstrip lines on multi-layed dielectric substrate by considering the line-substrate interphase effect, although attempts have been made to study the finite thickness effect of the conductor and dielectric substrate. The present work represents the first attempt to obtain a closed-form CAD formula for the effective dielectric constant of microstrip lines on dielectric substrates by considering the effect of conductor-substrate interphase, in addition to the skin effect losses, dielectric loss, dispersion and radiation losses based on the quasi-TEM assumption and the superposition of partial capacitance. The model is verified by experimental observations on the effective dielectric constant and its dependence on microstrip dimension and frequency.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008072
A. Jancura, Guang Chen
This paper presents simulation and experimental results for gridded power/ground plane structures in LTCC-modules. The approach of using different simulation techniques for power/ground structures is discussed and a wire-trace model for solid-gridded plane pair based on the transmission line model is derived and verified with measurements.
{"title":"Frequency domain behavior of solid and gridded reference power/ground planes in LTCC modules","authors":"A. Jancura, Guang Chen","doi":"10.1109/ECTC.2002.1008072","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008072","url":null,"abstract":"This paper presents simulation and experimental results for gridded power/ground plane structures in LTCC-modules. The approach of using different simulation techniques for power/ground structures is discussed and a wire-trace model for solid-gridded plane pair based on the transmission line model is derived and verified with measurements.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129125528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008099
Seong Joon Ok, J. Neysmith, D. Baldwin
Micro-Electro-Mechanical-Systems (MEMS) are integrated systems combining electrical and mechanical components, which are fabricated using integrated circuit (IC) batch processing techniques. The influence of MEMS is made possible through their benefits in functionality, size, and reliability. In spite of these remarkable and promising achievements in the field of microsystem fabrication, the commercialization of proven devices are lagged far behind expectations, considerably due to high packaging cost, improper packaging design solution and high testing cost. This paper is focused on suggesting and demonstrating a promising generic, modular, Direct-Chip-Attach (DCA), low cost and high reliable MEMS packaging design strategy and solution applying with high aspect ratio Through-Wafer Electrical Interconnect (TWEI). Fabrication of TWEI using dry etching is relatively new technology that can create more and better packaging options than any other conventional packaging design. The various techniques that can make through-wafer vias conductive are demonstrated and analyzed with advantages and drawbacks.
{"title":"Generic, Direct-Chip-Attach MEMS packaging design with high density and aspect ratio Through-Wafer Electrical Interconnect","authors":"Seong Joon Ok, J. Neysmith, D. Baldwin","doi":"10.1109/ECTC.2002.1008099","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008099","url":null,"abstract":"Micro-Electro-Mechanical-Systems (MEMS) are integrated systems combining electrical and mechanical components, which are fabricated using integrated circuit (IC) batch processing techniques. The influence of MEMS is made possible through their benefits in functionality, size, and reliability. In spite of these remarkable and promising achievements in the field of microsystem fabrication, the commercialization of proven devices are lagged far behind expectations, considerably due to high packaging cost, improper packaging design solution and high testing cost. This paper is focused on suggesting and demonstrating a promising generic, modular, Direct-Chip-Attach (DCA), low cost and high reliable MEMS packaging design strategy and solution applying with high aspect ratio Through-Wafer Electrical Interconnect (TWEI). Fabrication of TWEI using dry etching is relatively new technology that can create more and better packaging options than any other conventional packaging design. The various techniques that can make through-wafer vias conductive are demonstrated and analyzed with advantages and drawbacks.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129220644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008275
Jian Chen, I. De Wolf
In the paper, RS (Raman Spectroscopy) is discussed as a stress sensor in packaging. This paper discusses the measurement of thermo-mechanical stress introduced in the Si chip by packaging. Examples are shown for Si on Cu substrate, flip-chip and PSGA samples. It is shown that the relation between the Raman shift and the stress tensor components depends on the crystallographic orientation of the surface of the sample, i.e. Raman measurements on a [001] surface of a chip give different results than measurements on a cross-section ((1-10) surface). The Raman data are compared with finite element calculations.
本文讨论了拉曼光谱在包装中的应力传感器应用。本文讨论了用封装的方法测量硅片中引入的热机械应力。示例显示了Si on Cu衬底，倒装芯片和PSGA样品。结果表明，拉曼位移和应力张量分量之间的关系取决于样品表面的晶体取向，即在芯片[001]表面上的拉曼测量结果与在截面((1-10)表面上的拉曼测量结果不同。拉曼数据与有限元计算结果进行了比较。
{"title":"Raman spectroscopy as a stress sensor in packaging: correct formulae for different sample surfaces","authors":"Jian Chen, I. De Wolf","doi":"10.1109/ECTC.2002.1008275","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008275","url":null,"abstract":"In the paper, RS (Raman Spectroscopy) is discussed as a stress sensor in packaging. This paper discusses the measurement of thermo-mechanical stress introduced in the Si chip by packaging. Examples are shown for Si on Cu substrate, flip-chip and PSGA samples. It is shown that the relation between the Raman shift and the stress tensor components depends on the crystallographic orientation of the surface of the sample, i.e. Raman measurements on a [001] surface of a chip give different results than measurements on a cross-section ((1-10) surface). The Raman data are compared with finite element calculations.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008163
M. Joodaki, G. Kompa, H. Hillmer
A new technology for integration of high frequency active devices into low cost silicon substrates has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermal stress than the earlier QMIT concepts (Wasige et al., 1999; Joodaki et al., 2001 and 2002). This highly improves the packaging life-time and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of low-loss and high-Q passive elements. Successful integration of low-loss high-Q passive elements on low resistivity Si-substrates in this technology has been achieved for the first time (Joodaki et al., 2002). In comparison to the old concept of QMIT, the elimination of air-bridges in this technology not only reduces the parasitics but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible.
介绍了一种将高频有源器件集成到低成本硅衬底上的新技术。这种新颖的制造工艺具有优异的优点，如极低的热阻，以及比早期QMIT概念低得多的热应力(Wasige等人，1999;Joodaki等人，2001年和2002年)。这大大提高了封装寿命和有源器件的电气特性。制造工艺简单，可用于制造低损耗、高q的无源元件。该技术首次成功地将低损耗高q的无源元件集成到低电阻硅衬底上(Joodaki et al.， 2002)。与QMIT的旧概念相比，该技术中消除了空气桥，不仅减少了寄生，而且可以在测量嵌入式有源器件的微波特性后制作其余电路。这使得非常精确的微波和毫米波设计成为可能。使用新的制造工艺，包含功率器件的微波和毫米波电路(包括共面和微带线)首次成为可能。
{"title":"New generation quasi-monolithic integration technology (QMIT)","authors":"M. Joodaki, G. Kompa, H. Hillmer","doi":"10.1109/ECTC.2002.1008163","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008163","url":null,"abstract":"A new technology for integration of high frequency active devices into low cost silicon substrates has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermal stress than the earlier QMIT concepts (Wasige et al., 1999; Joodaki et al., 2001 and 2002). This highly improves the packaging life-time and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of low-loss and high-Q passive elements. Successful integration of low-loss high-Q passive elements on low resistivity Si-substrates in this technology has been achieved for the first time (Joodaki et al., 2002). In comparison to the old concept of QMIT, the elimination of air-bridges in this technology not only reduces the parasitics but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"7 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008173
L. Martin, J. Frei
Statistical tools and methodologies were used in a process development application to develop the alignment process for high density substrate fabrication. Improved. capability of the alignment process was realized by reducing variation of the scale alignment mode. First, the data range of interest was determined for scale alignment mode. Then, over the determined data range of interest, the measurement capabilities of the measurement systems used in the work were determined by MSA (measurement system analysis). By use of a DOE (design of experiment), the measurement systems were determined to give significantly different measurements, indicating algorithms were necessary to translate available data from one measurement system to the reference measurement system for reducing scaling variation in the alignment process. The available data was found to highly correlate to the reference measurement system. Subsequently, using regression modeling techniques, algorithms were developed that translated available data to scale factors for compensation of the placement of through-vias and outermetal in relation to the microvias, the identified limiting factor to alignment capability.
{"title":"Application of statistical tools and methods for high density substrate process development [printed circuit board fabrication]","authors":"L. Martin, J. Frei","doi":"10.1109/ECTC.2002.1008173","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008173","url":null,"abstract":"Statistical tools and methodologies were used in a process development application to develop the alignment process for high density substrate fabrication. Improved. capability of the alignment process was realized by reducing variation of the scale alignment mode. First, the data range of interest was determined for scale alignment mode. Then, over the determined data range of interest, the measurement capabilities of the measurement systems used in the work were determined by MSA (measurement system analysis). By use of a DOE (design of experiment), the measurement systems were determined to give significantly different measurements, indicating algorithms were necessary to translate available data from one measurement system to the reference measurement system for reducing scaling variation in the alignment process. The available data was found to highly correlate to the reference measurement system. Subsequently, using regression modeling techniques, algorithms were developed that translated available data to scale factors for compensation of the placement of through-vias and outermetal in relation to the microvias, the identified limiting factor to alignment capability.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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