Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616996
D.H. Yom, H. Cheong
A 0.5 /spl mu/ CMOS single chip complex adaptive transversal equalizer for digital wireless communication is presented. The chip contains four 11-tap transversal digital filters and tap coefficient adaptation circuits. The chip can operate at up to 55 MBaud. Power dissipation is 3 Watts at 55 MBaud.
{"title":"A 55 MBaud single chip complex adaptive transversal equalizer for digital wireless communication systems","authors":"D.H. Yom, H. Cheong","doi":"10.1109/ASIC.1997.616996","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616996","url":null,"abstract":"A 0.5 /spl mu/ CMOS single chip complex adaptive transversal equalizer for digital wireless communication is presented. The chip contains four 11-tap transversal digital filters and tap coefficient adaptation circuits. The chip can operate at up to 55 MBaud. Power dissipation is 3 Watts at 55 MBaud.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132831389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617035
J.D. Hayes, D. B. White
Rather than applying the historical approach of using voltage and temperature multipliers to scale timing performance in digital simulators, adders are used to model the change in performance due to variations in operating conditions (voltage and temperature). The adders are treated as functions of input transition rate (Tx) and output load capacitance (Cload) and greatly improve the absolute accuracy of the timing simulator as compared to using multipliers. A methodology for predicting the sensitivity of timing performance to variations in voltage and temperature is presented.
{"title":"Using voltage and temperature adders to account for variations in operating conditions during digital timing simulation","authors":"J.D. Hayes, D. B. White","doi":"10.1109/ASIC.1997.617035","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617035","url":null,"abstract":"Rather than applying the historical approach of using voltage and temperature multipliers to scale timing performance in digital simulators, adders are used to model the change in performance due to variations in operating conditions (voltage and temperature). The adders are treated as functions of input transition rate (Tx) and output load capacitance (Cload) and greatly improve the absolute accuracy of the timing simulator as compared to using multipliers. A methodology for predicting the sensitivity of timing performance to variations in voltage and temperature is presented.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125603804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617030
D. Hsiu-Chun Chiang, R. Schaumann, W. R. Daasch
Experimental procedures and a versatile circuit board designed for testing fully-differential CMOS OTAs are presented. The techniques can be used to measure most DC and AC parameters of an OTA. The approach used leads to guidelines for OTA design.
{"title":"Test board design and measurement techniques for high-frequency fully-differential CMOS OTAs","authors":"D. Hsiu-Chun Chiang, R. Schaumann, W. R. Daasch","doi":"10.1109/ASIC.1997.617030","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617030","url":null,"abstract":"Experimental procedures and a versatile circuit board designed for testing fully-differential CMOS OTAs are presented. The techniques can be used to measure most DC and AC parameters of an OTA. The approach used leads to guidelines for OTA design.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123446891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617033
J.A. Barby, H. Shen
A suite of AHDL models has been developed to enhance the traditional simulation verification of an IC design before it goes to fabrication. A typical IC hardware verification unit is analyzed identifying a minimum subset of simulation models along with their specifications. Proof of concept models were written and tested on a simple IC design to illustrate their usefulness.
{"title":"AHDL models to detect verification problems early in the design process","authors":"J.A. Barby, H. Shen","doi":"10.1109/ASIC.1997.617033","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617033","url":null,"abstract":"A suite of AHDL models has been developed to enhance the traditional simulation verification of an IC design before it goes to fabrication. A typical IC hardware verification unit is analyzed identifying a minimum subset of simulation models along with their specifications. Proof of concept models were written and tested on a simple IC design to illustrate their usefulness.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128467132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617016
A. Martinez-Smith, S. Mathew, R. Sridhar
This paper presents the design and partial implementation of a chip set for a new object-based video coding technique. The hardware algorithm uses unsupervised learning of image contents for efficient second-generation coding of video. Computational complexity is controlled by storing a minimum feature set, upon which higher level contents are defined. Numerical results for test video sequences are given.
{"title":"Design and implementation of an object-based video coder chip set based on syntactic pattern recognition","authors":"A. Martinez-Smith, S. Mathew, R. Sridhar","doi":"10.1109/ASIC.1997.617016","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617016","url":null,"abstract":"This paper presents the design and partial implementation of a chip set for a new object-based video coding technique. The hardware algorithm uses unsupervised learning of image contents for efficient second-generation coding of video. Computational complexity is controlled by storing a minimum feature set, upon which higher level contents are defined. Numerical results for test video sequences are given.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127449584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616992
A. Mathur, P. Parikh, A. Mujumdar, R. Shur, T. Bulgerin, M. Mahmood, S. Desai, P. Juneja
This paper presents an HDL generation method for generating synthesizable Verilog and VHDL models for DSP designs captured using a block-based schematic system. The schematic library consists of parameterized blocks that model various algorithmic functions. A schematic description of a design is first mapped to an HDL (Hardware Description Language) description, which is then synthesized using an RTL (Register-Transfer Level) or a behavioral synthesis tool. The HDL description generated by this method is optimized, easy-to-read and suited for RTL and behavioral synthesis tools. The synthesis results presented for some examples demonstrate the advantages of this technique.
{"title":"HDL generation from parameterized schematic design system","authors":"A. Mathur, P. Parikh, A. Mujumdar, R. Shur, T. Bulgerin, M. Mahmood, S. Desai, P. Juneja","doi":"10.1109/ASIC.1997.616992","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616992","url":null,"abstract":"This paper presents an HDL generation method for generating synthesizable Verilog and VHDL models for DSP designs captured using a block-based schematic system. The schematic library consists of parameterized blocks that model various algorithmic functions. A schematic description of a design is first mapped to an HDL (Hardware Description Language) description, which is then synthesized using an RTL (Register-Transfer Level) or a behavioral synthesis tool. The HDL description generated by this method is optimized, easy-to-read and suited for RTL and behavioral synthesis tools. The synthesis results presented for some examples demonstrate the advantages of this technique.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617008
H. Savoj, Duen-Jeng Wang, D. Hoang, Chi-Lai Hiang
This paper presents a RTL synthesis flow that considers area minimization in mapping to complex cells from a technology library. A mapping decision is made by examining the complete design, If a complex cell in the middle of a design has many redundancies because of the boundary conditions (inputs or outputs of the complex cell are somwehow related) the Boolean equations for the complex cell are simplified and the cell is implemented from single-output Boolean gates. Otherwise, the complex cell from the library is retained. This approach not only achieves smaller design but also improves the testability of the overall design.
{"title":"Optimal complex operator mapping","authors":"H. Savoj, Duen-Jeng Wang, D. Hoang, Chi-Lai Hiang","doi":"10.1109/ASIC.1997.617008","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617008","url":null,"abstract":"This paper presents a RTL synthesis flow that considers area minimization in mapping to complex cells from a technology library. A mapping decision is made by examining the complete design, If a complex cell in the middle of a design has many redundancies because of the boundary conditions (inputs or outputs of the complex cell are somwehow related) the Boolean equations for the complex cell are simplified and the cell is implemented from single-output Boolean gates. Otherwise, the complex cell from the library is retained. This approach not only achieves smaller design but also improves the testability of the overall design.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617014
M. Langhammer
This paper examines methods for the design, implementation, and verification of pipelined adaptive filters in programmable logic. Pipelined adaptive filters can operate at far higher rates than non-pipelined types, but relaxations are required to realize these recursive structures. Design tools that automate the implementation of these filters are demonstrated, along with utilities that allow simulation of the completed system in both fixed and floating point formats. Finally, a communications channel equalization is designed and implemented.
{"title":"Pipelined adaptive filters","authors":"M. Langhammer","doi":"10.1109/ASIC.1997.617014","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617014","url":null,"abstract":"This paper examines methods for the design, implementation, and verification of pipelined adaptive filters in programmable logic. Pipelined adaptive filters can operate at far higher rates than non-pipelined types, but relaxations are required to realize these recursive structures. Design tools that automate the implementation of these filters are demonstrated, along with utilities that allow simulation of the completed system in both fixed and floating point formats. Finally, a communications channel equalization is designed and implemented.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116936599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617031
J. Armstrong
The role of HDL modeling and simulation in the design process is discussed. The modeling process involves both model and model test development. Simulation is used to ensure model correctness. Being able to create HDL models of complex systems is imperative in designing today's systems, but model creation and validation is itself a complex task. Intelligent use of tools is necessary to simplify of this effort. Hardware description languages such as VHDL have a powerful set of constructs, but the modeler must keep in mind the model's application when coding it. Model test benches that can be reused throughout the design cycle and simulation efficiency are critical to effective model testing.
{"title":"Modeling and simulation with hardware description languages","authors":"J. Armstrong","doi":"10.1109/ASIC.1997.617031","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617031","url":null,"abstract":"The role of HDL modeling and simulation in the design process is discussed. The modeling process involves both model and model test development. Simulation is used to ensure model correctness. Being able to create HDL models of complex systems is imperative in designing today's systems, but model creation and validation is itself a complex task. Intelligent use of tools is necessary to simplify of this effort. Hardware description languages such as VHDL have a powerful set of constructs, but the modeler must keep in mind the model's application when coding it. Model test benches that can be reused throughout the design cycle and simulation efficiency are critical to effective model testing.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617001
A. Baganne, J. Philippe, E. Martin
This paper presents a codesign methodology and environment for both hardware and software modules design of telecommunication systems. We describe how High Level Synthesis (HLS) tools like GAUT and SYNDEX can be efficiently used for rapid prototyping of heterogeneous architecture based on DSP TMS320C40 and ASIC. As an illustration, we present a mixed implementation of the GMDF alpha algorithm, an adaptive filter well suited to acoustic echo cancellation, on both ASIC and TS320C40 DSP.
{"title":"Rapid prototyping of telecommunication systems on mixed HW/SW architectures","authors":"A. Baganne, J. Philippe, E. Martin","doi":"10.1109/ASIC.1997.617001","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617001","url":null,"abstract":"This paper presents a codesign methodology and environment for both hardware and software modules design of telecommunication systems. We describe how High Level Synthesis (HLS) tools like GAUT and SYNDEX can be efficiently used for rapid prototyping of heterogeneous architecture based on DSP TMS320C40 and ASIC. As an illustration, we present a mixed implementation of the GMDF alpha algorithm, an adaptive filter well suited to acoustic echo cancellation, on both ASIC and TS320C40 DSP.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"4 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131840339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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