Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617011
P. Astrom, P. Nilsson, M. Torkelsson
A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.
{"title":"Low power optimization of bit-serial digital filters","authors":"P. Astrom, P. Nilsson, M. Torkelsson","doi":"10.1109/ASIC.1997.617011","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617011","url":null,"abstract":"A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"48 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616982
Hyeong-Sook Park, Kyung-Yeol Sohn, Dae-Ho Kim
This paper describes the design and implementation of the modulator in subscriber unit for wideband code division multiple access (CDMA) wireless local loop (WLL) testbed with 5 MHz bandwidth using Field Programmable Gate Array (FPGA) technology. The modulator presented in this paper provides two main functions: it carries out the complete digital modulation process for the reverse link and deinterleaves the forward-link symbols received from the symbol combiner of the demodulating unit. Also, the spectral degradation due to quantization error of filter coefficients and truncation of filter output is simulated. Filter output signals obtained from this implemented modulator are also included.
{"title":"The implementation of modulator using FPGA technology for W-CDMA WLL","authors":"Hyeong-Sook Park, Kyung-Yeol Sohn, Dae-Ho Kim","doi":"10.1109/ASIC.1997.616982","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616982","url":null,"abstract":"This paper describes the design and implementation of the modulator in subscriber unit for wideband code division multiple access (CDMA) wireless local loop (WLL) testbed with 5 MHz bandwidth using Field Programmable Gate Array (FPGA) technology. The modulator presented in this paper provides two main functions: it carries out the complete digital modulation process for the reverse link and deinterleaves the forward-link symbols received from the symbol combiner of the demodulating unit. Also, the spectral degradation due to quantization error of filter coefficients and truncation of filter output is simulated. Filter output signals obtained from this implemented modulator are also included.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132331896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616976
C. Stroud, Piyumani Karunaratna, E. Bradley
We describe the design and operation of a digital test pattern generator (TPG) along with three accumulator based output response analysis (ORA) circuits that are targeted for implementing Built-In Self-Test (BIST) for analog circuits in mixed signal based ASICs. The test patterns produced by the TPG include ramps, triangle and square waves, pseudo-random noise, and a frequency sweep capability for testing the frequency response of the analog circuit under test. The ORA circuits include single and double precision as well as residue accumulators for magnitude and phase measurements. We include an overview of the complete mixed signal based BIST architecture and simulation system along with the results of our initial application of the BIST architecture to an analog circuit under test.
{"title":"Digital components for built-in self-test of analog circuits","authors":"C. Stroud, Piyumani Karunaratna, E. Bradley","doi":"10.1109/ASIC.1997.616976","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616976","url":null,"abstract":"We describe the design and operation of a digital test pattern generator (TPG) along with three accumulator based output response analysis (ORA) circuits that are targeted for implementing Built-In Self-Test (BIST) for analog circuits in mixed signal based ASICs. The test patterns produced by the TPG include ramps, triangle and square waves, pseudo-random noise, and a frequency sweep capability for testing the frequency response of the analog circuit under test. The ORA circuits include single and double precision as well as residue accumulators for magnitude and phase measurements. We include an overview of the complete mixed signal based BIST architecture and simulation system along with the results of our initial application of the BIST architecture to an analog circuit under test.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"243 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130700458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616993
D. Upp
The explosive growth of the Internet is the single most important factor influencing global networking today. With over 40 million users and demand increasing at a rate of nearly 20% per month, the Internet accounts for the bulk of new data traffic, particularly in local exchanges. Dealing with this phenomenal growth and determining how to profit from it is one of the most pressing problems of telephone operating companies. Today's standard access methods for public and Wide Area Networks (WANs) using dial-up modems are inadequate to the task of delivering data at higher speeds. The use of Digital Subscriber Loop (DSL) technologies offers one of the best network access options for public carriers.
{"title":"DSL technology shifts carriers to the passing lane for Internet access","authors":"D. Upp","doi":"10.1109/ASIC.1997.616993","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616993","url":null,"abstract":"The explosive growth of the Internet is the single most important factor influencing global networking today. With over 40 million users and demand increasing at a rate of nearly 20% per month, the Internet accounts for the bulk of new data traffic, particularly in local exchanges. Dealing with this phenomenal growth and determining how to profit from it is one of the most pressing problems of telephone operating companies. Today's standard access methods for public and Wide Area Networks (WANs) using dial-up modems are inadequate to the task of delivering data at higher speeds. The use of Digital Subscriber Loop (DSL) technologies offers one of the best network access options for public carriers.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134303413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616974
M. Al-Qutayri, W. Tenten, P. Shepherd
This paper presents the design of a unified supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit in a simulation environment are outlined.
{"title":"A prototype supply current monitor for testing analogue circuits","authors":"M. Al-Qutayri, W. Tenten, P. Shepherd","doi":"10.1109/ASIC.1997.616974","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616974","url":null,"abstract":"This paper presents the design of a unified supply current monitor for the detection of faults in analogue circuits. The emphasis is placed on the design of a monitor with minimum overhead that can be implemented to detect variations in the dynamic supply current. The design of the monitor and the results of using it to detect faults in an analogue circuit in a simulation environment are outlined.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616967
Anan Tha Chandrakasan
Supply voltage scaling to 1 V and below is the key to low-power system design. Threshold voltage reduction enables aggressive supply scaling but increases leakage power. Emerging technologies such as MTCMOS and variable threshold bulk/SOI will be essential in controlling leakage while achieving high performance levels at low supply voltages. Power can also be reduced by adaptively varying the supply voltage in applications where the computational workload varies with time. Aggressive voltage and power level scaling requires efficient DC-DC conversion circuitry and in some cases, it is necessary to embed this function in the processor.
{"title":"Voltage reduction techniques for portable systems","authors":"Anan Tha Chandrakasan","doi":"10.1109/ASIC.1997.616967","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616967","url":null,"abstract":"Supply voltage scaling to 1 V and below is the key to low-power system design. Threshold voltage reduction enables aggressive supply scaling but increases leakage power. Emerging technologies such as MTCMOS and variable threshold bulk/SOI will be essential in controlling leakage while achieving high performance levels at low supply voltages. Power can also be reduced by adaptively varying the supply voltage in applications where the computational workload varies with time. Aggressive voltage and power level scaling requires efficient DC-DC conversion circuitry and in some cases, it is necessary to embed this function in the processor.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"54 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116534690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617012
Myeong-Hwan Lee, D. Han, Hyun-Soo Shin, Ki-bum Kim, D. song, Du Nguyen, Steve Ku, Sung-Sam Im
In this paper, we present ASIC design and implementation of vestigial sideband (VSB) demodulator for high definition television (HDTV) system employing the VSB modulation technique. We present three ASIC chips for VSB demodulator implementation.
{"title":"VSB demodulator ASIC design and development for HDTV system","authors":"Myeong-Hwan Lee, D. Han, Hyun-Soo Shin, Ki-bum Kim, D. song, Du Nguyen, Steve Ku, Sung-Sam Im","doi":"10.1109/ASIC.1997.617012","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617012","url":null,"abstract":"In this paper, we present ASIC design and implementation of vestigial sideband (VSB) demodulator for high definition television (HDTV) system employing the VSB modulation technique. We present three ASIC chips for VSB demodulator implementation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129814504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617010
Hanho Lee, G. Sobelman
This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.
{"title":"FPGA-based FIR filters using digit-serial arithmetic","authors":"Hanho Lee, G. Sobelman","doi":"10.1109/ASIC.1997.617010","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617010","url":null,"abstract":"This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126361857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616998
Vasily G. Moshnyaga, Keikichi Tamaru
Architectural transformations are efficient means for reducing energy consumption of portable devices. In this paper we survey state-of-the-art techniques that target energy saving in the architecture design, and outline difficulties in their practical implementation. Future challenges in low energy architecture design are summarized.
{"title":"Energy saving techniques for architecture design of portable embedded devices","authors":"Vasily G. Moshnyaga, Keikichi Tamaru","doi":"10.1109/ASIC.1997.616998","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616998","url":null,"abstract":"Architectural transformations are efficient means for reducing energy consumption of portable devices. In this paper we survey state-of-the-art techniques that target energy saving in the architecture design, and outline difficulties in their practical implementation. Future challenges in low energy architecture design are summarized.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129439542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASIC.1997.617015
S. Naess, T. Lande
This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block.
{"title":"Synthesis of building blocks for low-power stochastic pulse coded systems","authors":"S. Naess, T. Lande","doi":"10.1109/ASIC.1997.617015","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617015","url":null,"abstract":"This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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