Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617013
D. Hung, H. D. Cheng, S. Sengkhamyong
In image processing, moment-invariant is one of the most useful methods for feature extraction. However, real-time applications of this method have been prohibited due to the intensive computation required in calculating the moments of an image. This paper describes a hardware solution to this problem.
{"title":"A reconfigurable hardware accelerator for moment computation","authors":"D. Hung, H. D. Cheng, S. Sengkhamyong","doi":"10.1109/ASIC.1997.617013","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617013","url":null,"abstract":"In image processing, moment-invariant is one of the most useful methods for feature extraction. However, real-time applications of this method have been prohibited due to the intensive computation required in calculating the moments of an image. This paper describes a hardware solution to this problem.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"71 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617020
B. L. Morris
This paper describes an output buffer which is capable of producing a 5 volt output voltage in a 3 volt technology, without exceeding 3.6 volts across a gate or drain-to-source of any transistor in the circuit. The buffer requires a 5 volt supply in addition to the normal (3.3 volt) supply. This buffer has been manufactured in the Lucent Technologies 0.35 /spl mu/m 3 volt technology.
{"title":"A 5 volt drive output buffer in a 3 volt technology","authors":"B. L. Morris","doi":"10.1109/ASIC.1997.617020","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617020","url":null,"abstract":"This paper describes an output buffer which is capable of producing a 5 volt output voltage in a 3 volt technology, without exceeding 3.6 volts across a gate or drain-to-source of any transistor in the circuit. The buffer requires a 5 volt supply in addition to the normal (3.3 volt) supply. This buffer has been manufactured in the Lucent Technologies 0.35 /spl mu/m 3 volt technology.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125570724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616985
D. Navarro, J.I. Garcia-Nicolas, I. Parada, M. A. Lopez, A. Roy, C. Paz
A circuit that receives and process analog signals from the telephone line is presented; it generates dialing signals, and controls a number of electrical functions (power supply, ...) and mechanical functions (hanging, money-box, ...). This circuit replaces digital and analog electronic components in an existing printed circuit board. One of its main functions is to reduce phone operating power consumption.
{"title":"ASIC for signal processing and control for public telephones","authors":"D. Navarro, J.I. Garcia-Nicolas, I. Parada, M. A. Lopez, A. Roy, C. Paz","doi":"10.1109/ASIC.1997.616985","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616985","url":null,"abstract":"A circuit that receives and process analog signals from the telephone line is presented; it generates dialing signals, and controls a number of electrical functions (power supply, ...) and mechanical functions (hanging, money-box, ...). This circuit replaces digital and analog electronic components in an existing printed circuit board. One of its main functions is to reduce phone operating power consumption.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617007
Wei Huang, A. Kahng
We describe a "topology advisor" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parameter) that satisfy all constraints are returned. Efficient implementations of exhaustive search are used to guarantee optimal results when practical, and otherwise yield fast, high-quality results (if the problem is large or if the constraints are loose). Practical features include: (i) modeling of per-region and per-layer routing costs, (ii) routing to terminals located inside blocks, (iii) optional splitting of k-pin bus routes when the optimal routing passes through narrow channels, and (iv) heuristic speedups based on clustering and sampling.
{"title":"A layout advisor for timing-critical bus routing","authors":"Wei Huang, A. Kahng","doi":"10.1109/ASIC.1997.617007","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617007","url":null,"abstract":"We describe a \"topology advisor\" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parameter) that satisfy all constraints are returned. Efficient implementations of exhaustive search are used to guarantee optimal results when practical, and otherwise yield fast, high-quality results (if the problem is large or if the constraints are loose). Practical features include: (i) modeling of per-region and per-layer routing costs, (ii) routing to terminals located inside blocks, (iii) optional splitting of k-pin bus routes when the optimal routing passes through narrow channels, and (iv) heuristic speedups based on clustering and sampling.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122223176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617003
Zhanping Chen, K. Roy
Power dissipation in CMOS circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. In this paper, we present a novel statistical approach to accurately estimate the maximum and minimum bounds for average power of sequential circuits using a technique which estimates the sensitivities of average power dissipation to primary input signal properties. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). The sensitivities are obtained as a by-product of the statistical power estimation technique using a Monte Carlo based approach. Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.
{"title":"An efficient statistical method to estimate average power in sequential circuits considering input sensitivities","authors":"Zhanping Chen, K. Roy","doi":"10.1109/ASIC.1997.617003","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617003","url":null,"abstract":"Power dissipation in CMOS circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. In this paper, we present a novel statistical approach to accurately estimate the maximum and minimum bounds for average power of sequential circuits using a technique which estimates the sensitivities of average power dissipation to primary input signal properties. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). The sensitivities are obtained as a by-product of the statistical power estimation technique using a Monte Carlo based approach. Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133850848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616975
P. Fasang
An optimal method for testing a type of 8-bit digital to analog converters is presented. The method uses 89 out of 256 test vectors. The method for selecting the 89 vectors is explained. It is also pointed out that digital to analog converters of the type described in this paper are tested with 100% fault coverage with the 89 vectors. In addition, the 89 vectors also test for simultaneously switching errors (noise induced errors) and differential linearity. A discussion on the type of code which is used for designing this type of digital to analog converters which renders optimal testing (with 89 vectors) is included.
{"title":"An optimal method for testing digital to analog converters","authors":"P. Fasang","doi":"10.1109/ASIC.1997.616975","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616975","url":null,"abstract":"An optimal method for testing a type of 8-bit digital to analog converters is presented. The method uses 89 out of 256 test vectors. The method for selecting the 89 vectors is explained. It is also pointed out that digital to analog converters of the type described in this paper are tested with 100% fault coverage with the 89 vectors. In addition, the 89 vectors also test for simultaneously switching errors (noise induced errors) and differential linearity. A discussion on the type of code which is used for designing this type of digital to analog converters which renders optimal testing (with 89 vectors) is included.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"67 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617005
M. Tachibana
In this paper, a heuristic algorithm for free BDD node minimization is presented. This algorithm is designed to minimize small size FBDDs with application to synthesize pass transistor logic gate families. Experimental results based on 169 single output functions from MCNC benchmark two-level logic examples indicate 22 to 24% reduction of node count compared with initial ROBDD. Also, experimental results based on HWB functions (N=3-16) indicate node count reduced to 30 to 40% larger than the theoretical limit.
{"title":"Synthesize pass transistor logic gate by using free binary decision diagram","authors":"M. Tachibana","doi":"10.1109/ASIC.1997.617005","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617005","url":null,"abstract":"In this paper, a heuristic algorithm for free BDD node minimization is presented. This algorithm is designed to minimize small size FBDDs with application to synthesize pass transistor logic gate families. Experimental results based on 169 single output functions from MCNC benchmark two-level logic examples indicate 22 to 24% reduction of node count compared with initial ROBDD. Also, experimental results based on HWB functions (N=3-16) indicate node count reduced to 30 to 40% larger than the theoretical limit.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128524534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616980
J.J. Niewiadomski, B. Carlson
The design and prototype of a read-out integrated circuit for an uncooled infrared focal plane array are described in this paper. The device is designed to interface to a pyroelectric infrared detector array of size 320/spl times/240. The read-out IC presented here achieves better performance and uniformity compared to existing approaches by implementing a single stage CMOS op-amp within each pixel of the detector array. The prototype devices exhibit fixed pattern noise less than 5 mv (0.5% of full scale) without correction. The pixel amplifier exhibits less than 0.6% maximum (0.5% average) relative gain error with less than 0.2% gain variation over the 1 V input range.
{"title":"CMOS read-out IC with op-amp pixel amplifier for infrared focal plane arrays","authors":"J.J. Niewiadomski, B. Carlson","doi":"10.1109/ASIC.1997.616980","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616980","url":null,"abstract":"The design and prototype of a read-out integrated circuit for an uncooled infrared focal plane array are described in this paper. The device is designed to interface to a pyroelectric infrared detector array of size 320/spl times/240. The read-out IC presented here achieves better performance and uniformity compared to existing approaches by implementing a single stage CMOS op-amp within each pixel of the detector array. The prototype devices exhibit fixed pattern noise less than 5 mv (0.5% of full scale) without correction. The pixel amplifier exhibits less than 0.6% maximum (0.5% average) relative gain error with less than 0.2% gain variation over the 1 V input range.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128567765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616999
E. Gayles, K. Acken, R. Owens, M. J. Irwin
Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds.
{"title":"A robust CMOS logic technique for building high frequency circuits with efficient pipelining","authors":"E. Gayles, K. Acken, R. Owens, M. J. Irwin","doi":"10.1109/ASIC.1997.616999","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616999","url":null,"abstract":"Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127630169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617019
P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler
This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.
{"title":"I/O impedance matching algorithm for high-performance ASICs","authors":"P. Zuchowski, J. H. Panner, D. Stout, J. Adams, F. Chan, P. Dunn, A. D. Huber, J. J. Oler","doi":"10.1109/ASIC.1997.617019","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617019","url":null,"abstract":"This paper discusses a design style that utilizes an area array of flip-chip solder bump connections, I/O circuit designs that implement a programmable impedance matching algorithm, and a design system that must utilize these features during chip layout, chip checking, and release to manufacturing. Results from a recent test chip are also given.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122305978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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