Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617033
J.A. Barby, H. Shen
A suite of AHDL models has been developed to enhance the traditional simulation verification of an IC design before it goes to fabrication. A typical IC hardware verification unit is analyzed identifying a minimum subset of simulation models along with their specifications. Proof of concept models were written and tested on a simple IC design to illustrate their usefulness.
{"title":"AHDL models to detect verification problems early in the design process","authors":"J.A. Barby, H. Shen","doi":"10.1109/ASIC.1997.617033","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617033","url":null,"abstract":"A suite of AHDL models has been developed to enhance the traditional simulation verification of an IC design before it goes to fabrication. A typical IC hardware verification unit is analyzed identifying a minimum subset of simulation models along with their specifications. Proof of concept models were written and tested on a simple IC design to illustrate their usefulness.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128467132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617009
R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris
Companies such as Lucent Technologies, which was involved in pioneering efforts such as the AT&T DSP16C in 1989, have been integrating mixed-signal and DSP for close to ten years. New techniques and expertise support integration earlier in the product life-cycle with minimal risk. In fact, many mixed-signal integrated solutions implemented by Lucent's technical staff achieved fully functional first silicon. Techniques such as those described in this paper are necessary steps along the way to achieving fully integrated digital communication ultrachips.
{"title":"Mixed-signal considerations when integrating systems","authors":"R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris","doi":"10.1109/ASIC.1997.617009","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617009","url":null,"abstract":"Companies such as Lucent Technologies, which was involved in pioneering efforts such as the AT&T DSP16C in 1989, have been integrating mixed-signal and DSP for close to ten years. New techniques and expertise support integration earlier in the product life-cycle with minimal risk. In fact, many mixed-signal integrated solutions implemented by Lucent's technical staff achieved fully functional first silicon. Techniques such as those described in this paper are necessary steps along the way to achieving fully integrated digital communication ultrachips.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617026
P.K. Oborn, D. Comer
This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using "virtual resistance coding" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.
{"title":"A new digital to analog converter resistor string architecture","authors":"P.K. Oborn, D. Comer","doi":"10.1109/ASIC.1997.617026","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617026","url":null,"abstract":"This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using \"virtual resistance coding\" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616971
Y. Berg, T. Lande, S. Naess
In this paper we propose a novel design of low-voltage current mirrors using floating gates. Floating gate UV-light programmable MOS transistors (FGUVMOS) are used to design current mirrors in low-voltage/low-power analog applications. The capacitive divider inputs to the floating gates can he utilized to reduce current mismatch due to Early effect.
{"title":"Low-voltage floating-gate current mirrors","authors":"Y. Berg, T. Lande, S. Naess","doi":"10.1109/ASIC.1997.616971","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616971","url":null,"abstract":"In this paper we propose a novel design of low-voltage current mirrors using floating gates. Floating gate UV-light programmable MOS transistors (FGUVMOS) are used to design current mirrors in low-voltage/low-power analog applications. The capacitive divider inputs to the floating gates can he utilized to reduce current mismatch due to Early effect.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617029
Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim
This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.
{"title":"Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach","authors":"Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim","doi":"10.1109/ASIC.1997.617029","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617029","url":null,"abstract":"This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617032
M. Cirstea, M. G. Giamusi, M. McCormick
This paper illustrates the advantages of silicon implementation of a digital controller for 3-phase 6-pulse power rectifiers, using Electronic Design Automation (EDA) techniques. The control Application Specific Integrated Circuit (ASIC) was simulated and then implemented into a XILINX Field Programmable Gate Array (FPGA). The paper describes the practical achievement of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunction with a high noise immunity. The complete 6-pulse controller including the ASIC, the zero-crossing detector and an interface circuit was commissioned and is currently being comprehensively tested.
{"title":"A modern ASIC controller for a 6-pulse rectifier","authors":"M. Cirstea, M. G. Giamusi, M. McCormick","doi":"10.1109/ASIC.1997.617032","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617032","url":null,"abstract":"This paper illustrates the advantages of silicon implementation of a digital controller for 3-phase 6-pulse power rectifiers, using Electronic Design Automation (EDA) techniques. The control Application Specific Integrated Circuit (ASIC) was simulated and then implemented into a XILINX Field Programmable Gate Array (FPGA). The paper describes the practical achievement of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunction with a high noise immunity. The complete 6-pulse controller including the ASIC, the zero-crossing detector and an interface circuit was commissioned and is currently being comprehensively tested.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117314950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616990
T. Schlipf, T. Buchner, R. Fritz, M. Helms
Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.
{"title":"An easy approach to formal verification","authors":"T. Schlipf, T. Buchner, R. Fritz, M. Helms","doi":"10.1109/ASIC.1997.616990","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616990","url":null,"abstract":"Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616970
L.K. Wang, H.H. Chen
This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.
{"title":"A low power high speed error correction code macro using complementary pass transistor logic circuit","authors":"L.K. Wang, H.H. Chen","doi":"10.1109/ASIC.1997.616970","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616970","url":null,"abstract":"This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616989
Kyung-Im Son, Heung-Joon Park, M. Soma
This paper proposes a new technique to estimate the feasibility/performance surfaces of mixed-signal circuits. The estimates will be used to construct a multi-class classifier which can be used as an automatic topology selector for the top-down design of analog circuits. The technique employs an ANN classification algorithm that requires no a priori knowledge of the complexity or shape of estimated surfaces. The estimation is optimized with respect to the training data size using a query-based data growing technique. As a case study, the feasibility/performance surfaces of sub-circuits in a 2nd order /spl Sigma/-/spl Delta/ ADC are estimated. The estimation results confirm the generality of the proposed method. Estimated surfaces can be updated swiftly as the process technology evolves, which makes our technique nearly process technology independent.
{"title":"Automatic feasibility/performance estimation of mixed-signal circuits based on design specifications","authors":"Kyung-Im Son, Heung-Joon Park, M. Soma","doi":"10.1109/ASIC.1997.616989","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616989","url":null,"abstract":"This paper proposes a new technique to estimate the feasibility/performance surfaces of mixed-signal circuits. The estimates will be used to construct a multi-class classifier which can be used as an automatic topology selector for the top-down design of analog circuits. The technique employs an ANN classification algorithm that requires no a priori knowledge of the complexity or shape of estimated surfaces. The estimation is optimized with respect to the training data size using a query-based data growing technique. As a case study, the feasibility/performance surfaces of sub-circuits in a 2nd order /spl Sigma/-/spl Delta/ ADC are estimated. The estimation results confirm the generality of the proposed method. Estimated surfaces can be updated swiftly as the process technology evolves, which makes our technique nearly process technology independent.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616984
A. Titus, T. Drabik
This paper describes a unique implementation of an optical-in/optical-out focal-plane processor with improved performance and increased control over the output that uses differential difference amplifiers and a clocked-analog scheme. This is accomplished on a single chip and represents a step toward creating a low-power, compact, visual processing system.
{"title":"An improved silicon retina chip with optical input and optical output","authors":"A. Titus, T. Drabik","doi":"10.1109/ASIC.1997.616984","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616984","url":null,"abstract":"This paper describes a unique implementation of an optical-in/optical-out focal-plane processor with improved performance and increased control over the output that uses differential difference amplifiers and a clocked-analog scheme. This is accomplished on a single chip and represents a step toward creating a low-power, compact, visual processing system.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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