Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617021
H. Chi, D. Stout, J. Chickanosky
A control circuit that compensates for variations in process, voltage and temperature (PVT) has been developed to control off-chip-driver circuits used for sub-0.25-/spl mu/m technology. The off-chip-driver (OCD), alone with a simple control scheme, delivers a tight impedance tolerance at the output, improving the output signal waveforms. Across-chip length variation (ACLV), the controlled-circuit design and off-chip-driver performance are also discussed.
{"title":"Process, voltage and temperature compensation of off-chip-driver circuits for sub-0.25-/spl mu/m CMOS technology","authors":"H. Chi, D. Stout, J. Chickanosky","doi":"10.1109/ASIC.1997.617021","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617021","url":null,"abstract":"A control circuit that compensates for variations in process, voltage and temperature (PVT) has been developed to control off-chip-driver circuits used for sub-0.25-/spl mu/m technology. The off-chip-driver (OCD), alone with a simple control scheme, delivers a tight impedance tolerance at the output, improving the output signal waveforms. Across-chip length variation (ACLV), the controlled-circuit design and off-chip-driver performance are also discussed.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617009
R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris
Companies such as Lucent Technologies, which was involved in pioneering efforts such as the AT&T DSP16C in 1989, have been integrating mixed-signal and DSP for close to ten years. New techniques and expertise support integration earlier in the product life-cycle with minimal risk. In fact, many mixed-signal integrated solutions implemented by Lucent's technical staff achieved fully functional first silicon. Techniques such as those described in this paper are necessary steps along the way to achieving fully integrated digital communication ultrachips.
{"title":"Mixed-signal considerations when integrating systems","authors":"R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris","doi":"10.1109/ASIC.1997.617009","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617009","url":null,"abstract":"Companies such as Lucent Technologies, which was involved in pioneering efforts such as the AT&T DSP16C in 1989, have been integrating mixed-signal and DSP for close to ten years. New techniques and expertise support integration earlier in the product life-cycle with minimal risk. In fact, many mixed-signal integrated solutions implemented by Lucent's technical staff achieved fully functional first silicon. Techniques such as those described in this paper are necessary steps along the way to achieving fully integrated digital communication ultrachips.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616990
T. Schlipf, T. Buchner, R. Fritz, M. Helms
Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.
{"title":"An easy approach to formal verification","authors":"T. Schlipf, T. Buchner, R. Fritz, M. Helms","doi":"10.1109/ASIC.1997.616990","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616990","url":null,"abstract":"Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616984
A. Titus, T. Drabik
This paper describes a unique implementation of an optical-in/optical-out focal-plane processor with improved performance and increased control over the output that uses differential difference amplifiers and a clocked-analog scheme. This is accomplished on a single chip and represents a step toward creating a low-power, compact, visual processing system.
{"title":"An improved silicon retina chip with optical input and optical output","authors":"A. Titus, T. Drabik","doi":"10.1109/ASIC.1997.616984","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616984","url":null,"abstract":"This paper describes a unique implementation of an optical-in/optical-out focal-plane processor with improved performance and increased control over the output that uses differential difference amplifiers and a clocked-analog scheme. This is accomplished on a single chip and represents a step toward creating a low-power, compact, visual processing system.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616971
Y. Berg, T. Lande, S. Naess
In this paper we propose a novel design of low-voltage current mirrors using floating gates. Floating gate UV-light programmable MOS transistors (FGUVMOS) are used to design current mirrors in low-voltage/low-power analog applications. The capacitive divider inputs to the floating gates can he utilized to reduce current mismatch due to Early effect.
{"title":"Low-voltage floating-gate current mirrors","authors":"Y. Berg, T. Lande, S. Naess","doi":"10.1109/ASIC.1997.616971","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616971","url":null,"abstract":"In this paper we propose a novel design of low-voltage current mirrors using floating gates. Floating gate UV-light programmable MOS transistors (FGUVMOS) are used to design current mirrors in low-voltage/low-power analog applications. The capacitive divider inputs to the floating gates can he utilized to reduce current mismatch due to Early effect.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617025
N. Verghese, D. Allstot
This paper overviews substrate coupling in mixed mode and RF integrated circuits. Verification methods are reviewed with emphasis on modeling techniques for the substrate. An efficient substrate coupling simulation methodology is presented that utilizes macromodels of the circuit, substrate and package, and a design example is illustrated.
{"title":"Substrate coupling in mixed-mode and RF integrated circuits","authors":"N. Verghese, D. Allstot","doi":"10.1109/ASIC.1997.617025","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617025","url":null,"abstract":"This paper overviews substrate coupling in mixed mode and RF integrated circuits. Verification methods are reviewed with emphasis on modeling techniques for the substrate. An efficient substrate coupling simulation methodology is presented that utilizes macromodels of the circuit, substrate and package, and a design example is illustrated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114924742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617002
A. Bhavnagarwala, B. Austin, J. Meindl
Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.
{"title":"Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010","authors":"A. Bhavnagarwala, B. Austin, J. Meindl","doi":"10.1109/ASIC.1997.617002","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617002","url":null,"abstract":"Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131074547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617026
P.K. Oborn, D. Comer
This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using "virtual resistance coding" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.
{"title":"A new digital to analog converter resistor string architecture","authors":"P.K. Oborn, D. Comer","doi":"10.1109/ASIC.1997.617026","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617026","url":null,"abstract":"This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using \"virtual resistance coding\" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617017
R. Frye
Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.
{"title":"Design issues for flip-chip ICs in multilayer packages","authors":"R. Frye","doi":"10.1109/ASIC.1997.617017","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617017","url":null,"abstract":"Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130961996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617029
Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim
This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.
{"title":"Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach","authors":"Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim","doi":"10.1109/ASIC.1997.617029","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617029","url":null,"abstract":"This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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