Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617017
R. Frye
Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.
{"title":"Design issues for flip-chip ICs in multilayer packages","authors":"R. Frye","doi":"10.1109/ASIC.1997.617017","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617017","url":null,"abstract":"Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130961996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616981
D. Pok, C.-i.H. Chen
In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.
{"title":"Testable VLSI circuit design of SIMD graphics engine","authors":"D. Pok, C.-i.H. Chen","doi":"10.1109/ASIC.1997.616981","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616981","url":null,"abstract":"In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617002
A. Bhavnagarwala, B. Austin, J. Meindl
Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.
{"title":"Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010","authors":"A. Bhavnagarwala, B. Austin, J. Meindl","doi":"10.1109/ASIC.1997.617002","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617002","url":null,"abstract":"Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131074547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617025
N. Verghese, D. Allstot
This paper overviews substrate coupling in mixed mode and RF integrated circuits. Verification methods are reviewed with emphasis on modeling techniques for the substrate. An efficient substrate coupling simulation methodology is presented that utilizes macromodels of the circuit, substrate and package, and a design example is illustrated.
{"title":"Substrate coupling in mixed-mode and RF integrated circuits","authors":"N. Verghese, D. Allstot","doi":"10.1109/ASIC.1997.617025","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617025","url":null,"abstract":"This paper overviews substrate coupling in mixed mode and RF integrated circuits. Verification methods are reviewed with emphasis on modeling techniques for the substrate. An efficient substrate coupling simulation methodology is presented that utilizes macromodels of the circuit, substrate and package, and a design example is illustrated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114924742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616987
C. Yeh
Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.
{"title":"Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs","authors":"C. Yeh","doi":"10.1109/ASIC.1997.616987","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616987","url":null,"abstract":"Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114294274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616979
H. Werkmann, B. Hofflinger, B. Laquai
A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their effects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan test systems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.
{"title":"Boundary scan adaption for active substrate MCM-test","authors":"H. Werkmann, B. Hofflinger, B. Laquai","doi":"10.1109/ASIC.1997.616979","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616979","url":null,"abstract":"A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their effects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan test systems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617024
T. Gabara
A new set of terminals has been introduced to control the behavior of an MOS device. A magnetic field, formed when current flows through an on-chip coil, is applied to the inversion layer of an MOS device. The generated Lorentz force is applied to the carriers in the inversion layer to alter the characteristics of the MOS device. The magnetic field is applied parallel to the inversion layer and perpendicular to the carrier flow. Measurement results using this structure as a 1.8 GHz mixer are given. Measurements demonstrate that the interaction between the coil and the MOS device is primarily due to the Lorentz force. The capacitive coupling effect between the coil and the device plays a minor role.
{"title":"Lorentz force MOS transistor","authors":"T. Gabara","doi":"10.1109/ASIC.1997.617024","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617024","url":null,"abstract":"A new set of terminals has been introduced to control the behavior of an MOS device. A magnetic field, formed when current flows through an on-chip coil, is applied to the inversion layer of an MOS device. The generated Lorentz force is applied to the carriers in the inversion layer to alter the characteristics of the MOS device. The magnetic field is applied parallel to the inversion layer and perpendicular to the carrier flow. Measurement results using this structure as a 1.8 GHz mixer are given. Measurements demonstrate that the interaction between the coil and the MOS device is primarily due to the Lorentz force. The capacitive coupling effect between the coil and the device plays a minor role.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130199772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616977
Sangyun Han, Sungho Kang
Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults.
{"title":"Efficient redundancy identification for test pattern generation","authors":"Sangyun Han, Sungho Kang","doi":"10.1109/ASIC.1997.616977","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616977","url":null,"abstract":"Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129210360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617011
P. Astrom, P. Nilsson, M. Torkelsson
A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.
{"title":"Low power optimization of bit-serial digital filters","authors":"P. Astrom, P. Nilsson, M. Torkelsson","doi":"10.1109/ASIC.1997.617011","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617011","url":null,"abstract":"A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"48 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616986
D. Hill, A. Domic
Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional "over the wall" methodology. Section 3 then proposes a "limited loops" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.
{"title":"On the relationship among accuracy, tolerance and compensation in the deep sub-micron era","authors":"D. Hill, A. Domic","doi":"10.1109/ASIC.1997.616986","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616986","url":null,"abstract":"Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional \"over the wall\" methodology. Section 3 then proposes a \"limited loops\" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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