Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617032
M. Cirstea, M. G. Giamusi, M. McCormick
This paper illustrates the advantages of silicon implementation of a digital controller for 3-phase 6-pulse power rectifiers, using Electronic Design Automation (EDA) techniques. The control Application Specific Integrated Circuit (ASIC) was simulated and then implemented into a XILINX Field Programmable Gate Array (FPGA). The paper describes the practical achievement of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunction with a high noise immunity. The complete 6-pulse controller including the ASIC, the zero-crossing detector and an interface circuit was commissioned and is currently being comprehensively tested.
{"title":"A modern ASIC controller for a 6-pulse rectifier","authors":"M. Cirstea, M. G. Giamusi, M. McCormick","doi":"10.1109/ASIC.1997.617032","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617032","url":null,"abstract":"This paper illustrates the advantages of silicon implementation of a digital controller for 3-phase 6-pulse power rectifiers, using Electronic Design Automation (EDA) techniques. The control Application Specific Integrated Circuit (ASIC) was simulated and then implemented into a XILINX Field Programmable Gate Array (FPGA). The paper describes the practical achievement of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunction with a high noise immunity. The complete 6-pulse controller including the ASIC, the zero-crossing detector and an interface circuit was commissioned and is currently being comprehensively tested.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117314950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616970
L.K. Wang, H.H. Chen
This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.
{"title":"A low power high speed error correction code macro using complementary pass transistor logic circuit","authors":"L.K. Wang, H.H. Chen","doi":"10.1109/ASIC.1997.616970","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616970","url":null,"abstract":"This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616989
Kyung-Im Son, Heung-Joon Park, M. Soma
This paper proposes a new technique to estimate the feasibility/performance surfaces of mixed-signal circuits. The estimates will be used to construct a multi-class classifier which can be used as an automatic topology selector for the top-down design of analog circuits. The technique employs an ANN classification algorithm that requires no a priori knowledge of the complexity or shape of estimated surfaces. The estimation is optimized with respect to the training data size using a query-based data growing technique. As a case study, the feasibility/performance surfaces of sub-circuits in a 2nd order /spl Sigma/-/spl Delta/ ADC are estimated. The estimation results confirm the generality of the proposed method. Estimated surfaces can be updated swiftly as the process technology evolves, which makes our technique nearly process technology independent.
{"title":"Automatic feasibility/performance estimation of mixed-signal circuits based on design specifications","authors":"Kyung-Im Son, Heung-Joon Park, M. Soma","doi":"10.1109/ASIC.1997.616989","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616989","url":null,"abstract":"This paper proposes a new technique to estimate the feasibility/performance surfaces of mixed-signal circuits. The estimates will be used to construct a multi-class classifier which can be used as an automatic topology selector for the top-down design of analog circuits. The technique employs an ANN classification algorithm that requires no a priori knowledge of the complexity or shape of estimated surfaces. The estimation is optimized with respect to the training data size using a query-based data growing technique. As a case study, the feasibility/performance surfaces of sub-circuits in a 2nd order /spl Sigma/-/spl Delta/ ADC are estimated. The estimation results confirm the generality of the proposed method. Estimated surfaces can be updated swiftly as the process technology evolves, which makes our technique nearly process technology independent.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616981
D. Pok, C.-i.H. Chen
In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.
{"title":"Testable VLSI circuit design of SIMD graphics engine","authors":"D. Pok, C.-i.H. Chen","doi":"10.1109/ASIC.1997.616981","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616981","url":null,"abstract":"In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616987
C. Yeh
Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.
{"title":"Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs","authors":"C. Yeh","doi":"10.1109/ASIC.1997.616987","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616987","url":null,"abstract":"Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114294274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616986
D. Hill, A. Domic
Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional "over the wall" methodology. Section 3 then proposes a "limited loops" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.
{"title":"On the relationship among accuracy, tolerance and compensation in the deep sub-micron era","authors":"D. Hill, A. Domic","doi":"10.1109/ASIC.1997.616986","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616986","url":null,"abstract":"Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional \"over the wall\" methodology. Section 3 then proposes a \"limited loops\" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616979
H. Werkmann, B. Hofflinger, B. Laquai
A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their effects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan test systems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.
{"title":"Boundary scan adaption for active substrate MCM-test","authors":"H. Werkmann, B. Hofflinger, B. Laquai","doi":"10.1109/ASIC.1997.616979","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616979","url":null,"abstract":"A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their effects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan test systems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616977
Sangyun Han, Sungho Kang
Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults.
{"title":"Efficient redundancy identification for test pattern generation","authors":"Sangyun Han, Sungho Kang","doi":"10.1109/ASIC.1997.616977","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616977","url":null,"abstract":"Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129210360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617028
T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl
A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.
{"title":"LVDS I/O buffers with a controlled reference circuit","authors":"T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl","doi":"10.1109/ASIC.1997.617028","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617028","url":null,"abstract":"A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126235572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617024
T. Gabara
A new set of terminals has been introduced to control the behavior of an MOS device. A magnetic field, formed when current flows through an on-chip coil, is applied to the inversion layer of an MOS device. The generated Lorentz force is applied to the carriers in the inversion layer to alter the characteristics of the MOS device. The magnetic field is applied parallel to the inversion layer and perpendicular to the carrier flow. Measurement results using this structure as a 1.8 GHz mixer are given. Measurements demonstrate that the interaction between the coil and the MOS device is primarily due to the Lorentz force. The capacitive coupling effect between the coil and the device plays a minor role.
{"title":"Lorentz force MOS transistor","authors":"T. Gabara","doi":"10.1109/ASIC.1997.617024","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617024","url":null,"abstract":"A new set of terminals has been introduced to control the behavior of an MOS device. A magnetic field, formed when current flows through an on-chip coil, is applied to the inversion layer of an MOS device. The generated Lorentz force is applied to the carriers in the inversion layer to alter the characteristics of the MOS device. The magnetic field is applied parallel to the inversion layer and perpendicular to the carrier flow. Measurement results using this structure as a 1.8 GHz mixer are given. Measurements demonstrate that the interaction between the coil and the MOS device is primarily due to the Lorentz force. The capacitive coupling effect between the coil and the device plays a minor role.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130199772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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