Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617000
W. Paik, In-Chul Hwang, Jae-Wan Kim, S. Kim
This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.
{"title":"Data dependent precharging dynamic chain architecture for low power end high speed adders","authors":"W. Paik, In-Chul Hwang, Jae-Wan Kim, S. Kim","doi":"10.1109/ASIC.1997.617000","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617000","url":null,"abstract":"This paper presents a power efficient dynamic chain adder based on a Data Dependent Precharging (DDP) algorithm. It suppresses spurious transitions due to the unconditional precharging of outputs during the 'precharge' mode. A 64-bit adder has been designed using the DDP dynamic chain architecture. Simulation results confirm that it operates at 270 MHz with 0.105 mW/MHz power consumption at 3.3 V supply. It reduces power by 36% without speed degradation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114628012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616969
A. Handkiewicz, P. Sniatala, M. Lukowiak
A new switched current (SI) memory cell is proposed in the paper. Analysis and simulations show very good properties of the cell. Layout of a sample and hold (SH) circuit composed of the memory cell is also presented. This SH circuit is a basic cell of bilinear integrators and delay lines, being components of one- and two-dimensional SI filters. The method and tools for automated design of such filters are briefly described.
{"title":"Low-voltage high-performance switched current memory cell","authors":"A. Handkiewicz, P. Sniatala, M. Lukowiak","doi":"10.1109/ASIC.1997.616969","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616969","url":null,"abstract":"A new switched current (SI) memory cell is proposed in the paper. Analysis and simulations show very good properties of the cell. Layout of a sample and hold (SH) circuit composed of the memory cell is also presented. This SH circuit is a basic cell of bilinear integrators and delay lines, being components of one- and two-dimensional SI filters. The method and tools for automated design of such filters are briefly described.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123649267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616972
Yan Zhang, W. Ye, R. Owens, M. J. Irwin
Interconnect structures play a more and more important role in low power computer design. Yet few investigations have been done in power analysis of interconnect structures. In this paper five designs of interconnect structures are implemented and a power analysis of interconnect structures that vary at the architecture level and gate level for different numbers of input ports is presented. The results based on these designs show that MUXes implemented with n-type pass transistors consume the least total power and set up power (power consumption in setting up the transmitting path). Crossbars consume the least transfer power (power consumption in transferring data). MUXes implemented with SPSD (Sympathetic Precharge Static Domino) gates have relatively lower delay especially for high fan-in interconnect structures. MUXes implemented with pass transistors have the lowest power-delay product for input ports numbers of 4, 8 and 16 while MUXes implemented with SPSD gates have the lowest power-delay product for interconnect structures which have 32 input ports.
{"title":"The power analysis of interconnect structures","authors":"Yan Zhang, W. Ye, R. Owens, M. J. Irwin","doi":"10.1109/ASIC.1997.616972","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616972","url":null,"abstract":"Interconnect structures play a more and more important role in low power computer design. Yet few investigations have been done in power analysis of interconnect structures. In this paper five designs of interconnect structures are implemented and a power analysis of interconnect structures that vary at the architecture level and gate level for different numbers of input ports is presented. The results based on these designs show that MUXes implemented with n-type pass transistors consume the least total power and set up power (power consumption in setting up the transmitting path). Crossbars consume the least transfer power (power consumption in transferring data). MUXes implemented with SPSD (Sympathetic Precharge Static Domino) gates have relatively lower delay especially for high fan-in interconnect structures. MUXes implemented with pass transistors have the lowest power-delay product for input ports numbers of 4, 8 and 16 while MUXes implemented with SPSD gates have the lowest power-delay product for interconnect structures which have 32 input ports.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115294812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616968
M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, T. Tsuchiya
An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-/spl mu/m at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz.
{"title":"An ultra-low-voltage MTCMOS/SIMOX gate array","authors":"M. Urano, T. Douseki, T. Hatano, H. Fukuda, M. Harada, T. Tsuchiya","doi":"10.1109/ASIC.1997.616968","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616968","url":null,"abstract":"An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-/spl mu/m at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131485787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617023
M. Ker, Tung-Yang Chen, Chung-Yu Wu
Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-/spl mu/m CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.
{"title":"Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique","authors":"M. Ker, Tung-Yang Chen, Chung-Yu Wu","doi":"10.1109/ASIC.1997.617023","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617023","url":null,"abstract":"Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-/spl mu/m CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124286242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617018
C. Tan, D. Bouldin, P. Dehkordi
Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.
{"title":"An intrinsic area-array pad router for ICs","authors":"C. Tan, D. Bouldin, P. Dehkordi","doi":"10.1109/ASIC.1997.617018","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617018","url":null,"abstract":"Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117077058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617006
A. Farrahi, M. Sarrafzadeh
A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70 to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.
{"title":"TDD: a technology dependent decomposition algorithm for LUT-based FPGAs","authors":"A. Farrahi, M. Sarrafzadeh","doi":"10.1109/ASIC.1997.617006","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617006","url":null,"abstract":"A major drawback of the previous algorithms that perform decomposition and covering for LUT-based FPGA technology mapping is the lack of a fast, and reasonably accurate evaluation scheme for the decomposition phase. In this paper, we will show how a fast covering algorithm can be used as an evaluation engine for the decomposition phase. We show that decomposition has a significant impact on the quality of the final mapping result. More specifically, we show that starting from the same circuit topology, a blind decomposition leads to mapping results that use an average of 70 to 150% more LUTs compared to the results obtained using a technology driven decomposition algorithm. A technology driven decomposition algorithm is developed based on the proposed idea. Experiments on a number of MCNC benchmark circuits show an average of 12% to 72% improvement on the number of LUTs compared to the previously reported results.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122553024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617022
M. Ker
A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12V (VSS-12V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.
{"title":"ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices","authors":"M. Ker","doi":"10.1109/ASIC.1997.617022","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617022","url":null,"abstract":"A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12V (VSS-12V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.617004
M. Hashimoto, H. Onoedera, K. Tamaru
It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate; this has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which drives the reordered gate. It is because the input capacitance depends on signal values of other inputs. We propose a reordering algorithm considering the power dissipation in the driving gate, the reordered gate and the gates driven by the reordered gate. Experimental results using 21 benchmark circuits show that our method reduces the power dissipation in all the circuits by 3.6% on average. There is a possibility that power dissipation is reduced by 17.2% maximum. In the case of delay and power optimization, our method reduces delay by 7.0% and power dissipation by 3.1% on average.
{"title":"Input reordering for power and delay optimization","authors":"M. Hashimoto, H. Onoedera, K. Tamaru","doi":"10.1109/ASIC.1997.617004","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617004","url":null,"abstract":"It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate; this has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which drives the reordered gate. It is because the input capacitance depends on signal values of other inputs. We propose a reordering algorithm considering the power dissipation in the driving gate, the reordered gate and the gates driven by the reordered gate. Experimental results using 21 benchmark circuits show that our method reduces the power dissipation in all the circuits by 3.6% on average. There is a possibility that power dissipation is reduced by 17.2% maximum. In the case of delay and power optimization, our method reduces delay by 7.0% and power dissipation by 3.1% on average.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-07DOI: 10.1109/ASIC.1997.616994
D. Pok, C.-i.H. Chen, C. Montgomery, B. Tsui, J. Schamus
A design for the monobit receiver application specific integrated circuit (ASIC) is described. The monobit receiver is a wide band (1 GHz) digital receiver designed for electronic warfare applications. The receiver can process two simultaneous signals and has the potential for fabrication on a single multi-chip module (MCM). The receiver consists of three major elements: (1) a nonlinear radio frequency (RF) front-end, (2) a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and (3) a patented "monobit" algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver's front end, ADC and algorithm experimental performance results will be presented. The receiver uses a two-bit ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: (1) perform a fast Fourier transform (FFT) and (2) determine the number of signals and report their frequencies. The ASIC design contains five stages: (1) the input, (2) the FFT, (3) the initial sort, (4) the squaring and addition, and (5) the final sort. The chip will process the ADC outputs in real time, reporting detected signal frequencies every 102.4 ns.
{"title":"ASIC design for monobit receiver","authors":"D. Pok, C.-i.H. Chen, C. Montgomery, B. Tsui, J. Schamus","doi":"10.1109/ASIC.1997.616994","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616994","url":null,"abstract":"A design for the monobit receiver application specific integrated circuit (ASIC) is described. The monobit receiver is a wide band (1 GHz) digital receiver designed for electronic warfare applications. The receiver can process two simultaneous signals and has the potential for fabrication on a single multi-chip module (MCM). The receiver consists of three major elements: (1) a nonlinear radio frequency (RF) front-end, (2) a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and (3) a patented \"monobit\" algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver's front end, ADC and algorithm experimental performance results will be presented. The receiver uses a two-bit ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: (1) perform a fast Fourier transform (FFT) and (2) determine the number of signals and report their frequencies. The ASIC design contains five stages: (1) the input, (2) the FFT, (3) the initial sort, (4) the squaring and addition, and (5) the final sort. The chip will process the ADC outputs in real time, reporting detected signal frequencies every 102.4 ns.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128108331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：