A triple interconnection process suitable for a CMOS 1.2- mu m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P/sub 2/O/sub 5/ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively.<>
{"title":"A triple metal interconnection process for CMOS technology","authors":"P. Cagnoni, F. Gualandris, L. Masini","doi":"10.1109/VMIC.1989.78075","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78075","url":null,"abstract":"A triple interconnection process suitable for a CMOS 1.2- mu m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P/sub 2/O/sub 5/ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115792731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Planarization of interlevel dielectrics by nonetchback spin-on glass (SOG) techniques requires the use of a dense, inorganic SOG with good dielectric characteristics. The authors have evaluated two recently developed phosphosilicate-type SOG materials, Accuglass P-114 and P-114A, for use in nonetchback processing. Both materials were successfully applied to the fabrication of 1.2- mu m CMOS ASIC circuits. Extensive reliability tests, including thermal stressing of via chains, DHTL, PPOT, and THBS were performed at the wafer level and on packaged parts fabricated with P-114. The very favorable results confirm the viability of the nonetchback process used.<>
通过非反蚀自旋玻璃(SOG)技术使介电层间介质平面化需要使用具有良好介电特性的致密无机SOG。作者评估了最近开发的两种磷酸硅酸盐型SOG材料，Accuglass P-114和P-114A，用于无腐蚀加工。这两种材料都成功地应用于1.2 μ m CMOS ASIC电路的制作。广泛的可靠性测试，包括通过链的热应力、DHTL、PPOT和THBS，在晶圆级和用P-114制造的封装部件上进行。非常好的结果证实了所采用的无回蚀工艺的可行性
{"title":"Fabrication of CMOS circuits using non-etchback SOG processing for dielectric planarization","authors":"H.W.M. Chung, S.K. Gupta, T. Baldwin","doi":"10.1109/VMIC.1989.77997","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77997","url":null,"abstract":"Planarization of interlevel dielectrics by nonetchback spin-on glass (SOG) techniques requires the use of a dense, inorganic SOG with good dielectric characteristics. The authors have evaluated two recently developed phosphosilicate-type SOG materials, Accuglass P-114 and P-114A, for use in nonetchback processing. Both materials were successfully applied to the fabrication of 1.2- mu m CMOS ASIC circuits. Extensive reliability tests, including thermal stressing of via chains, DHTL, PPOT, and THBS were performed at the wafer level and on packaged parts fabricated with P-114. The very favorable results confirm the viability of the nonetchback process used.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131081495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Fieber, E. Martin, H. Chew, G. Hills, N. Selamoglu, S. Lytle
A two-level metal process for a fourth-generation 1.0- mu m CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma-enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process.<>
开发了第四代1.0 μ m CMOS技术的两级金属工艺，该工艺无需引入复杂的加工程序，即可产生优越的铝台阶覆盖和高质量的介电体。该工艺具有成本效益，因为它包括传统材料和高通量操作，并且易于扩展到三层金属。该工艺结合了电介质I的高度平滑BPSG和电介质II的等离子体增强TEOS的电阻蚀刻平面化。还具有锥形铝I型型材和修改的接触窗口和通过蚀刻型材。缺陷密度和电迁移数据预测了该工艺的优良良率和可靠性。
{"title":"Superior metal step coverage and dielectric quality in a simple two-level metal 1.0 mu m CMOS technology","authors":"C. Fieber, E. Martin, H. Chew, G. Hills, N. Selamoglu, S. Lytle","doi":"10.1109/VMIC.1989.78006","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78006","url":null,"abstract":"A two-level metal process for a fourth-generation 1.0- mu m CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma-enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130262298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
TiN-encapsulized Cu interconnects were developed for ultra-large-scale integration (ULSI) by nitriding the Cu-10%Ti alloy. The 500-nm-thick Cu-Ti alloy layer was separated into an upper TiN layer and a lower Cu layer after nitriding at 800 degrees C. The interconnects had a higher oxidation resistance than Cu interconnects, and their resistivity was as low. The electromigration lifetime of the new interconnects was two orders of magnitude larger than that of pure Cu interconnects.<>
{"title":"TiN-encapsulized copper interconnects for ULSI applications","authors":"K. Hoshino, H. Yagi, H. Tsuchikawa","doi":"10.1109/VMIC.1989.78025","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78025","url":null,"abstract":"TiN-encapsulized Cu interconnects were developed for ultra-large-scale integration (ULSI) by nitriding the Cu-10%Ti alloy. The 500-nm-thick Cu-Ti alloy layer was separated into an upper TiN layer and a lower Cu layer after nitriding at 800 degrees C. The interconnects had a higher oxidation resistance than Cu interconnects, and their resistivity was as low. The electromigration lifetime of the new interconnects was two orders of magnitude larger than that of pure Cu interconnects.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129908772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The relation between EM (electromigration) characteristics and interlayer dielectric film structure is described. It was found that a well-planarized interlayer significantly increases EM resistance for underlying Al wirings. This EM improvement is attributed to reinforcement and crack suppression at interlayer sidewalls. A constant atom flux model is proposed that explains the mechanism for this phenomenon.<>
{"title":"Increase in EM resistance by planarizing dielectric film over Al wirings","authors":"A. Isobe, Y. Numazawa, M. Sakamoto","doi":"10.1109/VMIC.1989.78019","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78019","url":null,"abstract":"The relation between EM (electromigration) characteristics and interlayer dielectric film structure is described. It was found that a well-planarized interlayer significantly increases EM resistance for underlying Al wirings. This EM improvement is attributed to reinforcement and crack suppression at interlayer sidewalls. A constant atom flux model is proposed that explains the mechanism for this phenomenon.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133567356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Al-Si-Pd alloy with high stress-induced migration resistance was developed for VLSI interconnects. Pd was selected to depress grain boundary diffusion of Al alloys. The microstructures of Al matrices alloyed with Pd and Cu were investigated. The morphologies of precipitation in Al alloy conductors were examined after high-temperature heat treatment. The stress-induced migration resistances of the Al-Si-Pd and Al-Si-Cu were found to be influenced by the microstructures of Al matrices.<>
开发了一种抗应力迁移的Al-Si-Pd合金用于超大规模集成电路互连。选择Pd抑制Al合金的晶界扩散。研究了Pd和Cu合金Al基体的显微组织。研究了高温热处理后铝合金导体中析出物的形貌。Al- si - pd和Al- si - cu的应力诱导迁移性能受Al基体微观结构的影响。
{"title":"Stress migration resistance of Al-Si-Pd alloy interconnects","authors":"Y. Koubuchi, J. Onuki, M. Suwa, S. Fukada","doi":"10.1109/VMIC.1989.78003","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78003","url":null,"abstract":"Al-Si-Pd alloy with high stress-induced migration resistance was developed for VLSI interconnects. Pd was selected to depress grain boundary diffusion of Al alloys. The microstructures of Al matrices alloyed with Pd and Cu were investigated. The morphologies of precipitation in Al alloy conductors were examined after high-temperature heat treatment. The stress-induced migration resistances of the Al-Si-Pd and Al-Si-Cu were found to be influenced by the microstructures of Al matrices.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Yamazaki, S. Shimizu, H. Sakamoto, K. Mitsuhashi, K. Ohtake, M. Koba
Low-resistance contact plug technology using selective CVD of W by the SiH/sub 4/ reduction of WF/sub 6/ with SF/sub 6/ pretreatment was developed. This technology solved problems such as encroachment, wormholes, Si consumption, and poor adhesion encountered in only the H/sub 2/-reduction system or only the SiH/sub 4/-reduction system without pretreatment. The contact resistance in this system is lower than that in conventional metallization with Al-Si/Si contacts. It is predicted that this technology will become important for improving the reliability of the interconnection for submicron VLSI.<>
{"title":"Selective CVD tungsten contact plug technology with plasma pre-treatment","authors":"O. Yamazaki, S. Shimizu, H. Sakamoto, K. Mitsuhashi, K. Ohtake, M. Koba","doi":"10.1109/VMIC.1989.78018","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78018","url":null,"abstract":"Low-resistance contact plug technology using selective CVD of W by the SiH/sub 4/ reduction of WF/sub 6/ with SF/sub 6/ pretreatment was developed. This technology solved problems such as encroachment, wormholes, Si consumption, and poor adhesion encountered in only the H/sub 2/-reduction system or only the SiH/sub 4/-reduction system without pretreatment. The contact resistance in this system is lower than that in conventional metallization with Al-Si/Si contacts. It is predicted that this technology will become important for improving the reliability of the interconnection for submicron VLSI.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128481327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cu film was evaluated as a candidate for future interconnection. As the device dimensions are scaled below 0.5 mu m, the RC time constant of interconnection becomes a major part of the total delay. By reducing the resistivity of interconnect, the operating speed can be increased by more than 20% without any change in design rule. An electroless deposition process is proposed to solve the Cu patterning difficulty. Patterns of 2.0- mu m pitch were achieved with this process. Copper contamination was addressed, and dielectric films such as silicon oxynitride and silicon nitride were shown to be effective in stopping Cu diffusion. The authors also investigated Cu corrosion. By coating a thin Ni film on Cu they reduced the corrosion from 0.2 mu m/h to less than 0.05 mu m/h at 100 degrees C in 1-mol/1 KCl solution.<>
{"title":"Copper as the future interconnection material","authors":"P. Pai, C. Ting","doi":"10.1109/VMIC.1989.78029","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78029","url":null,"abstract":"Cu film was evaluated as a candidate for future interconnection. As the device dimensions are scaled below 0.5 mu m, the RC time constant of interconnection becomes a major part of the total delay. By reducing the resistivity of interconnect, the operating speed can be increased by more than 20% without any change in design rule. An electroless deposition process is proposed to solve the Cu patterning difficulty. Patterns of 2.0- mu m pitch were achieved with this process. Copper contamination was addressed, and dielectric films such as silicon oxynitride and silicon nitride were shown to be effective in stopping Cu diffusion. The authors also investigated Cu corrosion. By coating a thin Ni film on Cu they reduced the corrosion from 0.2 mu m/h to less than 0.05 mu m/h at 100 degrees C in 1-mol/1 KCl solution.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114369684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Omega on p-type and 57 Omega on n-type diffusion layers for 0.6- mu m hole diameter and 0.8- mu m hole depth. Moreover, a shallow source/drain junction of 0.15- mu m depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time.<>
{"title":"Low contact resistance polysilicon plug for halfmicron CMOS technology","authors":"T. Hamajima, Y. Sugano","doi":"10.1109/VMIC.1989.78017","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78017","url":null,"abstract":"A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Omega on p-type and 57 Omega on n-type diffusion layers for 0.6- mu m hole diameter and 0.8- mu m hole depth. Moreover, a shallow source/drain junction of 0.15- mu m depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132190531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A report is presented on the results of a comparative series of experiments conducted on thin polyimide layers, of thicknesses in the range approximately 600 A to >1.5 mu m, containing intentionally introduced and controlled amounts of Na. The levels of Na ranged from undoped (<0.2 p.p.m.) to 200 p.p.m. in the starting stock. These films were characterized using I/V and C/V measurements on MIS structures fabricated on Si wafers. Although the very best PI films has resistivities of approximately 10/sup 16/ Omega -cm the authors feel that, for use for gate isolation, the Na/sup +/ contamination level in the polyimide dielectric would need to be less than 0.2 p.p.m. for stable device operation.<>
{"title":"Electrical properties of polyimides for interlevel isolation and active device gate isolation","authors":"A. Dubey, D. Lile","doi":"10.1109/VMIC.1989.77999","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77999","url":null,"abstract":"A report is presented on the results of a comparative series of experiments conducted on thin polyimide layers, of thicknesses in the range approximately 600 A to >1.5 mu m, containing intentionally introduced and controlled amounts of Na. The levels of Na ranged from undoped (<0.2 p.p.m.) to 200 p.p.m. in the starting stock. These films were characterized using I/V and C/V measurements on MIS structures fabricated on Si wafers. Although the very best PI films has resistivities of approximately 10/sup 16/ Omega -cm the authors feel that, for use for gate isolation, the Na/sup +/ contamination level in the polyimide dielectric would need to be less than 0.2 p.p.m. for stable device operation.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"128 13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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