Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553066
N. Gunther, E. Hamadeh, D. Niemann, M. Rahman
Random fluctuations in fabrication process outcomes such as Si-SiO2 interface surface roughness (SR) and gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. These fluctuations are intra-die and inherent even to ideal processes. As such, they represent fiudamental limitations to the die-level uniformity of the properties of otherwise identical devices. Modeling based on statistical characterization of fluctuations in the characteristics of small 3D devices is becoming increasingly important to understand the implications for product designers and process engineers. [1-5] Presently, TCAD numerical simulation is the only tool available for investigating the complex interaction of these issues. In this work, we employ a novel device modeling approach based on thennodynamics and on variational mathematical methods. [6] We obtain closed-form expressions for threshold voltage (Vth), and device capacitance (C) at Onset of Strong Inversion (OSI) for MOS devices in the deep sub-0.1 micron regime. In our model SR is assumed to affect only the gate area whereas LER affects only the gate perimeter of the device. Figure 1 shows the SEM of the fabricated line used in our analysis of SR and LER. [7-8] We take the roughness of this line to be representative and characterize it by Fourier transforming the digitized data. By choosing a pdf to represent the entire spectrm we can then identify the average frequency and the variance. Figure 2 shows the FFT of the digitized data (circles) from Fig. 1, together with the lognormal pdf (solid line) used to fit the data. We have looked in some detail at three possible candidate pdfs: exponential, gaussian, and lognormal. For a combination of reasons we prefer the lognormal. [9] Our variational model predicts that the random deviation of threshold voltage due to LER should increase as the square of the roughness amplitude. Figure 3 shows this variation for a MOSCAP of gate length 35 nm and a width of 50 nm. Our results are compared here with results from Kim et al. [10] In both cases the variation appears to be quadratic in roughness amplitude. Figure 4 shows our prediction of the random deviation of total capacitance of the device at OSI for both LER and SR against standard deviation of roughness wavenumber. Figure 5 shows the random deviation of Vt for LER and SR against average roughness wavenumber according to our model. These statistical characteristics are extremely difficult to capture using TCAD. In contrast, the novelty and strong advantage of our modeling approach is that it allows us to treat the situation with less difficulty by explicitly incorporating these statistical quantities. Oxide thickness is one of the key parameters that affect the variance in Vh. Figure 6 shows the effect of variation in the oxide thickness on the random deviation of Vh according to our model. The model predicts that the deviation is greater for LER than for SR. Interestin
{"title":"Interface and gate line edge roughness effects on intra die variance in mos device characteristics","authors":"N. Gunther, E. Hamadeh, D. Niemann, M. Rahman","doi":"10.1109/DRC.2005.1553066","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553066","url":null,"abstract":"Random fluctuations in fabrication process outcomes such as Si-SiO2 interface surface roughness (SR) and gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. These fluctuations are intra-die and inherent even to ideal processes. As such, they represent fiudamental limitations to the die-level uniformity of the properties of otherwise identical devices. Modeling based on statistical characterization of fluctuations in the characteristics of small 3D devices is becoming increasingly important to understand the implications for product designers and process engineers. [1-5] Presently, TCAD numerical simulation is the only tool available for investigating the complex interaction of these issues. In this work, we employ a novel device modeling approach based on thennodynamics and on variational mathematical methods. [6] We obtain closed-form expressions for threshold voltage (Vth), and device capacitance (C) at Onset of Strong Inversion (OSI) for MOS devices in the deep sub-0.1 micron regime. In our model SR is assumed to affect only the gate area whereas LER affects only the gate perimeter of the device. Figure 1 shows the SEM of the fabricated line used in our analysis of SR and LER. [7-8] We take the roughness of this line to be representative and characterize it by Fourier transforming the digitized data. By choosing a pdf to represent the entire spectrm we can then identify the average frequency and the variance. Figure 2 shows the FFT of the digitized data (circles) from Fig. 1, together with the lognormal pdf (solid line) used to fit the data. We have looked in some detail at three possible candidate pdfs: exponential, gaussian, and lognormal. For a combination of reasons we prefer the lognormal. [9] Our variational model predicts that the random deviation of threshold voltage due to LER should increase as the square of the roughness amplitude. Figure 3 shows this variation for a MOSCAP of gate length 35 nm and a width of 50 nm. Our results are compared here with results from Kim et al. [10] In both cases the variation appears to be quadratic in roughness amplitude. Figure 4 shows our prediction of the random deviation of total capacitance of the device at OSI for both LER and SR against standard deviation of roughness wavenumber. Figure 5 shows the random deviation of Vt for LER and SR against average roughness wavenumber according to our model. These statistical characteristics are extremely difficult to capture using TCAD. In contrast, the novelty and strong advantage of our modeling approach is that it allows us to treat the situation with less difficulty by explicitly incorporating these statistical quantities. Oxide thickness is one of the key parameters that affect the variance in Vh. Figure 6 shows the effect of variation in the oxide thickness on the random deviation of Vh according to our model. The model predicts that the deviation is greater for LER than for SR. Interestin","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121711244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553136
O. Wunnicke, S. Serafin, M. V. van Kouwen, A. Roest, E. Bakkers
{"title":"Integration of III-V nanowires in Si technology","authors":"O. Wunnicke, S. Serafin, M. V. van Kouwen, A. Roest, E. Bakkers","doi":"10.1109/DRC.2005.1553136","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553136","url":null,"abstract":"","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115534655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553093
M. Hamilton, J. Kanicki
We have studied the effects of bias temperature stress (BTS) on organic field-effect transistors (OFETs) in accumulation (negative stress bias) and depletion (positive stress bias) using both dc and ac stress biases. The device studied is an inverted, gate-planarized, co-planar thin-film transistor that has been previously described [1]. Indium tin oxide (ITO) was used for the source and drain contacts and benzocyclobutene (BCB) / amorphous silicon nitride was used for the gate-planarization / insulator. The organic semiconductor F8T2 (poly 9,9-dioctylfluorene-co-bithiophene) was deposited by spin-coating from xylenes solution. These devices exhibit typical p-type field-effect transistor behavior. Typical values of the linear regime field-effect mobility, threshold voltage, and subthreshold swing for these devices are: 5x10-3 cm2/Vs, -20 V, and 3.0 V/decade respectively. All measurements were performed in the dark and in air using an HP4156 connected to a Karl Suss PM-8 probe station with a temperature-controlled chuck. For the case of negative dc BTS over long time scales (>104sec), we have used both interrupted and noninterrupted stress methods measured over a range of temperatures (293K < T < 353K). The major observable effect is a shift of the threshold voltage to more negative values as the stress time accumulates, causing a decrease in the drain current at a specific applied gate bias. The observed dependence on stress temperature is analyzed in terms of the kinetics of the stress mechanism. This analysis is performed by unifying the threshold voltage shift curves through either the normalization of the accumulated stress time by a thermally activated time constant for the stress or by using the thermalization energy [2,3]. We note that the values of both the activation energy of the time constant and the thermalization energy are approximately 0.25eV. We propose that this energy corresponds to the peak of a density of trap states above the valence band/HOMO level of F8T2. The observed bias stress effects are reversible at room temperature in the dark. However, recovery of the device is accelerated at elevated temperatures and by illumination with strongly absorbed illumination, as has been observed by others [4], indicating charge trapping/de-trapping as the general stress/recovery mechanism. For the case of positive dc BTS, we observe an unexpected shift of the threshold voltage towards more negative values as well as a significant degradation of the subthreshold swing, while the field-effect mobility is left unchanged throughout the duration of the positive BTS. The effects of the positive BTS are also reversible and we have observed that the recovery of the threshold voltage lags the recovery of the subthreshold swing. This is a possible indication that there are at least two competing stress mechanisms occurring in this device for positive BTS. We propose that there is an additional threshold voltage shift due to the movement of charge
{"title":"Time and temperature dependence of the drain current of PF-based OFETs","authors":"M. Hamilton, J. Kanicki","doi":"10.1109/DRC.2005.1553093","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553093","url":null,"abstract":"We have studied the effects of bias temperature stress (BTS) on organic field-effect transistors (OFETs) in accumulation (negative stress bias) and depletion (positive stress bias) using both dc and ac stress biases. The device studied is an inverted, gate-planarized, co-planar thin-film transistor that has been previously described [1]. Indium tin oxide (ITO) was used for the source and drain contacts and benzocyclobutene (BCB) / amorphous silicon nitride was used for the gate-planarization / insulator. The organic semiconductor F8T2 (poly 9,9-dioctylfluorene-co-bithiophene) was deposited by spin-coating from xylenes solution. These devices exhibit typical p-type field-effect transistor behavior. Typical values of the linear regime field-effect mobility, threshold voltage, and subthreshold swing for these devices are: 5x10-3 cm2/Vs, -20 V, and 3.0 V/decade respectively. All measurements were performed in the dark and in air using an HP4156 connected to a Karl Suss PM-8 probe station with a temperature-controlled chuck. For the case of negative dc BTS over long time scales (>104sec), we have used both interrupted and noninterrupted stress methods measured over a range of temperatures (293K < T < 353K). The major observable effect is a shift of the threshold voltage to more negative values as the stress time accumulates, causing a decrease in the drain current at a specific applied gate bias. The observed dependence on stress temperature is analyzed in terms of the kinetics of the stress mechanism. This analysis is performed by unifying the threshold voltage shift curves through either the normalization of the accumulated stress time by a thermally activated time constant for the stress or by using the thermalization energy [2,3]. We note that the values of both the activation energy of the time constant and the thermalization energy are approximately 0.25eV. We propose that this energy corresponds to the peak of a density of trap states above the valence band/HOMO level of F8T2. The observed bias stress effects are reversible at room temperature in the dark. However, recovery of the device is accelerated at elevated temperatures and by illumination with strongly absorbed illumination, as has been observed by others [4], indicating charge trapping/de-trapping as the general stress/recovery mechanism. For the case of positive dc BTS, we observe an unexpected shift of the threshold voltage towards more negative values as well as a significant degradation of the subthreshold swing, while the field-effect mobility is left unchanged throughout the duration of the positive BTS. The effects of the positive BTS are also reversible and we have observed that the recovery of the threshold voltage lags the recovery of the subthreshold swing. This is a possible indication that there are at least two competing stress mechanisms occurring in this device for positive BTS. We propose that there is an additional threshold voltage shift due to the movement of charge","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553070
S. Krishinan, D. Vasileska, M. Fischetti
Abstract. Electron transport in Si inversion layers has been the primary subject ofresearch for many years now [1], but hole transport has been relegated to the background mainly due to the highly complicated valence band-structure in Si. Hole transport is affected by the warping and anisotropy of the valence bands and the band-structure cannot be approximated with an effective mass picture or with an analytical band model. The advent of alternate device structures [2,3&4] aimed at boosting the speed and density ofVLSI circuits however, seems to have revived interest.
{"title":"Simulation of hole transport in p-channel Si MOSFETs","authors":"S. Krishinan, D. Vasileska, M. Fischetti","doi":"10.1109/DRC.2005.1553070","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553070","url":null,"abstract":"Abstract. Electron transport in Si inversion layers has been the primary subject ofresearch for many years now [1], but hole transport has been relegated to the background mainly due to the highly complicated valence band-structure in Si. Hole transport is affected by the warping and anisotropy of the valence bands and the band-structure cannot be approximated with an effective mass picture or with an analytical band model. The advent of alternate device structures [2,3&4] aimed at boosting the speed and density ofVLSI circuits however, seems to have revived interest.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553071
A. Al-Ahmadi, S. Kaya
The Si nanoelectronic engineering have recently reached a level of capability, which make 3D processing and strain engineering on silicon-on-insulator (SOI) substrates not only possible [1,2], but also a necessity in order to surmount practical limitations of conventional planar CMOS [3]. Thus, device designers are presented with a multitude of options in exploring new designs, as evident in the proliferation of alternative architectures, including multi-gated, strained Si/SiGe channel, Schottky and Tunneling MOSFETs. While these structures have unique features superior to conventional bulk devices, nonetheless, they still retain the redundancy inherent to CMOS operation, namely building two devices even though only one operates at a given stable output. In this paper we demonstrate and design, through the use of 1/2/3D device simulations, a novel symmetrically operating CMOS device pair with a single gate structure having a unique device layout and ultra-thin strained channels [4]. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and pMOSFETs perpendicular to one another under a single gate, integrating them vertically (see Figs.1&2). Thus COSMOS can eliminate the aforementioned redundancy in CMOS and may result in dramatic savings (>50%) not only in active device area of a conventional digital CMOS layout, but also in R-C device parasitics associated with building and wiring two sets of devices for a single Boolean output function. We argue that the COSMOS structure is a natural candidate for very dense, low-power circuitry required in sub-5Onm scale. The proposed COSMOS architecture relies for operation on a conventional silicon electron channel grown atop a strained-SiGe channel for holes, as shown in Fig.2. To facilitate threshold tuning, reduce parallel conduction and eliminate need for doping, Ge concentration in the strained channel must be high. In accordance, the gate material may be a mid-gap metal, poly-SiGe alloy or polySi, depending on the choice of Ge concentration or background doping. The channel layers must be grown [5] or bonded [6] on a SOI substrate to allow isolation of both MOSFETs, while also keeping with the general scaling trends associated with low-leakage and low-parasitic SOI substrates. For a sample layer structure with a 4nm strained-Si03Ge0.7 hole channel and 3nm Si electron channel under a mid-gap metal gate, ID self-consistent Poisson-Schrodinger simulations (see Fig.3) indicate that symmetric population of both channels is possible with a threshold of IVTI=0.4±0.2 V. We also find that there is no significant parallel conduction in this layer structure, removing concerns for isolation in the stacked channels. Even for this non-optimum layer example, the carriers in both channels of COSMOS layers are well confined and have quite similar distributions. The use of large Ge concentration in the buried strained channel should improve hole mobility considerably over that of electr
{"title":"Device scaling in COSMOS architecture","authors":"A. Al-Ahmadi, S. Kaya","doi":"10.1109/DRC.2005.1553071","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553071","url":null,"abstract":"The Si nanoelectronic engineering have recently reached a level of capability, which make 3D processing and strain engineering on silicon-on-insulator (SOI) substrates not only possible [1,2], but also a necessity in order to surmount practical limitations of conventional planar CMOS [3]. Thus, device designers are presented with a multitude of options in exploring new designs, as evident in the proliferation of alternative architectures, including multi-gated, strained Si/SiGe channel, Schottky and Tunneling MOSFETs. While these structures have unique features superior to conventional bulk devices, nonetheless, they still retain the redundancy inherent to CMOS operation, namely building two devices even though only one operates at a given stable output. In this paper we demonstrate and design, through the use of 1/2/3D device simulations, a novel symmetrically operating CMOS device pair with a single gate structure having a unique device layout and ultra-thin strained channels [4]. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and pMOSFETs perpendicular to one another under a single gate, integrating them vertically (see Figs.1&2). Thus COSMOS can eliminate the aforementioned redundancy in CMOS and may result in dramatic savings (>50%) not only in active device area of a conventional digital CMOS layout, but also in R-C device parasitics associated with building and wiring two sets of devices for a single Boolean output function. We argue that the COSMOS structure is a natural candidate for very dense, low-power circuitry required in sub-5Onm scale. The proposed COSMOS architecture relies for operation on a conventional silicon electron channel grown atop a strained-SiGe channel for holes, as shown in Fig.2. To facilitate threshold tuning, reduce parallel conduction and eliminate need for doping, Ge concentration in the strained channel must be high. In accordance, the gate material may be a mid-gap metal, poly-SiGe alloy or polySi, depending on the choice of Ge concentration or background doping. The channel layers must be grown [5] or bonded [6] on a SOI substrate to allow isolation of both MOSFETs, while also keeping with the general scaling trends associated with low-leakage and low-parasitic SOI substrates. For a sample layer structure with a 4nm strained-Si03Ge0.7 hole channel and 3nm Si electron channel under a mid-gap metal gate, ID self-consistent Poisson-Schrodinger simulations (see Fig.3) indicate that symmetric population of both channels is possible with a threshold of IVTI=0.4±0.2 V. We also find that there is no significant parallel conduction in this layer structure, removing concerns for isolation in the stacked channels. Even for this non-optimum layer example, the carriers in both channels of COSMOS layers are well confined and have quite similar distributions. The use of large Ge concentration in the buried strained channel should improve hole mobility considerably over that of electr","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130314939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553149
H. Moyer, T. Hsu, R. Bowen, Y. Boegeman, P. Deelman, S. Thomas, A. Hunter, J. Schulman
Current millimeter wave imaging cameras based on square-law detector diodes require an RF low noise amplifier (LNA) to boost the signal above the detector noise floor. Sb-heterostructure diodes, fabricated from epitaxial layers of InAs and AlGaSb, have shown very high zero-biased sensitivities at W-band, but the devices studied were not optimized for low noise [1-3]. Zero-biased devices have an important a priori advantage over the commonly used biased Schottky diode detector because removing the bias eliminates 1/fnoise and provides the potential for ultra-low noise performance without the need for pre-amplification. The remaining noise is predominantly Johnson noise, Sv =4kTRj (per Hz), where RJ is the junction resistance. A key figure of merit is the Noise Equivalent Power (NEP), a measure of the minimum detectable power, given by SV"I2/S, where S is the sensitivity in volts per watt. To lower the noise, RJ can be decreased from the -1OKQ value of the previous diodes. The basic diode active region contains highly doped n-type InAs, an AlSb barrier, an un-doped AlGaSb layer, followed by a highly doped GaSb (p) to InAs (n) tunnel junction [1-3]. The key layer being altered here is the AlSb layer. It controls the overall current flow through the device and thus the junction resistance. We have thinned it from its previous values of 32-39A to 1 5-20A to lower the junction resistance. The I-V curve of a typical 2x2 [m2 diode with a 15iA AlSb barrier is shown in Fig. 1. A polynomial fit to the important figure of merit y, the I-V curvature divided by the slope [4], is found to be 23V'. This is somewhat less than the ~40V-1 curvature found with the thicker AlSb barriers. The diode with a 20A AlSb produced an intermediate curvature of 27V-', illustrating the expected trend of approaching ohmic behavior as the barrier is thinned. Sparameters measured to 40 GHz are used to extract a standard equivalent circuit model. Figure 2 shows a table ofthe extracted results for the diodes with 15A and 20A barrier thicknesses. The values differ by about 10-15% across a wafer due to variations in epitaxy, processing tolerances, and measurement uncertainties. These values, along with the polynomial, are utilized in a user defined non-linear model in Microwave Offi1ce [5] with the results being displayed in Fig. 3. This result is similar to the measured data in Fig. 4. for which the diode was placed in a housing with 5 mil alumina circuits and tuned for optimum sensitivity. In both cases, the maximum sensitivity is close to 2500 V/W. An open X/4 line at 36 GHz was added to reflect the RF signal back into the diode to offset the effects from capacitor loss on the DC output side. As the line acts as a narrowband bandstop filter, the bandwidth of the circuit was reduced. Associated measured low frequency noise of the diode is shown in Fig. 5. The best fit is to a Johnson noise power equivalent to that of a 630Q resistor, quite close to the junction resistance plus -38Q o
{"title":"Optimization of sb-heterostructure diode for low noise detection","authors":"H. Moyer, T. Hsu, R. Bowen, Y. Boegeman, P. Deelman, S. Thomas, A. Hunter, J. Schulman","doi":"10.1109/DRC.2005.1553149","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553149","url":null,"abstract":"Current millimeter wave imaging cameras based on square-law detector diodes require an RF low noise amplifier (LNA) to boost the signal above the detector noise floor. Sb-heterostructure diodes, fabricated from epitaxial layers of InAs and AlGaSb, have shown very high zero-biased sensitivities at W-band, but the devices studied were not optimized for low noise [1-3]. Zero-biased devices have an important a priori advantage over the commonly used biased Schottky diode detector because removing the bias eliminates 1/fnoise and provides the potential for ultra-low noise performance without the need for pre-amplification. The remaining noise is predominantly Johnson noise, Sv =4kTRj (per Hz), where RJ is the junction resistance. A key figure of merit is the Noise Equivalent Power (NEP), a measure of the minimum detectable power, given by SV\"I2/S, where S is the sensitivity in volts per watt. To lower the noise, RJ can be decreased from the -1OKQ value of the previous diodes. The basic diode active region contains highly doped n-type InAs, an AlSb barrier, an un-doped AlGaSb layer, followed by a highly doped GaSb (p) to InAs (n) tunnel junction [1-3]. The key layer being altered here is the AlSb layer. It controls the overall current flow through the device and thus the junction resistance. We have thinned it from its previous values of 32-39A to 1 5-20A to lower the junction resistance. The I-V curve of a typical 2x2 [m2 diode with a 15iA AlSb barrier is shown in Fig. 1. A polynomial fit to the important figure of merit y, the I-V curvature divided by the slope [4], is found to be 23V'. This is somewhat less than the ~40V-1 curvature found with the thicker AlSb barriers. The diode with a 20A AlSb produced an intermediate curvature of 27V-', illustrating the expected trend of approaching ohmic behavior as the barrier is thinned. Sparameters measured to 40 GHz are used to extract a standard equivalent circuit model. Figure 2 shows a table ofthe extracted results for the diodes with 15A and 20A barrier thicknesses. The values differ by about 10-15% across a wafer due to variations in epitaxy, processing tolerances, and measurement uncertainties. These values, along with the polynomial, are utilized in a user defined non-linear model in Microwave Offi1ce [5] with the results being displayed in Fig. 3. This result is similar to the measured data in Fig. 4. for which the diode was placed in a housing with 5 mil alumina circuits and tuned for optimum sensitivity. In both cases, the maximum sensitivity is close to 2500 V/W. An open X/4 line at 36 GHz was added to reflect the RF signal back into the diode to offset the effects from capacitor loss on the DC output side. As the line acts as a narrowband bandstop filter, the bandwidth of the circuit was reduced. Associated measured low frequency noise of the diode is shown in Fig. 5. The best fit is to a Johnson noise power equivalent to that of a 630Q resistor, quite close to the junction resistance plus -38Q o","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121195353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553142
V. Klimov, S. Ivanov, J. Nanda, I. Bezel, M. Achermann, L. Balet
Because of size-controlled emission color, good photostability, and chemical flexibility, colloidal semiconductor nanocrystals (NCs) are promising building blocks for new types of colorselectable optical gain media [1]. One factor limiting optical gain performance ofNCs is highly efficient multiexciton Auger recombination that leads to short picosecond optical gain life times [2]. Recent attempts to suppress Auger recombination utilized NC shape control [3, 4]. Using elongated CdSe NCs (quantum rods) it was possible to extend optical gain life times by almost an order of magnitude, which further allowed a many-fold reduction of the excitation threshold for amplified spontaneous emission (ASE) [4]. For both spherical and elongated particles, Auger recombination times rapidly shorten as the particle dimensions are decreased. Therefore, it becomes progressively more difficult to achieve the ASE regime for shorter wavelengths that require the use of NCs of small sizes. In particular, while demonstrating strong optical-gain performance in the red-yellow spectral ranges, CdSe NCs do not show efficient ASE in the range of green and particularly blue colors that correspond to extremely small NC sizes (< 3nm).
{"title":"Nanocrystal lasing in the single-exciton regime using engineered exciton-exciton interactions","authors":"V. Klimov, S. Ivanov, J. Nanda, I. Bezel, M. Achermann, L. Balet","doi":"10.1109/DRC.2005.1553142","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553142","url":null,"abstract":"Because of size-controlled emission color, good photostability, and chemical flexibility, colloidal semiconductor nanocrystals (NCs) are promising building blocks for new types of colorselectable optical gain media [1]. One factor limiting optical gain performance ofNCs is highly efficient multiexciton Auger recombination that leads to short picosecond optical gain life times [2]. Recent attempts to suppress Auger recombination utilized NC shape control [3, 4]. Using elongated CdSe NCs (quantum rods) it was possible to extend optical gain life times by almost an order of magnitude, which further allowed a many-fold reduction of the excitation threshold for amplified spontaneous emission (ASE) [4]. For both spherical and elongated particles, Auger recombination times rapidly shorten as the particle dimensions are decreased. Therefore, it becomes progressively more difficult to achieve the ASE regime for shorter wavelengths that require the use of NCs of small sizes. In particular, while demonstrating strong optical-gain performance in the red-yellow spectral ranges, CdSe NCs do not show efficient ASE in the range of green and particularly blue colors that correspond to extremely small NC sizes (< 3nm).","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125729987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553108
K. Joshin, T. Kikkawa
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Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553076
J. Sim, S.C. Song, R. Choi, C. Young, G. Bersuker, S. H. Bae, D. Kwong, B. Lee
Introduction Hafnium based high-k dielectrics and metal gate electrodes have been aggressively investigated in order to ensure continued scaling ofCMOS technology. Well known limitations of high-k dielectric devices such as low mobility, charge trapping, interfacial oxide quality have been improved significantly and will no longer be a show stopper for the implementation in 45nm node [1-4]. However, reliability characteristics of high-k dielectrics have not been fully understood yet. Since the transient charging effect, which is generally not observed in SiO2, complicates evaluation of the properties of high-k gate stacks [5-10]. Hot carrier effects of the high-k gate dielectrics should be investigated considering the effect from cold carriers [1114]. Even though the contribution of cold carrier are not separable from that of hot carrier during channel hot carrier stress, the reversibility of cold carrier effects can be carefully examined to differentiate the effect of cold carrier from hot carrier induced damage on the device, which is assumed to be permanent. In this paper, we investigate the effect of cold carrier and hot carrier on the HfO2 and HfSiO NMOSFETs transistor devices.
{"title":"Cold and hot carrier effects on HfO/sub 2/ and HfSiO NMOSFETS with tin gate electrode","authors":"J. Sim, S.C. Song, R. Choi, C. Young, G. Bersuker, S. H. Bae, D. Kwong, B. Lee","doi":"10.1109/DRC.2005.1553076","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553076","url":null,"abstract":"Introduction Hafnium based high-k dielectrics and metal gate electrodes have been aggressively investigated in order to ensure continued scaling ofCMOS technology. Well known limitations of high-k dielectric devices such as low mobility, charge trapping, interfacial oxide quality have been improved significantly and will no longer be a show stopper for the implementation in 45nm node [1-4]. However, reliability characteristics of high-k dielectrics have not been fully understood yet. Since the transient charging effect, which is generally not observed in SiO2, complicates evaluation of the properties of high-k gate stacks [5-10]. Hot carrier effects of the high-k gate dielectrics should be investigated considering the effect from cold carriers [1114]. Even though the contribution of cold carrier are not separable from that of hot carrier during channel hot carrier stress, the reversibility of cold carrier effects can be carefully examined to differentiate the effect of cold carrier from hot carrier induced damage on the device, which is assumed to be permanent. In this paper, we investigate the effect of cold carrier and hot carrier on the HfO2 and HfSiO NMOSFETs transistor devices.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133192103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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