Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553156
D. Feezell, D. Buell, L. Johansson, L. Coldren
In this paper, the authors designed a 1.3mum VCSEL with Sb-based DBR technology and demonstrated its first CW operation. It has achieved record-high CW differential efficiencies. High speed modulation was also demonstrated for the first time with this technology. Coupled with previous results at 1.55mum, these results clearly demonstrate this platform's ability to generate high-performance monolithic VCSELs spanning the entire 1.3-1.6mum wavelength window
在本文中，作者设计了一种基于Sb-based DBR技术的1.3 mm VCSEL，并演示了其首次连续波操作。它实现了创纪录的连续波差效率。该技术还首次演示了高速调制。再加上之前在1.55 μ m波段的结果，这些结果清楚地证明了该平台能够在整个1.3-1.6 μ m波长窗口内生成高性能单片vcsel
{"title":"High differential efficiency (>60%) continuous-wave operation of 1.3gjm inp-based VCSELs with Sb-based DBRs","authors":"D. Feezell, D. Buell, L. Johansson, L. Coldren","doi":"10.1109/DRC.2005.1553156","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553156","url":null,"abstract":"In this paper, the authors designed a 1.3mum VCSEL with Sb-based DBR technology and demonstrated its first CW operation. It has achieved record-high CW differential efficiencies. High speed modulation was also demonstrated for the first time with this technology. Coupled with previous results at 1.55mum, these results clearly demonstrate this platform's ability to generate high-performance monolithic VCSELs spanning the entire 1.3-1.6mum wavelength window","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"45 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553121
C. Ni Chleirigh, O. Olubuyide, J. Hoyt
In this work, for the first time, a comprehensive study of mobility, sub-threshold slope and off-state leakage current in high Ge content dual-channel strained Si/strained Si1-yGe on relaxed Si1-xGex p-MOSFETs is presented. Hole mobility enhancements of 3X are observed at high inversion charge densities (N inv=1013 cm-2) for the strained Si0.3Ge0.7 on relaxed Si0.7Ge0.3 (70/30) structure with 2 nm-thick cap, and 3 nm-thick gate oxide. A wide range of Ge fractions and Si cap thicknesses are studied. The mobility enhancement is dominated by the Ge fraction in the strained Si 1-yGey layer, while the level of strain is a second order effect. The off-state drain leakage is studied in detail. At low drain-to-gate bias (VDG), off-state leakage is attributed to a trap assisted tunneling (TAT) mechanism at the Si surface, and is sensitive to Si cap layer thickness. At high VDG the leakage increases with the Ge fraction in the strained Si1-yGey and strain in the Si cap layer, consistent with band-to-band tunneling (BTBT). The data illustrates trade-offs critical to optimizing the structures with respect to mobility, charge control, and leakage
{"title":"Mobility and sub-threshold characteristics in high-mobility dual-channel strained Si/strainef SiGe p-MOSFETs","authors":"C. Ni Chleirigh, O. Olubuyide, J. Hoyt","doi":"10.1109/DRC.2005.1553121","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553121","url":null,"abstract":"In this work, for the first time, a comprehensive study of mobility, sub-threshold slope and off-state leakage current in high Ge content dual-channel strained Si/strained Si<sub>1-y</sub>Ge on relaxed Si<sub>1-x</sub>Ge<sub>x</sub> p-MOSFETs is presented. Hole mobility enhancements of 3X are observed at high inversion charge densities (N <sub>inv</sub>=10<sup>13</sup> cm<sup>-2</sup>) for the strained Si<sub>0.3</sub>Ge<sub>0.7</sub> on relaxed Si<sub>0.7</sub>Ge<sub>0.3 </sub> (70/30) structure with 2 nm-thick cap, and 3 nm-thick gate oxide. A wide range of Ge fractions and Si cap thicknesses are studied. The mobility enhancement is dominated by the Ge fraction in the strained Si <sub>1-y</sub>Ge<sub>y</sub> layer, while the level of strain is a second order effect. The off-state drain leakage is studied in detail. At low drain-to-gate bias (V<sub>DG</sub>), off-state leakage is attributed to a trap assisted tunneling (TAT) mechanism at the Si surface, and is sensitive to Si cap layer thickness. At high V<sub>DG </sub>the leakage increases with the Ge fraction in the strained Si<sub>1-y</sub>Ge<sub>y</sub> and strain in the Si cap layer, consistent with band-to-band tunneling (BTBT). The data illustrates trade-offs critical to optimizing the structures with respect to mobility, charge control, and leakage","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114486797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553081
Y. Lin, A. Appenzeller, Z. Chen, Z. Chen, H. Cheng, P. Avouris
Carbon nanotubes (CNTs) are promising candidates for post-Si nanoelectronics (Avouris et al., 2003). They are particularly attractive for high-speed applications due to their ballistic properties and high Fermi velocity (~106 m/s) Liang et al., 2001. The small-signal switching speed of a transistor is determined by the intrinsic delay time tau = 2piCG/gm, where C G is the gate capacitance and gm=dId/dV gs is the transconductance. For carbon nanotube field-effect transistors (CNFETs), the highest gm reported so far is ~ 27 muS by Javey et al. (Javey et al., 2004) using a dielectric film of 8-nm HfO2 (K=15). In their CNFET, the gate capacitance per unit length is estimated to be CG/L=1.8times10-16 F/mum, resulting in a gate delay per unit length of dL=42 ps/mum. Here we present a high-performance CNFET with a delay time per unit length of dL=22 ps/mum, the smallest value reported for CNFETs to date. In order to further minimize the parasitic capacitances and lower the intrinsic gate capacitance, we utilize a dual-gate design and fabricate a 40-nm gate CNFET possessing excellent subthreshold and output characteristics, which is the shortest gate length for a well-tempered CNFET demonstrated so far
{"title":"Demonstration of a high performance 40-nm-gate carbon nanotube field-effect transistor","authors":"Y. Lin, A. Appenzeller, Z. Chen, Z. Chen, H. Cheng, P. Avouris","doi":"10.1109/DRC.2005.1553081","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553081","url":null,"abstract":"Carbon nanotubes (CNTs) are promising candidates for post-Si nanoelectronics (Avouris et al., 2003). They are particularly attractive for high-speed applications due to their ballistic properties and high Fermi velocity (~106 m/s) Liang et al., 2001. The small-signal switching speed of a transistor is determined by the intrinsic delay time tau = 2piCG/gm, where C G is the gate capacitance and gm=dId/dV gs is the transconductance. For carbon nanotube field-effect transistors (CNFETs), the highest gm reported so far is ~ 27 muS by Javey et al. (Javey et al., 2004) using a dielectric film of 8-nm HfO2 (K=15). In their CNFET, the gate capacitance per unit length is estimated to be CG/L=1.8times10-16 F/mum, resulting in a gate delay per unit length of dL=42 ps/mum. Here we present a high-performance CNFET with a delay time per unit length of dL=22 ps/mum, the smallest value reported for CNFETs to date. In order to further minimize the parasitic capacitances and lower the intrinsic gate capacitance, we utilize a dual-gate design and fabricate a 40-nm gate CNFET possessing excellent subthreshold and output characteristics, which is the shortest gate length for a well-tempered CNFET demonstrated so far","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130876587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553067
M.S. Rahman, H. Park, M. Chang, R. Choi, B. Lee, J.C. Lee, H. Hwang
Hafnium and hafnium based oxide materials seems most promising gate material for aggressively scaled device. However, the mobility degradation of Hf-base gate dielectric is one of the most difficult problems. Recently, we have reported a significant improvement in interface characteristics, device drive current and maximum transconductance (Gm) by employing high pressure (HP) deuterium annealing at relatively low temperature. However reliability characteristics are not much improved compared with forming gas annealed sample. This might be due to the presence of excess deuterium in the oxide. In this presentation, we report the effect of two step anneal process and its effect on reliability and performance
{"title":"Improved reliability characteristics of ultrathin high-k MOSFET with TiN gate by employing two step post deposition annealing process","authors":"M.S. Rahman, H. Park, M. Chang, R. Choi, B. Lee, J.C. Lee, H. Hwang","doi":"10.1109/DRC.2005.1553067","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553067","url":null,"abstract":"Hafnium and hafnium based oxide materials seems most promising gate material for aggressively scaled device. However, the mobility degradation of Hf-base gate dielectric is one of the most difficult problems. Recently, we have reported a significant improvement in interface characteristics, device drive current and maximum transconductance (Gm) by employing high pressure (HP) deuterium annealing at relatively low temperature. However reliability characteristics are not much improved compared with forming gas annealed sample. This might be due to the presence of excess deuterium in the oxide. In this presentation, we report the effect of two step anneal process and its effect on reliability and performance","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124986774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553164
Y.M. Huang, M. Uppalapati, W. Hancock, T. Jackson
We have investigated hierarchical capped channels that provide 3D microtubule confinement (Huang et al., 2004). We describe here a simplified polymethymethacrylate bonded (PMMA) 3D hierarchical channel process. This process provides shallow motor microchannels (4-6 mum wide and 1.5 mum deep) and deeper structures (~250 mum deep) for fluid input and output and allow simple electrode integration
我们已经研究了提供三维微管约束的分层封顶通道(Huang et al.， 2004)。我们在这里描述了一个简化的聚甲基丙烯酸甲酯键合(PMMA)三维分层通道工艺。该过程提供浅电机微通道(4-6妈宽，1.5妈深)和更深的结构(~250妈深)，用于流体输入和输出，并允许简单的电极集成
{"title":"Nano-bio-molecular motors in microfabricated channels","authors":"Y.M. Huang, M. Uppalapati, W. Hancock, T. Jackson","doi":"10.1109/DRC.2005.1553164","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553164","url":null,"abstract":"We have investigated hierarchical capped channels that provide 3D microtubule confinement (Huang et al., 2004). We describe here a simplified polymethymethacrylate bonded (PMMA) 3D hierarchical channel process. This process provides shallow motor microchannels (4-6 mum wide and 1.5 mum deep) and deeper structures (~250 mum deep) for fluid input and output and allow simple electrode integration","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"34 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123817507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553158
T. Kondo, J. Hayafuji, H. Munekata
In this paper, the authors propose a spin-photodiode (spin-PD) that can convert directly the magnitude of circular polarization of incident light into an electric analog signal. This novel device makes it possible to simplify the optical system based on circularly polarized light, such as the optical-chirality detection for organic compounds and stress detection in the solid objects. We show experimentally the device characteristics of III-V-based spin-PD, and discuss that the spin-PD operates as we expected from the model calculations
{"title":"Design and fabrication of the spin-photodiode based on non-magnetic III-V semiconductor heterostructures","authors":"T. Kondo, J. Hayafuji, H. Munekata","doi":"10.1109/DRC.2005.1553158","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553158","url":null,"abstract":"In this paper, the authors propose a spin-photodiode (spin-PD) that can convert directly the magnitude of circular polarization of incident light into an electric analog signal. This novel device makes it possible to simplify the optical system based on circularly polarized light, such as the optical-chirality detection for organic compounds and stress detection in the solid objects. We show experimentally the device characteristics of III-V-based spin-PD, and discuss that the spin-PD operates as we expected from the model calculations","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125487527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553073
Chungho Lee, T. Hou, E. Kan
Nonvolatile memories with heterogeneous-stack floating gate of metal nanocrystals and silicon nitride (Si3N4) have been fabricated and characterized. The heterogeneous gate stacks showed superior characteristics in retention and low voltage write/erase over single metal nanocrystal memories and/or nitride memories (i.e., MONOS or SONOS). The metal nanocrystals in the stack made low voltage operation possible by the direct tunneling programming, while the nitride layer as an additional charge storage trap layer enabled longer retention time. By making the double stack of Si3N4-Au-Si3N4-Au, we could enhance the memory characteristics even further
{"title":"Metal nanocrystal/nitride heterogeneous-stack floating gate memory","authors":"Chungho Lee, T. Hou, E. Kan","doi":"10.1109/DRC.2005.1553073","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553073","url":null,"abstract":"Nonvolatile memories with heterogeneous-stack floating gate of metal nanocrystals and silicon nitride (Si3N4) have been fabricated and characterized. The heterogeneous gate stacks showed superior characteristics in retention and low voltage write/erase over single metal nanocrystal memories and/or nitride memories (i.e., MONOS or SONOS). The metal nanocrystals in the stack made low voltage operation possible by the direct tunneling programming, while the nitride layer as an additional charge storage trap layer enabled longer retention time. By making the double stack of Si3N4-Au-Si3N4-Au, we could enhance the memory characteristics even further","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"136 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117347109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553037
S. Chakravarty, J. Topolancik, S. Chakrabarti, P. Bhattacharya
The authors present here the characteristics of an electrically injected single defect (or larger) photonic crystal microcavity device with quantum dot active region that exhibits single-mode behaviour in the output spectra. The devices are mechanically robust and the design minimizes thermal instabilities
{"title":"Electrically injected quantum dot bottom-emitting photonic crystal single mode microcavity light source","authors":"S. Chakravarty, J. Topolancik, S. Chakrabarti, P. Bhattacharya","doi":"10.1109/DRC.2005.1553037","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553037","url":null,"abstract":"The authors present here the characteristics of an electrically injected single defect (or larger) photonic crystal microcavity device with quantum dot active region that exhibits single-mode behaviour in the output spectra. The devices are mechanically robust and the design minimizes thermal instabilities","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129727084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553112
K. Boutros, W. Luo, K. Shinohara
In this work, we report on vertically scaled, 100nm gate-length Al 0.31Ga0.69N/AlN/GaN HEMTs with a low sheet resistance of 260Omega/square, an fT of 125 GHz and an f max (Ug) of 174 GHz. Careful device design and unique process features also resulted in a high peak Gm,ext of 498 mS/mm, an Idss of 1.2A/mm, and a gate-to-drain breakdown of 30V
{"title":"Vertically-scaled 100nm T-gate AlGaN/GaN HEMTs with 125GHz f/sub T/ and 174GHz f/sub MAX/","authors":"K. Boutros, W. Luo, K. Shinohara","doi":"10.1109/DRC.2005.1553112","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553112","url":null,"abstract":"In this work, we report on vertically scaled, 100nm gate-length Al <sub>0.31</sub>Ga<sub>0.69</sub>N/AlN/GaN HEMTs with a low sheet resistance of 260Omega/square, an f<sub>T</sub> of 125 GHz and an f <sub>max</sub> (U<sub>g</sub>) of 174 GHz. Careful device design and unique process features also resulted in a high peak G<sub>m,ext</sub> of 498 mS/mm, an I<sub>dss</sub> of 1.2A/mm, and a gate-to-drain breakdown of 30V","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553117
S. Subbanna, G. Freeman, S. Koester, K. Rim, A. Joseph, D. Harame
This paper will focus on the various and ubiquitous uses of silicon-germanium (SiGe) in high-performance silicon-based semiconductor technology. SiGe can now qualify as a "mature" technology - it is almost 20 years since the first SiGe HBT work. It is 10 years since the qualification of SiGe as a manufacturable silicon technology in a high-volume silicon fabricator
{"title":"High-performance silicon-germanium technology","authors":"S. Subbanna, G. Freeman, S. Koester, K. Rim, A. Joseph, D. Harame","doi":"10.1109/DRC.2005.1553117","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553117","url":null,"abstract":"This paper will focus on the various and ubiquitous uses of silicon-germanium (SiGe) in high-performance silicon-based semiconductor technology. SiGe can now qualify as a \"mature\" technology - it is almost 20 years since the first SiGe HBT work. It is 10 years since the qualification of SiGe as a manufacturable silicon technology in a high-volume silicon fabricator","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128627984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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