Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553147
S. Kim, I. Adesida
The reliability of high electron mobility transistors (HEMTs) significantly depends on the stability of the gate Schottky contact to the semiconductor. Gate sinking during the fabrication and device operation alters transconductance, gate capacitance, and threshold voltage, which are crucial device parameters for modeling HEMT devices and designing circuits. In particular for enhancement-mode InAlAs/InGaAs/InP HEMTs (eHEMTs) where thermally-treated Pt is utilized as the gate metallization, thermal stability has always constituted a problem due to the diffusion of Pt. Although aspects of this diffusion are utilized to enhance e-mode behavior, no quantitative measurements have been conducted to estimate the diffusion depth of Pt in InAlAs. Further, it would be preferable to develop a metallization scheme where the Schottky contact barrier height is similar to that of Pt but with a much lower diffusivity. To this end, we have developed a gate metal structure based on Ir for InAlAs/InGaAs/InP HEMTs and investigated its thermal stability in comparison to the conventional Pt-based contact. A 0.15 um-gatelength eHEMT utilizing Ir/Ti/Pt/Au gate was fabricated to demonstrate the potential of Ir-based gate technology
{"title":"Enhancement-mode InAlAs/InGaAs/InP HEMTs with Ir-based gate metallization","authors":"S. Kim, I. Adesida","doi":"10.1109/DRC.2005.1553147","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553147","url":null,"abstract":"The reliability of high electron mobility transistors (HEMTs) significantly depends on the stability of the gate Schottky contact to the semiconductor. Gate sinking during the fabrication and device operation alters transconductance, gate capacitance, and threshold voltage, which are crucial device parameters for modeling HEMT devices and designing circuits. In particular for enhancement-mode InAlAs/InGaAs/InP HEMTs (eHEMTs) where thermally-treated Pt is utilized as the gate metallization, thermal stability has always constituted a problem due to the diffusion of Pt. Although aspects of this diffusion are utilized to enhance e-mode behavior, no quantitative measurements have been conducted to estimate the diffusion depth of Pt in InAlAs. Further, it would be preferable to develop a metallization scheme where the Schottky contact barrier height is similar to that of Pt but with a much lower diffusivity. To this end, we have developed a gate metal structure based on Ir for InAlAs/InGaAs/InP HEMTs and investigated its thermal stability in comparison to the conventional Pt-based contact. A 0.15 um-gatelength eHEMT utilizing Ir/Ti/Pt/Au gate was fabricated to demonstrate the potential of Ir-based gate technology","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122429835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553074
C. Lai, C.C. Huang, K. Chiang, H. Kao, W. Chen, A. Chin, C. Chi
We have obtained good non-volatile memory device integrity of fast 100mus program and 1ms erase time at plusmn13V, large initial memory window of 4.5V, and extrapolated 10-year memory window of 3.8V or 2.4V at 25 or 85degC in the new IrO2-HfAlO-AlN-SiO2-Si MONOS device
{"title":"Fast high-k AIN MONOS memory with large memory window and good retention","authors":"C. Lai, C.C. Huang, K. Chiang, H. Kao, W. Chen, A. Chin, C. Chi","doi":"10.1109/DRC.2005.1553074","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553074","url":null,"abstract":"We have obtained good non-volatile memory device integrity of fast 100mus program and 1ms erase time at plusmn13V, large initial memory window of 4.5V, and extrapolated 10-year memory window of 3.8V or 2.4V at 25 or 85degC in the new IrO2-HfAlO-AlN-SiO2-Si MONOS device","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553161
M. Higashiwaki, T. Matsui, T. Mimura
In conclusion, we demonstrated AlGaN/GaN HFETs with fT=163 GHz and fmax=184 GHz by using thin, high-Al-composition barrier layers, Cat-CVD SiN gate-insulating and passivation layers, and 60-nm T-gates defined by EB lithography
{"title":"Cat-CVD SiN insulated-gate AlGaN/GaN HFETs with 163 GHz f/sub T/ and 184 GHz f/sub max/","authors":"M. Higashiwaki, T. Matsui, T. Mimura","doi":"10.1109/DRC.2005.1553161","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553161","url":null,"abstract":"In conclusion, we demonstrated AlGaN/GaN HFETs with fT=163 GHz and fmax=184 GHz by using thin, high-Al-composition barrier layers, Cat-CVD SiN gate-insulating and passivation layers, and 60-nm T-gates defined by EB lithography","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131519974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553101
Yanfeng Wang, K. Lew, James B. Mattzela, J. Redwing, T. Mayer
The Si nanowires (SiNWs) used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH 4 in H2 as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH3) as the n-type dopant. The ratio of TMB or PH3 to SiH4 was varied from 0 to 10-2 to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700degC for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the -10 nm thick SiO2 shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 mum long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO2 shell, which served as the top gate dielectric. The n++ Si substrate coated with 100 nm of LPCVD Si3N4 was used as a back gate in these structures
{"title":"Top-gated field effect devices using oxidized silicon nanowires","authors":"Yanfeng Wang, K. Lew, James B. Mattzela, J. Redwing, T. Mayer","doi":"10.1109/DRC.2005.1553101","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553101","url":null,"abstract":"The Si nanowires (SiNWs) used in these studies were synthesized by vapor-liquid-solid (VLS) growth from Au catalyst particles using 10% SiH 4 in H2 as the silicon gas source, trimethylboron (TMB) as the p-type dopant, and phosphine (PH3) as the n-type dopant. The ratio of TMB or PH3 to SiH4 was varied from 0 to 10-2 to modulate the hole or electron carrier concentration in the SiNWs. Following growth, the Au catalyst particles were removed from the tips of the as-grown SiNWs, and the wires were cleaned using a modified RCA process prior to dry thermal oxidation at 700degC for 4 hours. Transmission electron microscopy studies show that the interface between the SiNW core and the -10 nm thick SiO2 shell is smooth and uniform. These SiNWs were integrated onto a top- and back-gated test structure by electrofludically aligning individual wires between pairs of large area electrodes. Source and drain (S/D) contacts were defined by first removing the oxide shell at the NW tips and then lifting off Ti(100nm)/Au(60nm) metal. Non-self-aligned 3 mum long top gates comprised of Ti(60nm)/Au(40nm) were then deposited on the SiO2 shell, which served as the top gate dielectric. The n++ Si substrate coated with 100 nm of LPCVD Si3N4 was used as a back gate in these structures","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553039
M. Grundmann, J. Speck, U. Mishra
The authors propose a new device design using the polarization properties of the III-nitrides system that eliminates the need for high doping concentrations and has the further benefit of potentially eliminating problematic p-type contacts. P-type material in the nitrides is plagued by high contact resistance and high sheet resistance. These problems could be eliminated by contacting n-type material that acts as a current spreading layer and using a tunnel junction to transfer current to p-type material with minimal losses (Takeuchi et al., 2001)
{"title":"Tunnel junctions in GaN/AlN for optoelectronic applications","authors":"M. Grundmann, J. Speck, U. Mishra","doi":"10.1109/DRC.2005.1553039","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553039","url":null,"abstract":"The authors propose a new device design using the polarization properties of the III-nitrides system that eliminates the need for high doping concentrations and has the further benefit of potentially eliminating problematic p-type contacts. P-type material in the nitrides is plagued by high contact resistance and high sheet resistance. These problems could be eliminated by contacting n-type material that acts as a current spreading layer and using a tunnel junction to transfer current to p-type material with minimal losses (Takeuchi et al., 2001)","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"26 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553159
L. Cywinski, H. Dery, L. Sham
Connection between spin orientation in semiconductors and optical selection rules has been exploited in spin LEDs (Fiederling et al., 1999), where the degree of luminescence polarization indicates the average spin of electrons injected into the diode. We present a proposal of a reciprocal device: a spin-based detector of circularly polarized light, in which the absorption occurs in the planar semiconductor (SC) structure
{"title":"Proposal of a spintronics-based polarization detector","authors":"L. Cywinski, H. Dery, L. Sham","doi":"10.1109/DRC.2005.1553159","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553159","url":null,"abstract":"Connection between spin orientation in semiconductors and optical selection rules has been exploited in spin LEDs (Fiederling et al., 1999), where the degree of luminescence polarization indicates the average spin of electrons injected into the diode. We present a proposal of a reciprocal device: a spin-based detector of circularly polarized light, in which the absorption occurs in the planar semiconductor (SC) structure","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116215425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553100
T. Bryllert, L. Samuelson, L. Jensen, L. Wernersson
We demonstrate a wrap-gated field effect transistor based on a matrix of vertically standing InAs nanowires (Jensen, et. al., 2004). A lower limit of the mobility, derived from the transconductance, is on the order of 3000 cm2/Vs. The narrow ~100 nm channels show excellent current saturation and a threshold of Vg = -0.15 V. The sub-threshold characteristics show a close to ideal slope of 62mV/decade over two orders of magnitude
{"title":"Vertical high mobility wrap-gated inas nanowire transistor","authors":"T. Bryllert, L. Samuelson, L. Jensen, L. Wernersson","doi":"10.1109/DRC.2005.1553100","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553100","url":null,"abstract":"We demonstrate a wrap-gated field effect transistor based on a matrix of vertically standing InAs nanowires (Jensen, et. al., 2004). A lower limit of the mobility, derived from the transconductance, is on the order of 3000 cm2/Vs. The narrow ~100 nm channels show excellent current saturation and a threshold of Vg = -0.15 V. The sub-threshold characteristics show a close to ideal slope of 62mV/decade over two orders of magnitude","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553115
Y. Dora, C. Suh, A. Chakraborty, S. Heikman, S. Chandrasekaran, V. Mehrotraa, U. Mishra
In this report we present the switching measurements on large area AlGaN/GaN HEMT devices with high breakdown voltage achieved with the help of multiple field plates. AlGaN/GaN high electron mobility transistors have shown potential advantages over Si and SiC based transistors for high power switching. The very high electron mobility in the AlGaN/GaN HEMT system combined with the high density of polarization induced 2D electron concentration yield a very low on-resistance and high switching frequency. Also the high band gap energy of AlGaN/GaN system results in a high critical electric field. Hence it is possible to have high voltage power switches capable of operating at high frequencies (~100MHz). However there are some difficulties, which have prevented the achievement of very high breakdown voltages at high frequency operation
{"title":"Switching characteristics of high-breakdown voltage AlGaN/GaN HEMTs","authors":"Y. Dora, C. Suh, A. Chakraborty, S. Heikman, S. Chandrasekaran, V. Mehrotraa, U. Mishra","doi":"10.1109/DRC.2005.1553115","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553115","url":null,"abstract":"In this report we present the switching measurements on large area AlGaN/GaN HEMT devices with high breakdown voltage achieved with the help of multiple field plates. AlGaN/GaN high electron mobility transistors have shown potential advantages over Si and SiC based transistors for high power switching. The very high electron mobility in the AlGaN/GaN HEMT system combined with the high density of polarization induced 2D electron concentration yield a very low on-resistance and high switching frequency. Also the high band gap energy of AlGaN/GaN system results in a high critical electric field. Hence it is possible to have high voltage power switches capable of operating at high frequencies (~100MHz). However there are some difficulties, which have prevented the achievement of very high breakdown voltages at high frequency operation","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125594516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553078
T. Yokoyama, T. Nishimura, K. Kita, K. Kyuno, A. Toriumi
This paper discusses a possible way to achieve better FET performances for both channels as well as a determination mechanism of the channel type. We investigated perfluoropentace (C22F14) (PF-pentacene) for n-channel and pentacene (C22F14) for p-channel FETs. On the basis of the energy level consideration for both channel material and S/D metals, we show a systematic guideline for achieving a better OFET performance
{"title":"Energy level consideration of source/channel/drain for performance enhancements of N- and P-channel organic FETs","authors":"T. Yokoyama, T. Nishimura, K. Kita, K. Kyuno, A. Toriumi","doi":"10.1109/DRC.2005.1553078","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553078","url":null,"abstract":"This paper discusses a possible way to achieve better FET performances for both channels as well as a determination mechanism of the channel type. We investigated perfluoropentace (C22F14) (PF-pentacene) for n-channel and pentacene (C22F14) for p-channel FETs. On the basis of the energy level consideration for both channel material and S/D metals, we show a systematic guideline for achieving a better OFET performance","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553068
B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog
Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide
在Si上外延生长的晶体高k氧化物允许进一步降低等效氧化物厚度(EOT)，是2013年以后要求EOT < 1nm的32nm CMOS技术模式中栅极电介质的潜在候选者。证明了钙钛矿型氧化物在硅上的外延生长，并实现了高晶体管迁移率(McKee et al.， 2001)。本文报道了二元氧化镨Pr2O3在Si(001)上的分子束外延(MBE)，根据热力学，它对硅是稳定的。pr2o3存在两种不同的相，晶格常数为11.152 Aring的立方相和晶格常数为3.8577 Aring和c=6.012 Aring的六方相(Burnham and Eyring, 1968; Adachi and Imanaka, 1998)。三次相的a/2与Si晶格常数的误差约为2.7%。六边形pr2o3的(0001)面相对于Si的(111)面误差仅为0.5%。初步结果表明(Osten et al.， 2001)，在Si(001)上生长的结晶pr2o3是一种很有前途的栅极绝缘体，具有足够高的k (k=30)和超低漏电流密度(10-8 a /cm2，电压g0 = + 1 V, EOT = 1.4 nm)和良好的可靠性。避免在Pr2O /Si界面处形成中间层是至关重要的，因为任何低钾硅酸盐样层都代表低容量串联，从而恶化了高钾氧化物的期望容量效果
{"title":"Molecular beam epitaxy of Pr/sub 2/O/sub 3/on Si","authors":"B. Tinkham, X. Guo, W. Braun, A. Trampert, K. Ploog","doi":"10.1109/DRC.2005.1553068","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553068","url":null,"abstract":"Crystalline high-k oxides epitaxially grown on Si which allow further reduction of equivalent oxide thickness (EOT), are potential candidates for gate dielectrics in the 32 nm CMOS technology mode requiring EOT < 1 nm beyond 2013. Epitaxial growth of perovskite-type oxides on Si for gate dielectrics was demonstrated and high transistor mobility was achieved (McKee et al., 2001). Here we report on molecular beam epitaxy (MBE) of binary praseodymium oxide Pr2O3 on Si (001) which according to thermodynamics should be stable against silicon. Two different phases of Pr2O3exist, a cubic phase with a lattice constant of 11.152 Aring, and a hexagonal phase with a=3.8577 Aring and c=6.012 Aring (Burnham and Eyring, 1968 and Adachi and Imanaka, 1998). The misfit between a/2 of the cubic phase and the Si lattice constant is about 2.7%. The misfit in the (0001) plane of the hexagonal Pr2 O3relative to the (111) plane of Si is only 0.5%. Preliminary results show (Osten et al., 2001) that crystalline Pr2 O3grown on Si(001) is a promising candidate for scaled gate insulators, displaying sufficiently high-k (k=30) combined with ultra-low leakage current density (10-8 A/cm2 at V g0 = plusmn 1 V for EOT = 1.4 nm) and good reliability. It is crucial to avoid the formation of interlayers at the Pr2O 3/Si interface, as any low-k silicate-like layers represent a low capacity in series which deteriorates the desired capacity effect of the high-k oxide","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：