Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553150
Z. Griffith, M. Rodwell, X. Fang, D. Loubychev, Ying Wu, J. Fastenau, A. Liu
The paper reports on InP/In0.53Ga0.47As /InP DHBTs fabricated using a conventional mesa structure, exhibiting a 450 GHz ftau and 490 GHz fmax, which is to our knowledge the highest simultaneous ftau and fmaxfor a mesa HBT. The collector has been scaled vertically to 120 nm for reduced electron collector transit time, aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors, and the base and emitter contact resistances rhoc have been reduced. The device reported here employs a 30 nm highly doped InGaAs base and an InGaAs/InAlAs superlattice base-collector grade
{"title":"In/sub 0.53/Ga/sub 0.47/As/InP type-I DHBTs having 450 GHz f/sub T/ and GHz f/sub max/ w/C/sub cb/I/sub c/ = 0.38 ps/V","authors":"Z. Griffith, M. Rodwell, X. Fang, D. Loubychev, Ying Wu, J. Fastenau, A. Liu","doi":"10.1109/DRC.2005.1553150","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553150","url":null,"abstract":"The paper reports on InP/In<sub>0.53</sub>Ga<sub>0.47</sub>As /InP DHBTs fabricated using a conventional mesa structure, exhibiting a 450 GHz f<sub>tau</sub> and 490 GHz f<sub>max</sub>, which is to our knowledge the highest simultaneous f<sub>tau</sub> and f<sub>max</sub>for a mesa HBT. The collector has been scaled vertically to 120 nm for reduced electron collector transit time, aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors, and the base and emitter contact resistances rho<sub>c</sub> have been reduced. The device reported here employs a 30 nm highly doped InGaAs base and an InGaAs/InAlAs superlattice base-collector grade","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126764469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553163
T. Kamimura, M. Maeda, Y. Nagamune, T. Nakanishi, K. Matsumoto
We have succeeded in observing the one dimensional sub-band structure of single walled carbon nanotube (SWNT) in the electrical measurement through the quantum capacitance effect, which could be observed even at room temperature. The sample structure was shown in Fig. 1. The SWNT was grown by chemical vapor deposition on a p-type silicon wafer with a thennally grown oxide. Pt/Au electrodes were deposited on the both side of the SW-NT for source and drain, and the back side of Si substrate for the gate. The channel length was 4 1tm. Thus, the back gate type SWNT-FET was fabricated. The left axis of Fig. 2 shows the gate voltage VG dependence of the drain Schottky barrier height of the SWNT-FET after the elimination of the adsorbed oxygen molecules by applying the Electrical Heating Process (EHP) I"2]. The SWNT-FET after EHP operates as a Schottky barrier transistor (SWNT-SBT). The barrier height qP was as large as qpB=1OO meV at VG-40 V. (The inset of Fig. 2 shows the band diagram at VG-40V near the drain contact.) The right axis of Fig. 2 shows the drain current IDVG characteristic of the SWNT-SBT with the constant drain voltage VD of I V, which indicates the ambipolar characteristics. Further increase of the drain voltage up to VD=10 V at 8.6 K, current step characteristics became appeared in the semi-logarithmic ID-VGcharacteristics as shown in Fig. 3, which are attributed to the oscillation characteristics of the quantum capacitance CQ [31. The gate capacitance consists of two components, one is the insulator capacitance Ci, which is originated from the geometry of the SWNT-SBT. And the other is the quantum capacitance CQ which is originated from the one dimensional sub-band structure of SWNT. In the present device, the CQ limits the operation of the device. The current step characteristics are resulted in the fact that the drain Schottky barrier is modulated stepwise by the effect of the quantum capacitance CQ. The CQ has the oscillation property corresponded to the saw teeth structure of the one dimensional sub-band structure of SWNT as shown in Fig. 4. Therefore, the current step characteristics in Fig. 3 indicate directly the sub-band structure in SWNT. The ratio of the gradients of the drain current IDin Fig. 3 at the step region and the slope region was estimated to be 3, which is almost in agreement with the ratio of the maximum and minimum of the CQ. The gate modulation coefficient a (which implies the ratio of the applied V0 and modulated potential energy in the SWNT-SBT) was estimated to be 0.071 from the other experimental results with the same sample structure device (not shown). Moreover, step width of the current step characteristics is about MaV6=0.5 eV, which is also in good agreement with the typical sub-band energy separation of 0.5 eV ofSWNT. Although a larger noise was superimposed, similar current step characteristics were also observed even at room temperature, owing to the large sub-band energy separation compared to the
{"title":"Electrical observation of one dimensional sub-band structure of carbon nanotube in schottky barrier transistor","authors":"T. Kamimura, M. Maeda, Y. Nagamune, T. Nakanishi, K. Matsumoto","doi":"10.1109/DRC.2005.1553163","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553163","url":null,"abstract":"We have succeeded in observing the one dimensional sub-band structure of single walled carbon nanotube (SWNT) in the electrical measurement through the quantum capacitance effect, which could be observed even at room temperature. The sample structure was shown in Fig. 1. The SWNT was grown by chemical vapor deposition on a p-type silicon wafer with a thennally grown oxide. Pt/Au electrodes were deposited on the both side of the SW-NT for source and drain, and the back side of Si substrate for the gate. The channel length was 4 1tm. Thus, the back gate type SWNT-FET was fabricated. The left axis of Fig. 2 shows the gate voltage VG dependence of the drain Schottky barrier height of the SWNT-FET after the elimination of the adsorbed oxygen molecules by applying the Electrical Heating Process (EHP) I\"2]. The SWNT-FET after EHP operates as a Schottky barrier transistor (SWNT-SBT). The barrier height qP was as large as qpB=1OO meV at VG-40 V. (The inset of Fig. 2 shows the band diagram at VG-40V near the drain contact.) The right axis of Fig. 2 shows the drain current IDVG characteristic of the SWNT-SBT with the constant drain voltage VD of I V, which indicates the ambipolar characteristics. Further increase of the drain voltage up to VD=10 V at 8.6 K, current step characteristics became appeared in the semi-logarithmic ID-VGcharacteristics as shown in Fig. 3, which are attributed to the oscillation characteristics of the quantum capacitance CQ [31. The gate capacitance consists of two components, one is the insulator capacitance Ci, which is originated from the geometry of the SWNT-SBT. And the other is the quantum capacitance CQ which is originated from the one dimensional sub-band structure of SWNT. In the present device, the CQ limits the operation of the device. The current step characteristics are resulted in the fact that the drain Schottky barrier is modulated stepwise by the effect of the quantum capacitance CQ. The CQ has the oscillation property corresponded to the saw teeth structure of the one dimensional sub-band structure of SWNT as shown in Fig. 4. Therefore, the current step characteristics in Fig. 3 indicate directly the sub-band structure in SWNT. The ratio of the gradients of the drain current IDin Fig. 3 at the step region and the slope region was estimated to be 3, which is almost in agreement with the ratio of the maximum and minimum of the CQ. The gate modulation coefficient a (which implies the ratio of the applied V0 and modulated potential energy in the SWNT-SBT) was estimated to be 0.071 from the other experimental results with the same sample structure device (not shown). Moreover, step width of the current step characteristics is about MaV6=0.5 eV, which is also in good agreement with the typical sub-band energy separation of 0.5 eV ofSWNT. Although a larger noise was superimposed, similar current step characteristics were also observed even at room temperature, owing to the large sub-band energy separation compared to the","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125190286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553146
R. Tsai, M. Lange, L.J. Lee, P. Nam, C. Namba, P. Liu, R. Sandhu, R. Grundbacher, W. Deal, A. Gutierrez
In this paper, we report AlSb/InAs HEMT high frequency perfornance up to 260 GHz fT. The 0.1-um gate length and 80-um total gate periphery devices exhibited a small-signal available gain of 10 dB at 100 GHz, and extrapolated fT and fmAx performance of 260 and 280 GHz, respectively at a drain voltage of 0.4 volts and drain current of 18 mA. To the best of our knowledge, this is the highest reported combination of simultaneous fT & fMAx reported for InAs-channel HEMTs. This fT result represents a significant improvement from our previously reported simultaneous fT and fMAx performances for AlSb/InAs HEMT's [1,2]. Particularly, in comparison to previous simultaneous fT and fMAx results of 220 and 275 GHz [2] small-signal model extractions indicate that the improvement in fT is attributed to a 23% reduction in gate-source capacitance from 65 fF to 50 fF. A low-field mobility of 26,300 cmN2/V-s was measured prior to fabrication by a Leheighton LEI 1600 contactless Hall measurement system. We have compared the mobility values measured from fabricated Hall effect structures and contactless Hall measurements prior to fabrication on other wafers grown with the same AlSb/InAs epitaxial profile. The Hall effect structures provide measured mobility over 3000 cmN/V-s greater than measurements by the contactless method. AlSb/InAs HEMTs offer more than two times increases in lowfield electron mobility and saturated electron velocity than InGaAs channel HEMTs, making them well suited for low power and high frequency amplifier applications for submillimeter wave frequencies and below. We have achieved excellent uniformity of device and circuit results on AlSb/InAs structures grown by molecular beam epitaxy (MBE) on semi-insulating 3" GaAs substrates. The uniformity of device characteristics is comparable to those of mature, production InAlAs/InGaAs HEMT's on 3" InP substrates. Electron beam lithography was utilized to fabricate 0.1 um Mo/Au T-gates in a 2 um source-drain region. The source to gate distance was 0.8 um. The devices were passivated with SiN and fabricated with two levels of interconnect metal including airbridges, 300 pF/mm2 doublelayer MIM capacitors, and 100-Ohm/sq precision NiCr resistors for circuit demonstration. We will discuss the development of state-of-the-art AlSb/InAs HEMT circuits at X-band and W-band.
{"title":"260 GHz F/sub T/, 280 GHz f/sub MAX/ AlSb/InAs HEMT technology","authors":"R. Tsai, M. Lange, L.J. Lee, P. Nam, C. Namba, P. Liu, R. Sandhu, R. Grundbacher, W. Deal, A. Gutierrez","doi":"10.1109/DRC.2005.1553146","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553146","url":null,"abstract":"In this paper, we report AlSb/InAs HEMT high frequency perfornance up to 260 GHz fT. The 0.1-um gate length and 80-um total gate periphery devices exhibited a small-signal available gain of 10 dB at 100 GHz, and extrapolated fT and fmAx performance of 260 and 280 GHz, respectively at a drain voltage of 0.4 volts and drain current of 18 mA. To the best of our knowledge, this is the highest reported combination of simultaneous fT & fMAx reported for InAs-channel HEMTs. This fT result represents a significant improvement from our previously reported simultaneous fT and fMAx performances for AlSb/InAs HEMT's [1,2]. Particularly, in comparison to previous simultaneous fT and fMAx results of 220 and 275 GHz [2] small-signal model extractions indicate that the improvement in fT is attributed to a 23% reduction in gate-source capacitance from 65 fF to 50 fF. A low-field mobility of 26,300 cmN2/V-s was measured prior to fabrication by a Leheighton LEI 1600 contactless Hall measurement system. We have compared the mobility values measured from fabricated Hall effect structures and contactless Hall measurements prior to fabrication on other wafers grown with the same AlSb/InAs epitaxial profile. The Hall effect structures provide measured mobility over 3000 cmN/V-s greater than measurements by the contactless method. AlSb/InAs HEMTs offer more than two times increases in lowfield electron mobility and saturated electron velocity than InGaAs channel HEMTs, making them well suited for low power and high frequency amplifier applications for submillimeter wave frequencies and below. We have achieved excellent uniformity of device and circuit results on AlSb/InAs structures grown by molecular beam epitaxy (MBE) on semi-insulating 3\" GaAs substrates. The uniformity of device characteristics is comparable to those of mature, production InAlAs/InGaAs HEMT's on 3\" InP substrates. Electron beam lithography was utilized to fabricate 0.1 um Mo/Au T-gates in a 2 um source-drain region. The source to gate distance was 0.8 um. The devices were passivated with SiN and fabricated with two levels of interconnect metal including airbridges, 300 pF/mm2 doublelayer MIM capacitors, and 100-Ohm/sq precision NiCr resistors for circuit demonstration. We will discuss the development of state-of-the-art AlSb/InAs HEMT circuits at X-band and W-band.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115550048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553139
Jing Wang, M. Lundstrom
Modem MOSFETs have channel lengths below 50 nm, and billion transistor logic chips have arrived. Moore's Law continues, but the end of MOSFET scaling is in sight. Many researchers are exploring new materials and device structures to push MOS technology towards fundamental limits. MOSFETs with strained silicon, SiGe, or even III-V channels are possibilities, as are one-dimensional channels made from nanowires or nanotubes. In this paper, we theoretically examine the impact of the channel material property (i.e., E(k)) and device structure (i.e., 2D planar vs. ID nanowire) on the ultimate performance of ballistic MOSFETs. The objective is to identify an optimum channel material for the ultimate planar/nanowire MOSFETs. The results show that when the transport effective mass is small, it degrades device performance, and that planar and nanowire MOSFETs behave differently. Different channel materials display different E(k) relations and different effective mass at the band-edge. To achieve high device performance, one might expect that a light transport effective mass would be best since it offers a high carrier injection velocity. On the other hand, a light effective mass also leads to a lower quantum (or semiconductor) capacitance, which degrades the ON-current of the device. When the channel length is sufficiently small, strong source-to-drain (S/D) tunneling occurs at a small transport effective mass. Tunneling degrades the subthreshold characteristics of the FET and consequently lowers the ON-current for the same OFF-current. For these reasons, an optimum transport effective mass may exist for a given device structure.
{"title":"Channel material optimization for the ultimate planar and nanowire mosfets: a theoretical exploration","authors":"Jing Wang, M. Lundstrom","doi":"10.1109/DRC.2005.1553139","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553139","url":null,"abstract":"Modem MOSFETs have channel lengths below 50 nm, and billion transistor logic chips have arrived. Moore's Law continues, but the end of MOSFET scaling is in sight. Many researchers are exploring new materials and device structures to push MOS technology towards fundamental limits. MOSFETs with strained silicon, SiGe, or even III-V channels are possibilities, as are one-dimensional channels made from nanowires or nanotubes. In this paper, we theoretically examine the impact of the channel material property (i.e., E(k)) and device structure (i.e., 2D planar vs. ID nanowire) on the ultimate performance of ballistic MOSFETs. The objective is to identify an optimum channel material for the ultimate planar/nanowire MOSFETs. The results show that when the transport effective mass is small, it degrades device performance, and that planar and nanowire MOSFETs behave differently. Different channel materials display different E(k) relations and different effective mass at the band-edge. To achieve high device performance, one might expect that a light transport effective mass would be best since it offers a high carrier injection velocity. On the other hand, a light effective mass also leads to a lower quantum (or semiconductor) capacitance, which degrades the ON-current of the device. When the channel length is sufficiently small, strong source-to-drain (S/D) tunneling occurs at a small transport effective mass. Tunneling degrades the subthreshold characteristics of the FET and consequently lowers the ON-current for the same OFF-current. For these reasons, an optimum transport effective mass may exist for a given device structure.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553038
A. Lunev, J. Zhang, Y. Bilenko, X. Hu, J. Deng, T. Katona, M. Shur, R. Gaska
We report record output power of deep ultraviolet (UV) LEDs with peak emission at 278 nm. These new light sources are expected to find numerous applications in air, water and surface sterilization/decontamination, bio-agent detection and identification, UV curing, biomedical and analytical instrumentation, etc. Recently we reported breakthrough in AlGaN-based deep UV LEDs with wallplug efficiency approaching 1%.' We will describe further improvements in the device design and processing for a better control of strain and carrier injection. These improvements yielded approximately 30% higher CW output powers close to 1. I mW at 20 mA current and 2 mW at 50 mA. The devices exhibit narrow emission line with FWHM of 11 nm and very high peak to stray light ratio close to 4 orders of magnitude, which to our knowledge is the best ratio ever reported for deep UV LEDs. We developed packaging solution for power combining of multiple deep UV LED chips with efficient heat dissipation. The UV lamp was made from 16 LEDs chips combined into 8x2 LED array in the form of 8 branches connected in parallel and each branch containing two LEDs connected in series. The lamp emitted at 278 nm and produced a continuous-wave power in excess of 11 mW at 200 mA. Under pulse operation the maximum power exceeding 110 mW was obtained at 1.9 A driving current. These are the highest CW and pulsed output power levels achieved in deep UV range.
{"title":"A 110 mW AlGaN-based UV lamp emitting at 278 nm","authors":"A. Lunev, J. Zhang, Y. Bilenko, X. Hu, J. Deng, T. Katona, M. Shur, R. Gaska","doi":"10.1109/DRC.2005.1553038","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553038","url":null,"abstract":"We report record output power of deep ultraviolet (UV) LEDs with peak emission at 278 nm. These new light sources are expected to find numerous applications in air, water and surface sterilization/decontamination, bio-agent detection and identification, UV curing, biomedical and analytical instrumentation, etc. Recently we reported breakthrough in AlGaN-based deep UV LEDs with wallplug efficiency approaching 1%.' We will describe further improvements in the device design and processing for a better control of strain and carrier injection. These improvements yielded approximately 30% higher CW output powers close to 1. I mW at 20 mA current and 2 mW at 50 mA. The devices exhibit narrow emission line with FWHM of 11 nm and very high peak to stray light ratio close to 4 orders of magnitude, which to our knowledge is the best ratio ever reported for deep UV LEDs. We developed packaging solution for power combining of multiple deep UV LED chips with efficient heat dissipation. The UV lamp was made from 16 LEDs chips combined into 8x2 LED array in the form of 8 branches connected in parallel and each branch containing two LEDs connected in series. The lamp emitted at 278 nm and produced a continuous-wave power in excess of 11 mW at 200 mA. Under pulse operation the maximum power exceeding 110 mW was obtained at 1.9 A driving current. These are the highest CW and pulsed output power levels achieved in deep UV range.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114768226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553103
Won n Park, Jin Suk Kim, JinKyung Yoo, G. Yi
A variety of elements and crystal structures of metal oxides allows for the integration of many magnetic, electronic, and optoelectronic functions into the materials, providing significant potential for realizing a diverse range of active devices [1]. For example, transparent conducting oxides (TCOs) such as indium-tin-oxide (ITO), SnO2, and ZnO have widely been used as window electrodes for flat panel displays, touch panels, and solar cells because of their unique features of excellent optical transparency and controllable electrical conductivity by impurity doping. Conventional TCOs have also been studied as semiconducting channel of thin-film transistors (TFTs) for invisible electronic circuit applications, but which are limited by the poor device performance resulting from the lack of high quality oxide semiconductor materials. The key parameters of SnO2 and ZnO TFTs, field-effect mobilities have been ranged from 0.1 to 10 cm2/Vs [2]. Since charge scattering by ionized impurities and grain-boundaries is thought to limit the performance, preparation of high-quality single-crystalline TCO with a low background carrier concentration is challengeable.
{"title":"High performance logic devices based on single crystalline ZnO nanorods","authors":"Won n Park, Jin Suk Kim, JinKyung Yoo, G. Yi","doi":"10.1109/DRC.2005.1553103","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553103","url":null,"abstract":"A variety of elements and crystal structures of metal oxides allows for the integration of many magnetic, electronic, and optoelectronic functions into the materials, providing significant potential for realizing a diverse range of active devices [1]. For example, transparent conducting oxides (TCOs) such as indium-tin-oxide (ITO), SnO2, and ZnO have widely been used as window electrodes for flat panel displays, touch panels, and solar cells because of their unique features of excellent optical transparency and controllable electrical conductivity by impurity doping. Conventional TCOs have also been studied as semiconducting channel of thin-film transistors (TFTs) for invisible electronic circuit applications, but which are limited by the poor device performance resulting from the lack of high quality oxide semiconductor materials. The key parameters of SnO2 and ZnO TFTs, field-effect mobilities have been ranged from 0.1 to 10 cm2/Vs [2]. Since charge scattering by ionized impurities and grain-boundaries is thought to limit the performance, preparation of high-quality single-crystalline TCO with a low background carrier concentration is challengeable.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130111464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553053
J. Kuzmík, J. Carlin, T. Kostopoulos, G. Konstantinidis, A. Georgakilas, D. Pogany
{"title":"Technology, properties and limitations of state-of-the-art InAlN/GaN HEMTs","authors":"J. Kuzmík, J. Carlin, T. Kostopoulos, G. Konstantinidis, A. Georgakilas, D. Pogany","doi":"10.1109/DRC.2005.1553053","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553053","url":null,"abstract":"","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133915028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553104
Y. Ding, A. Bapat, Y. Dong, C. Perrey, U. Kortshagen, C. B. Carter, S. Campbell
Unlike devices built using wafers, single nanoparticle semiconductor devices made from singlecrystal particles would allow the construction of high performance three-dimensional circuits and the integration of otherwise chemically and structurally incompatible single-crystal materials on virtually any substrate. This would dramatically reduce interconnect delay in integrated circuits, eliminate substrate parasitic effects, and allow the monolithic integration of complex systems.
{"title":"A single nanoparticle silicon transistor","authors":"Y. Ding, A. Bapat, Y. Dong, C. Perrey, U. Kortshagen, C. B. Carter, S. Campbell","doi":"10.1109/DRC.2005.1553104","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553104","url":null,"abstract":"Unlike devices built using wafers, single nanoparticle semiconductor devices made from singlecrystal particles would allow the construction of high performance three-dimensional circuits and the integration of otherwise chemically and structurally incompatible single-crystal materials on virtually any substrate. This would dramatically reduce interconnect delay in integrated circuits, eliminate substrate parasitic effects, and allow the monolithic integration of complex systems.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124464843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553069
A. Nayfeh, C. O. Chui, T. Yonehara, K.C. Saraswa
a) C. O. Chui was with the Dept. of EE at Stanford and is now with Intel Corporation, Santa Clara, CA 95054, USA b) T. Yonehara is with Leading-Edge Technology Development Headquarters, Canon Inc., 5-1, Morinosato-Wakamiya, Atsugi, Kanagawa 243-0193, Japan Abstract Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed smooth single crystal Ge layers on Si with defect density reduced to ~ 1 x 10 cm without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500 C process with low field mobility of ~250 cm/V-sec.
a) C. O. Chui曾任职于斯坦福大学电子电气系，现任职于英特尔公司，Santa Clara, CA 95054, USA。b) T. Yonehara任职于佳能公司，leadedge Technology Development总部，5-1,Morinosato-Wakamiya, Atsugi, Kanagawa, 243-0193。摘要:利用一种新的多步骤原位生长和氢退火工艺，异质外延锗层直接生长在硅上，缺陷限制在Si/Ge界面附近。因此，在这个4.2%的晶格不匹配系统中，不会像预期的那样穿到表面。结果表明，在没有渐变缓冲层或CMP步骤的情况下，在Si上获得了完全松弛的光滑单晶Ge层，缺陷密度降至~ 1 x 10 cm。为了证明Ge层的质量，pmosfet使用低于500 C的工艺制造，具有~250 cm/V-sec的低场迁移率。
{"title":"High mobility Ge pMOS fabricated using a novel heteroepitaxial ge on Si growth method","authors":"A. Nayfeh, C. O. Chui, T. Yonehara, K.C. Saraswa","doi":"10.1109/DRC.2005.1553069","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553069","url":null,"abstract":"a) C. O. Chui was with the Dept. of EE at Stanford and is now with Intel Corporation, Santa Clara, CA 95054, USA b) T. Yonehara is with Leading-Edge Technology Development Headquarters, Canon Inc., 5-1, Morinosato-Wakamiya, Atsugi, Kanagawa 243-0193, Japan Abstract Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed smooth single crystal Ge layers on Si with defect density reduced to ~ 1 x 10 cm without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500 C process with low field mobility of ~250 cm/V-sec.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130419675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553055
V. Kumar, G. Chen, S. Guo, B. Peres, I. Adesida
AlGaN/GaN high electron mobility transistors (HEMTs) are excellent candidates for high power and high frequency applications at room and elevated temperatures due to their superior material properties. As a result of improved material growth and processing technologies, microwave power densities have been demonstrated that are five to ten times greater than that of corresponding GaAs-based devices. Though GaN HEMTs using field plate have demonstrated power densities as high as 32W/mm at 4 GHz, however to date, there have been only few reports on field-plated devices up to X band [1,2]. In this paper, we present record power performance of AlGaN/GaN HEMTs on 6H-SiC substrates at 18 GHz. A CW output power density of 9.1 W/mm with a gain of 5.8 dB and power added efficiency of 23.7 % were achieved. The AlGaN HEMT structure used in the present study was grown on 6H-SiC substrates by metal organic chemical vapor deposition (MOCVD). The epilayer consists of an AlN buffer, 1.5 pm undoped GaN, and a 20 mm Al.30Ga70N barrier layer. Average sheet resistance across the as-grown wafer was 380 Q/sq as measured by Leighton. Device fabrication started with mesa isolation using C12/Ar plasma in an inductively-coupled-plasma reactive ion etch (ICP-RIE) system. Alloyed ohmic contacts of Ti/Al/Mo/Au were formed at 850°C with a low contact resistance of 0.15 ohm-mm. The source-drain spacing for these devices was 2.7 jim. Next, silicon nitride was deposited using PECVD system. Then 0.25 gm gatefootprints were patterned using e-beam lithography and etched through the silicon nitride film in a RIE system. The distance between the gate-footprint and source contact was 0.8 gm for all transistors. Finally, Ni/Au (300/2500 A) gamma-gates with different side-lobe lengths on the drain side were deposited by ebeam evaporation. Three side-lobe (field-plate) lengths were designed: 0.9, 1.2, and 1.5 jm. The devices had a total gate width of 100 jm. On-wafer DC measurements were performed using an HP4145B semiconductor parameter analyzer. Devices with different lengths of field plates had similar dc characteristics. Figure 1 shows a typical drain current-voltage (ID-VDS) characteristics for the device with a field plate length (LFP) of 1.5 jm. The gate was biased from -5 V to 2 V in a step of 1 V. The devices exhibited a maximum drain current density (ID,.) of 1.42 A/mm at a gate bias of 2 V and a drain bias of 9 V. The DC transfer characteristics for this device are shown in Fig. 2. The drain was biased at 7 V. A peak extrinsic transconductance (gm) of 437 mS/mm was measured at Vg, = -3.2 V. The high value of gm is attributed to the thin AlGaN barrier layer and the low contact resistance. On-wafer small signal RF measurements were carried out using a Cascade Microtech Probe and an HP851OC network analyzer. With the increase of field plate length from 0.9 to 1.5 pm, the cut-off frequency (fT) decreased from 50 to 41 GHz while the maximum frequency of oscillation (fm) degraded fro
AlGaN/GaN高电子迁移率晶体管(hemt)由于其优越的材料特性，是室温和高温下高功率和高频应用的优秀候选者。由于材料生长和加工技术的改进，微波功率密度已被证明比相应的gaas基器件高5到10倍。尽管使用场极板的GaN hemt已经证明在4ghz时功率密度高达32W/mm，但迄今为止，关于高达X波段的场极板器件的报道很少[1,2]。在本文中，我们提出了在18 GHz的6H-SiC衬底上的AlGaN/GaN hemt的创纪录功率性能。连续波输出功率密度为9.1 W/mm，增益为5.8 dB，功率增加效率为23.7%。本研究采用金属有机化学气相沉积(MOCVD)在6H-SiC衬底上生长AlGaN HEMT结构。涂层由AlN缓冲层、1.5 pm未掺杂的GaN和20 mm Al.30Ga70N阻挡层组成。Leighton测量的生长晶圆上的平均薄片电阻为380 Q/sq。在电感耦合等离子体反应离子蚀刻(ICP-RIE)系统中，使用C12/Ar等离子体进行台面隔离，开始器件制造。在850℃下形成Ti/Al/Mo/Au合金欧姆接触，接触电阻低至0.15 ω -mm。这些器件的源漏间距为2.7 jim。然后，利用PECVD系统沉积氮化硅。然后用电子束光刻技术刻制0.25 gm栅极足迹，并在RIE系统中通过氮化硅薄膜蚀刻。对于所有晶体管，栅极足迹和源触点之间的距离为0.8 gm。最后通过电子束蒸发在漏侧沉积不同旁瓣长度的Ni/Au (300/2500 A) γ门。设计了三个旁瓣(场板)长度:0.9、1.2和1.5 jm。这些器件的总栅极宽度为100 jm。晶圆上直流测量使用HP4145B半导体参数分析仪进行。不同场强板长度的器件具有相似的直流特性。图1显示了该器件在场极板长度(LFP)为1.5 jm时的典型漏极电流-电压(ID-VDS)特性。栅极在1 V的阶跃中从-5 V偏置到2 V。在栅极偏置2 V和漏极偏置9 V时，器件的最大漏极电流密度(ID，.)为1.42 a /mm。该器件的直流传输特性如图2所示。漏极偏置在7伏。在Vg = -3.2 V时，测量到的峰值外部跨导(gm)为437 mS/mm。高的gm值归因于较薄的AlGaN阻挡层和较低的接触电阻。晶圆上小信号射频测量使用级联微探针和HP851OC网络分析仪进行。随着场板长度从0.9 pm增加到1.5 pm，截止频率从50 GHz降低到41 GHz，最大振荡频率从81 GHz降低到63 GHz。这归因于栅极-漏极电容的增加。图3显示了场板长度(LFp)为1.5 lim时器件的小信号射频性能。采用Focus Microwave自动负载牵引系统进行了18 GHz的大信号连续波测量。这些数据是在没有任何热管理的情况下，在室温下进行的。在漏极偏置为40 V时，LFP分别为0.9、1.2和1.5 jm的器件的功率密度分别为5.4、6.4和7.3 W/mm。图4显示了该器件在漏极偏置为55 V时，L+p为1.5 jm时的大信号性能。该器件的输出功率为29.57 dBm，对应9.1 W/mm，相关增益为5.8 dB, PAE为23.7%。综上所述，我们已经展示了在18 GHz下具有场板的0.25 gm门长AlGaN/GaN hemt的连续波功率性能。这些结果证明了这些器件在X波段以外的高功率应用中的卓越潜力。[1] Y.-F。Wu et al.，“30 W/mm GaN HEMTs的场极板优化”，《电子开发》。[2]陈志强，“基于栅极扩展的AlGaN HEMT结构性能研究”，电子工程学报，vol. 25, p. 117(2004)。电子发展，vol. 51, p. 292 (2004)
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