Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553131
S. Unoa, N. Mori
Introduction Acoustic phonons in silicon-on-insulator (SOI) structures are different from those in bulk Si because of the large mechanical mismatch between Si and SiO2. Therefore, conventional modeling of electron transport in SOI, where bulk phonon wave function is assumed, must be re-examined. Equivalent investigations have been done for ILL-V semiconductors [1-3]. However, there are few investigations on Si/SiO2 systems such as SOI structures in spite of their technological significance. In this work, the impact of phonon wave modulation on electron transport in SOI is investigated theoretically. Phonon Normal Modes in SOI Structure Figure 1 shows an illustration of our SOI model used in the following analysis. The silicon plate is assumed to be embedded in bulk SiO with infinite extent. For mathematical convenience stress free boundaries are assumed at z + LJ2, and L is set much larger than the thickness of the Si plate, d. As the system is isotropic along the Si plate, the phonon normal modes in the x/l direction are simply plane waves. On the other hand, nonnal modes are more complicated in the z direction due to mechanical mismatch between Si and SiO2. Such phonon normal modes are often categorized using Fig. 2, where phonon frequency, a4 vs. wave vector along xll axis, qll, is plotted [4]. The two straight lines are defined by longitudinal sound velocities in Si (vsi,l = 9.0 x 10 m/s ) and SiO2 (v0,.l = 5.9 x 103 m/s). Type (I) w> viq,ll,: longitudinal phonon normal modes have sinusoidal wave forms as shown in Fig. 3 (I). Type (II) vsil qH > a)> vo,, qH,: normal modes are sinusoidal in SiO2, and decay exponentially in Si as in Fig. 3 (II). Type (III) vox,1q/l > w: normal modes decay exponentially both in Si and SiO2 as shown in Fig. 3 (III) (surface mode). It is important to note that no confined mode exists in the SOI structure, that is, there is no normal mode such that amplitude is limited in the Si region and energy is quantized. Reduction of Acoustic Phonon Scattering Potential The dominant electron-phonon interaction in Si is the acoustic deformation potential (ADP) scattering, and its scattering potential is written as HADP (z) = DADpV * u, where DADP is a coupling constant, and u is a phonon normal mode. Figure 4 shows the squared absolute value of V u as a function of z, which is equivalent to the strain caused by the phonon vibration u. Note that the strain in the Si region is less than that in bulk Si (dashed line), while the strain in the oxide region is increased. This has been observed in a similar SiISiO2 system, and referred to as 'strain absorption' [5]. Figure 5 shows an integral of HADP within Si region (-d/2 < z < d/2) plotted as a function of w. The value of qll was fixed, and the thickness of the Si region was set as (a) d = 50 nm (b) d = 10 nm. The spikes observed in solid curves are caused by interference between longitudinal and transverse phonon modes. The three types of phonon modes appear in different ranges of
{"title":"Phonon modification in SOI structures and its impact on electron transport","authors":"S. Unoa, N. Mori","doi":"10.1109/DRC.2005.1553131","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553131","url":null,"abstract":"Introduction Acoustic phonons in silicon-on-insulator (SOI) structures are different from those in bulk Si because of the large mechanical mismatch between Si and SiO2. Therefore, conventional modeling of electron transport in SOI, where bulk phonon wave function is assumed, must be re-examined. Equivalent investigations have been done for ILL-V semiconductors [1-3]. However, there are few investigations on Si/SiO2 systems such as SOI structures in spite of their technological significance. In this work, the impact of phonon wave modulation on electron transport in SOI is investigated theoretically. Phonon Normal Modes in SOI Structure Figure 1 shows an illustration of our SOI model used in the following analysis. The silicon plate is assumed to be embedded in bulk SiO with infinite extent. For mathematical convenience stress free boundaries are assumed at z + LJ2, and L is set much larger than the thickness of the Si plate, d. As the system is isotropic along the Si plate, the phonon normal modes in the x/l direction are simply plane waves. On the other hand, nonnal modes are more complicated in the z direction due to mechanical mismatch between Si and SiO2. Such phonon normal modes are often categorized using Fig. 2, where phonon frequency, a4 vs. wave vector along xll axis, qll, is plotted [4]. The two straight lines are defined by longitudinal sound velocities in Si (vsi,l = 9.0 x 10 m/s ) and SiO2 (v0,.l = 5.9 x 103 m/s). Type (I) w> viq,ll,: longitudinal phonon normal modes have sinusoidal wave forms as shown in Fig. 3 (I). Type (II) vsil qH > a)> vo,, qH,: normal modes are sinusoidal in SiO2, and decay exponentially in Si as in Fig. 3 (II). Type (III) vox,1q/l > w: normal modes decay exponentially both in Si and SiO2 as shown in Fig. 3 (III) (surface mode). It is important to note that no confined mode exists in the SOI structure, that is, there is no normal mode such that amplitude is limited in the Si region and energy is quantized. Reduction of Acoustic Phonon Scattering Potential The dominant electron-phonon interaction in Si is the acoustic deformation potential (ADP) scattering, and its scattering potential is written as HADP (z) = DADpV * u, where DADP is a coupling constant, and u is a phonon normal mode. Figure 4 shows the squared absolute value of V u as a function of z, which is equivalent to the strain caused by the phonon vibration u. Note that the strain in the Si region is less than that in bulk Si (dashed line), while the strain in the oxide region is increased. This has been observed in a similar SiISiO2 system, and referred to as 'strain absorption' [5]. Figure 5 shows an integral of HADP within Si region (-d/2 < z < d/2) plotted as a function of w. The value of qll was fixed, and the thickness of the Si region was set as (a) d = 50 nm (b) d = 10 nm. The spikes observed in solid curves are caused by interference between longitudinal and transverse phonon modes. The three types of phonon modes appear in different ranges of","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115291357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553064
M. Y. Louie, D. A. Miller, M. E. Jacob, L. Forbes
Klumperink et al.,[1] have recently had a number of publications on the low frequency noise of n-channel MOSFET's under switched gate bias conditions. We have also previously investigated the same type of devices, older 5 micron commercial devices, under the same type of switched bias conditions and have independently confirmed these prior results. There is an anomalous reduction in I/f noise at frequencies two orders of magnitude below the switching frequency.[2] The reduction occurs only when holes are accumulated at the surface under the gate when the transistor is off during the switched bias. We have also investigated the time dependence of switched bias 1/f noise and have discovered long term time dependent transients in the I/f noise.[3]
{"title":"Long term transients in MOSFEG 1/f noise under switched bias conditions","authors":"M. Y. Louie, D. A. Miller, M. E. Jacob, L. Forbes","doi":"10.1109/DRC.2005.1553064","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553064","url":null,"abstract":"Klumperink et al.,[1] have recently had a number of publications on the low frequency noise of n-channel MOSFET's under switched gate bias conditions. We have also previously investigated the same type of devices, older 5 micron commercial devices, under the same type of switched bias conditions and have independently confirmed these prior results. There is an anomalous reduction in I/f noise at frequencies two orders of magnitude below the switching frequency.[2] The reduction occurs only when holes are accumulated at the surface under the gate when the transistor is off during the switched bias. We have also investigated the time dependence of switched bias 1/f noise and have discovered long term time dependent transients in the I/f noise.[3]","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125179792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553061
Shui-Jinn Wang, Shiue-lung Chen, K. Uang, Yu-Cheng Yang, Tron-min Chen, B. Liou
{"title":"Effect of surface treatment on the performances of vertical-structured GaN-based LEDs with electroplating metallic substrate","authors":"Shui-Jinn Wang, Shiue-lung Chen, K. Uang, Yu-Cheng Yang, Tron-min Chen, B. Liou","doi":"10.1109/DRC.2005.1553061","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553061","url":null,"abstract":"","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124974143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553110
Yong Cai, Yugang Zhou, K. J. Chen, K. Lau
Wide bandgap AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as excellent candidates for high power, high frequency and also high temperature applications. Up to now, the focus has been to improve the performance of depletion-mode (D-mode) AlGaN/GaN HEMTs. From the application point of view, enhancement-mode (E-mode) HEMTs have many advantages. For applications such as high frequency PAs and LNAs, E-mode HEMTs allow elimination of negative-polarity voltage supply, thereby reducing the circuit complexity and cost. For digital applications, direct-coupled FET logic (DCFL) that features integration of D-mode and E-mode HEMTs offers the simplest circuit configuration. Several approaches, such as chloride-based ICP gate recess etching [1], [2] and gate metal (e.g. Pt) sunk into AlGaN cap layer by rapid thermal annealing [3], were used to achieve E-mode AlGaN/GaN HEMTs. However, the gate recess etching approach may encounter large gate leakage currents and the gate metal sinking process can only take effects on samples with near zero pinch off voltages. Here, we demonstrate a reliable technique to fabricate E-mode AlGaN/GaN HEMTs using a fluoride-based plasma treatment and post-gate rapid thermal annealing. The schematic cross section of E-mode AlGaN/GaN HEMT is shown in Fig. 1. Starting with a conventional D-mode AlGaN/GaN heterostructure sample, (electron sheet density 1.3x 1013 cm-2 and and mobility 1000 cm2/Vs), device mesa was etched using C12/He plasma dry etching followed by source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 850'C for 45 seconds. After gate windows with 1 gm length were opened by contact photolithography, the sample was treated by CF4 plasma in an RIE system at an RF plasma power of 150W for 150 sec. Ni/Au e-beam evaporation and lift-off were carried out subsequently to form the gate electrodes. The plasma treated gate region and the gate electrode were self-aligned. Post-gate rapid thermal annealing (RTA) was conducted at 400 °C for lOmins. The devices have a source-gate spacing of Lsg = I um and a gate-drain spacing of Lgd = 2 um. D-mode HEMTs were also fabricated on the same sample without plasma treatment to the gate region. Figure 2 shows the transfer characteristics of both D-mode and E-mode AlGaN/GaN HEMTs. Defining V,h as the gate bias intercept of the linear extrapolation of drain current at the point of peak transconductance (g) the V,h of E-mode device was determined to be 0.9 V, while the V1h of D-mode device is 4.0 V. At Vgs = OV, the transconductance reaches zero, indicating a true enhancement-mode operation. The drain current is well pinched off and shows a leakage of 28 gA/mm at Vd, = 6 V, the smallest value reported to date for E-mode AlGaN/GaN HEMTs. The peak gm, is 151 mS/mm for the D-mode HEMT and 148 mS/mm for the E-mode HEMT, respectively. The maximum drain current ('max) reaches 313mA/mm at a gate bias (Vgs) of 3V. Figure 3 shows the output curves of the E-mode device befor
{"title":"Self-aligned enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment","authors":"Yong Cai, Yugang Zhou, K. J. Chen, K. Lau","doi":"10.1109/DRC.2005.1553110","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553110","url":null,"abstract":"Wide bandgap AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as excellent candidates for high power, high frequency and also high temperature applications. Up to now, the focus has been to improve the performance of depletion-mode (D-mode) AlGaN/GaN HEMTs. From the application point of view, enhancement-mode (E-mode) HEMTs have many advantages. For applications such as high frequency PAs and LNAs, E-mode HEMTs allow elimination of negative-polarity voltage supply, thereby reducing the circuit complexity and cost. For digital applications, direct-coupled FET logic (DCFL) that features integration of D-mode and E-mode HEMTs offers the simplest circuit configuration. Several approaches, such as chloride-based ICP gate recess etching [1], [2] and gate metal (e.g. Pt) sunk into AlGaN cap layer by rapid thermal annealing [3], were used to achieve E-mode AlGaN/GaN HEMTs. However, the gate recess etching approach may encounter large gate leakage currents and the gate metal sinking process can only take effects on samples with near zero pinch off voltages. Here, we demonstrate a reliable technique to fabricate E-mode AlGaN/GaN HEMTs using a fluoride-based plasma treatment and post-gate rapid thermal annealing. The schematic cross section of E-mode AlGaN/GaN HEMT is shown in Fig. 1. Starting with a conventional D-mode AlGaN/GaN heterostructure sample, (electron sheet density 1.3x 1013 cm-2 and and mobility 1000 cm2/Vs), device mesa was etched using C12/He plasma dry etching followed by source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 850'C for 45 seconds. After gate windows with 1 gm length were opened by contact photolithography, the sample was treated by CF4 plasma in an RIE system at an RF plasma power of 150W for 150 sec. Ni/Au e-beam evaporation and lift-off were carried out subsequently to form the gate electrodes. The plasma treated gate region and the gate electrode were self-aligned. Post-gate rapid thermal annealing (RTA) was conducted at 400 °C for lOmins. The devices have a source-gate spacing of Lsg = I um and a gate-drain spacing of Lgd = 2 um. D-mode HEMTs were also fabricated on the same sample without plasma treatment to the gate region. Figure 2 shows the transfer characteristics of both D-mode and E-mode AlGaN/GaN HEMTs. Defining V,h as the gate bias intercept of the linear extrapolation of drain current at the point of peak transconductance (g) the V,h of E-mode device was determined to be 0.9 V, while the V1h of D-mode device is 4.0 V. At Vgs = OV, the transconductance reaches zero, indicating a true enhancement-mode operation. The drain current is well pinched off and shows a leakage of 28 gA/mm at Vd, = 6 V, the smallest value reported to date for E-mode AlGaN/GaN HEMTs. The peak gm, is 151 mS/mm for the D-mode HEMT and 148 mS/mm for the E-mode HEMT, respectively. The maximum drain current ('max) reaches 313mA/mm at a gate bias (Vgs) of 3V. Figure 3 shows the output curves of the E-mode device befor","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553084
K. Tsubaki, H. Shioya, J. Ono, Y. Nakajima, T. Hanajiri, H. Yamaguchi
New concepts of electronic components are needed to fabricate further high-performance integrated circuit. One of the new concepts is the incorporation of inductors into integrated circuits. The incorporation into integrated circuits, however, has the difficulty in three dimensional nano-fabrication technique, and the small effect due to the small quantity of magnetic permeability of o = 4 it x10-7 H/m and the large diameter of the inductor's wires. We have proposed the inductors made of carbon nanotube [1, 2]. Ihough the fabrication of the proposed inductor is still challenging and has many problems, merits of the proposed inductor are following, 1. Since the radius (r) of carbon nanotube are several nm, the magnetic field (H) induced by the current (1) in carbon nanotube is about one thousand times larger than that induced by the current in normal copper wire whose radius is about several gm. (H = I/2;zr) 2. According to the relation between magnetic field (I) in the inductor and inductance (L) of the inductor, 1/2 JPOH2dV = 1/2LI2, the large magnetic field (A) results in the large inductance (L). 3. Since the carbon nanotube can be bent with small curvature, the inductor made of carbon nanotube is smaller than the inductor made of copper or gold. In this paper, we have observed the large magnetic field induced by the small current in carbon nanotube using magnetic force microscope [31. The used carbon nanotube was made by laser ablation method. After the dispersing the carbon nanotube on the SiO 2/Si substrate, gold/nickel metal interconnects to the carbon nanotube. By applying the alternating current in carbon nanotube, we have obtained the images of synchronized component in the force signal using lock' in measurement. Since the images were the convolution of Kelvin force microscopy and magnetic force microscopy images, we extracted the magnetic field distribution using the symmetry difference between the magnetic and electric field. Observed magnetic fields were proportional to the amplitude of the alternating current. The estimated magnetic field near the carbon nanotube of 8 mT at 250 pA roughly agrees with the theoretical one. This magnetic field is also very large compared with that produced by the copper wire in the normal inductor. Since the inductance of 1.0 ,um long carbon nanotube is estimated to be about 1 pH, normalized inductance is found to be larger than that of normal inductance [21. Therefore, carbon nanotube inductors are promising passive electric component for the integrated circuit Reference [1]Y. Sakurada, S. Irako, Y. Nakajima, T. Hanajiri, K. Tsubaki, Ext. Abstr. (51st Spring meet 2004); Japan Society of Applied Physics and Related Societies, 29p-F-16. 121S. Irako, Y. Sakurada, Y. Nakajima, T. Hanajiri, T. Toyabe, K. Tsubaki, Ext. Abstr. (51st Spring meet. 2004); Japan Society of Applied Physics and Related Societies, 29p-F-15. 13]D. Saida and T. Takahashi, Jpn. J. Appl. Phys. Vol. 42, pp.4874, 2003.
{"title":"Large magnetic field induced by carbon nanotube current -proposal of carbon nanotube inductors","authors":"K. Tsubaki, H. Shioya, J. Ono, Y. Nakajima, T. Hanajiri, H. Yamaguchi","doi":"10.1109/DRC.2005.1553084","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553084","url":null,"abstract":"New concepts of electronic components are needed to fabricate further high-performance integrated circuit. One of the new concepts is the incorporation of inductors into integrated circuits. The incorporation into integrated circuits, however, has the difficulty in three dimensional nano-fabrication technique, and the small effect due to the small quantity of magnetic permeability of o = 4 it x10-7 H/m and the large diameter of the inductor's wires. We have proposed the inductors made of carbon nanotube [1, 2]. Ihough the fabrication of the proposed inductor is still challenging and has many problems, merits of the proposed inductor are following, 1. Since the radius (r) of carbon nanotube are several nm, the magnetic field (H) induced by the current (1) in carbon nanotube is about one thousand times larger than that induced by the current in normal copper wire whose radius is about several gm. (H = I/2;zr) 2. According to the relation between magnetic field (I) in the inductor and inductance (L) of the inductor, 1/2 JPOH2dV = 1/2LI2, the large magnetic field (A) results in the large inductance (L). 3. Since the carbon nanotube can be bent with small curvature, the inductor made of carbon nanotube is smaller than the inductor made of copper or gold. In this paper, we have observed the large magnetic field induced by the small current in carbon nanotube using magnetic force microscope [31. The used carbon nanotube was made by laser ablation method. After the dispersing the carbon nanotube on the SiO 2/Si substrate, gold/nickel metal interconnects to the carbon nanotube. By applying the alternating current in carbon nanotube, we have obtained the images of synchronized component in the force signal using lock' in measurement. Since the images were the convolution of Kelvin force microscopy and magnetic force microscopy images, we extracted the magnetic field distribution using the symmetry difference between the magnetic and electric field. Observed magnetic fields were proportional to the amplitude of the alternating current. The estimated magnetic field near the carbon nanotube of 8 mT at 250 pA roughly agrees with the theoretical one. This magnetic field is also very large compared with that produced by the copper wire in the normal inductor. Since the inductance of 1.0 ,um long carbon nanotube is estimated to be about 1 pH, normalized inductance is found to be larger than that of normal inductance [21. Therefore, carbon nanotube inductors are promising passive electric component for the integrated circuit Reference [1]Y. Sakurada, S. Irako, Y. Nakajima, T. Hanajiri, K. Tsubaki, Ext. Abstr. (51st Spring meet 2004); Japan Society of Applied Physics and Related Societies, 29p-F-16. 121S. Irako, Y. Sakurada, Y. Nakajima, T. Hanajiri, T. Toyabe, K. Tsubaki, Ext. Abstr. (51st Spring meet. 2004); Japan Society of Applied Physics and Related Societies, 29p-F-15. 13]D. Saida and T. Takahashi, Jpn. J. Appl. Phys. Vol. 42, pp.4874, 2003.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553124
S. Sugahara, M. Tanaka
Spin transistors, which utilize two ferromagnetic layers as a spin injector and as a spin detector, are very attractive as a basis for spin-electronic integrated circuits, owing to their additional spin degree of freedom in controlling output currents. In particular, recently proposed spin MOSFETs that are spin transistors analogous to MOSFETs are promising, since its prospected large current-drive capability, large magnetocurrent ratio, and compatibility with present MOS technology can lead to novel nonvolatile memory and reconfigurable logic architectures [1-3]. The spin MOSFETs can be classified by the structure of the source/drain and the source/drain material [1]. The simplest and most feasible way to realize a spin MOSFET is to replace the source/drain material of an Schottky barrier (SB) MOSFET with a ferromagnetic metal that forms a ferromagnetic Schottky junction with the Si channel (Fig.l). In this paper, we present the theoretical analysis and experimental demonstration of spin MOSFETs using a ferromagnetic metal for the SB source/drain. Fig.1 shows the structure of our model device used in the calculations. Assuming the ballistic transport of spin-polarized carriers in the nanometer-scale channel, the device performance was theoretically analyzed. Solid and dashed curves in Fig. 2 show calculated drain currents IDP and IDAP as a function of drain bias VDs in the parallel and antiparallel magnetization configurations, respectively, where gate bias VGS varied from 0.0 to 1.0 V in steps of 0.2 V. When the relative magnetization configuration of the source/drain is parallel, the spin MOSFET shows a large output current comparable to that of high performance MOSFETs, indicating the high transcondactance of the spin MOSFET. The output current for small VDS conditions (less than the pinch-off voltage) can be reduced by changing the relative magnetization of the source/drain from the parallel to antiparallel configuration. Figs. 3 and 4 show magnetocurrent ratio Nc [=(IDP-IDAP)/IDAP] as a function of VDs and VGS, respectively. Nc falls with increasing VDs, but it is enhanced with increasing VGS. These phenomena can be rationalized by spin dependent transport similar to the tunneling magnetoresistance effect and the gate-induced enhancement of spin injection efficiency [1]. The SB height SB of the source/drain is important to obtain large output currents and also large Nc. IDP dramatically increases with decreasing S5B in comparison with IDAP, and thus Nc increases with decreasing B, as shown in Fig. 5. This means that IDP and Nc can simultaneously increase without any trade-off, which is important for spin-electronic integrated circuit applications. In order to demonstrate the transistor action of a spin MOSFET using a ferromagnetic metal for the SB source/drain, a prototypic spin MOSFET was fabricated by using ferromagnetic silicide Fe,-1Si,. A bottom-gate structure with a SOI substrate was employed for simplicity, where the buried oxide and
{"title":"Spin mosfets using ferromagnetic schottky barrier contacts for the source and drain","authors":"S. Sugahara, M. Tanaka","doi":"10.1109/DRC.2005.1553124","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553124","url":null,"abstract":"Spin transistors, which utilize two ferromagnetic layers as a spin injector and as a spin detector, are very attractive as a basis for spin-electronic integrated circuits, owing to their additional spin degree of freedom in controlling output currents. In particular, recently proposed spin MOSFETs that are spin transistors analogous to MOSFETs are promising, since its prospected large current-drive capability, large magnetocurrent ratio, and compatibility with present MOS technology can lead to novel nonvolatile memory and reconfigurable logic architectures [1-3]. The spin MOSFETs can be classified by the structure of the source/drain and the source/drain material [1]. The simplest and most feasible way to realize a spin MOSFET is to replace the source/drain material of an Schottky barrier (SB) MOSFET with a ferromagnetic metal that forms a ferromagnetic Schottky junction with the Si channel (Fig.l). In this paper, we present the theoretical analysis and experimental demonstration of spin MOSFETs using a ferromagnetic metal for the SB source/drain. Fig.1 shows the structure of our model device used in the calculations. Assuming the ballistic transport of spin-polarized carriers in the nanometer-scale channel, the device performance was theoretically analyzed. Solid and dashed curves in Fig. 2 show calculated drain currents IDP and IDAP as a function of drain bias VDs in the parallel and antiparallel magnetization configurations, respectively, where gate bias VGS varied from 0.0 to 1.0 V in steps of 0.2 V. When the relative magnetization configuration of the source/drain is parallel, the spin MOSFET shows a large output current comparable to that of high performance MOSFETs, indicating the high transcondactance of the spin MOSFET. The output current for small VDS conditions (less than the pinch-off voltage) can be reduced by changing the relative magnetization of the source/drain from the parallel to antiparallel configuration. Figs. 3 and 4 show magnetocurrent ratio Nc [=(IDP-IDAP)/IDAP] as a function of VDs and VGS, respectively. Nc falls with increasing VDs, but it is enhanced with increasing VGS. These phenomena can be rationalized by spin dependent transport similar to the tunneling magnetoresistance effect and the gate-induced enhancement of spin injection efficiency [1]. The SB height SB of the source/drain is important to obtain large output currents and also large Nc. IDP dramatically increases with decreasing S5B in comparison with IDAP, and thus Nc increases with decreasing B, as shown in Fig. 5. This means that IDP and Nc can simultaneously increase without any trade-off, which is important for spin-electronic integrated circuit applications. In order to demonstrate the transistor action of a spin MOSFET using a ferromagnetic metal for the SB source/drain, a prototypic spin MOSFET was fabricated by using ferromagnetic silicide Fe,-1Si,. A bottom-gate structure with a SOI substrate was employed for simplicity, where the buried oxide and","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128796531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553077
D. Zhao, Yan Zhu, Ruigang Li, Jianlin Liu
Nonvolatile Si nanocrystal memory is fast approaching commercialization. In order to extend the scaling limits, many kinds of nanocrystals or device architectures were used to replace Si nanocrystals. In this work, we report for the first time the experimental demonstration of a nonvolatile memory device using cobalt silicide nanocrystals as floating gates. The band diagram is shown in Fig. 1 (a). There are at least two advantage of using cobalt silicide nanocrystal over Si nanocrystal: first, cobalt silicide is a metallic material and its band edges for conduction and valence bands are all lower than those of the Si [1], which helps both electron and hole retentions. Second, cobalt silicide can be grown on Si nanocrystal plus a rapid thermal annealing (RTP) [2]. The self-aligned silicide remains while the unreacted metal cobalt is removed in selective etchant. The device fabrication begins with a thermal oxide growth at 1000 °C for 4.5 minutes on a 4-inch n-type Si substrate, which leads to a tunneling oxide thickness ofabout 3 nm. Si nanocrystals were formed in a LPCVD furnace followed by a deposition of ultra thin Co metal in an e-beam evaporator. RTP is then performed in nitrogen to form silicide. The unreacted cobalt metal was removed in a selective. The control oxide (40 nm) was grown in another LPCVD furnace. A MOS capacitor is finally obtained after depositing and patterning the aluminum electrodes on frond and back sides of the sample. An SEM image of the CoSi2 nanocrystals on SiO2 is shown in Fig.1 (b).
{"title":"Cobalt silicide nanocrystal memory","authors":"D. Zhao, Yan Zhu, Ruigang Li, Jianlin Liu","doi":"10.1109/DRC.2005.1553077","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553077","url":null,"abstract":"Nonvolatile Si nanocrystal memory is fast approaching commercialization. In order to extend the scaling limits, many kinds of nanocrystals or device architectures were used to replace Si nanocrystals. In this work, we report for the first time the experimental demonstration of a nonvolatile memory device using cobalt silicide nanocrystals as floating gates. The band diagram is shown in Fig. 1 (a). There are at least two advantage of using cobalt silicide nanocrystal over Si nanocrystal: first, cobalt silicide is a metallic material and its band edges for conduction and valence bands are all lower than those of the Si [1], which helps both electron and hole retentions. Second, cobalt silicide can be grown on Si nanocrystal plus a rapid thermal annealing (RTP) [2]. The self-aligned silicide remains while the unreacted metal cobalt is removed in selective etchant. The device fabrication begins with a thermal oxide growth at 1000 °C for 4.5 minutes on a 4-inch n-type Si substrate, which leads to a tunneling oxide thickness ofabout 3 nm. Si nanocrystals were formed in a LPCVD furnace followed by a deposition of ultra thin Co metal in an e-beam evaporator. RTP is then performed in nitrogen to form silicide. The unreacted cobalt metal was removed in a selective. The control oxide (40 nm) was grown in another LPCVD furnace. A MOS capacitor is finally obtained after depositing and patterning the aluminum electrodes on frond and back sides of the sample. An SEM image of the CoSi2 nanocrystals on SiO2 is shown in Fig.1 (b).","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114140717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553102
Qin Zhang, Wei Zhao, A. Seabaugh
Recent experimental demonstrations of interband tunnel transistors by Appenzeller [1], in carbon nanotubes, and simulations by Bhuwalka [2], of vertical Si/SiGe p-i-n interband tunnel transistors show that subthreshold swings of 40 mV/decade or less can be achieved in tunneling transistors. We derive here, a simple analytic expression for the subthreshold swing in tunnel transistors which shows that there are two physical mechanisms in tunnel transistors which can be optimized to achieve low subthreshold swings. Extending from this analysis we propose a new silicon-on-insulator tunnel transistor to achieve low subthreshold swing toward significantly lowering power in digital logic devices.
{"title":"Analytic expression and approach for low subthreshold-swing tunnel transistors","authors":"Qin Zhang, Wei Zhao, A. Seabaugh","doi":"10.1109/DRC.2005.1553102","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553102","url":null,"abstract":"Recent experimental demonstrations of interband tunnel transistors by Appenzeller [1], in carbon nanotubes, and simulations by Bhuwalka [2], of vertical Si/SiGe p-i-n interband tunnel transistors show that subthreshold swings of 40 mV/decade or less can be achieved in tunneling transistors. We derive here, a simple analytic expression for the subthreshold swing in tunnel transistors which shows that there are two physical mechanisms in tunnel transistors which can be optimized to achieve low subthreshold swings. Extending from this analysis we propose a new silicon-on-insulator tunnel transistor to achieve low subthreshold swing toward significantly lowering power in digital logic devices.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-20DOI: 10.1109/DRC.2005.1553087
G. Withey, A. Lazareck, M. Tzolov, A. Yin, P. Aich, Joanne I. Yeh, J.M. Xu
We report on a redox protein highly ordered carbon nanotube (CNT) array conjugate system that exhibits an exceptionally high level of bioelectrocatalytic activity. The performance of the conjugated system is dependent upon site-selective placement of the protein on the nanotube. Enzymes immobilized on the nanotube tip have generated electrical biosignals more than 60 times greater than enzymes bound to the nanotube side walls, and have shown electron transfer rates on the order of 1500 sQ1. The substrate concentration dependence of the bioelectrocatalytic signal was measured by CV, and a detection limit in the single micromolar range was achieved. We conclude that the covalent attachment of redox enzymes to CNT tips enhances electron transfer efficiency by orders of magnitude when compared to side-wall adsorption, and that the resulting system enables real-time monitoring ofbiomolecular activities. The nanoelectronic platform that has enabled this novel course of study is a hexagonally ordered array of aligned multi-walled carbon nanotubes (MWNTs). Unique features of this array critical to this study include identical exposed nanotube length across the entire array, highly regular center-to-center CNT spacing, and electrical insulation of individual nanotubes within an aluminum oxide nanopore array. This configuration of nanotubes allows us to differentiate between the two distinctly different regions of the CNTs: the side walls which are highly hydrophobic and amenable to protein adsorption, and the tips that are easily oxidized and can be covalently modified with enzymes by carboxyl-amine coupling. We have exploited these properties to independently study the bioelectrocatalytic activity of enzymes bound to the two regions. A CNT array electrode was first treated with the surfactant arabic gum (GA) to prevent protein adsorption to the side wall and then the enzyme glucose oxidase (GOx) was covalently bound to the nanotube tips. On another sample, the nanotube tips were capped with ethanolamine to remove any free carboxylic acid groups, and then GOx was adsorbed to the protein sidewall. Gold nanoparticle labeling experiments were used to visually confirm the successful selective immobilization of GOx at the CNT tips, and an ELISA was performed to quantify the extent of enzyme coverage on the tips and on the side walls. We determined there to be more than 60 times more protein adsorbed to the side walls than GOx covalently linked to the CNT tips. Cyclic voltammetry (CV) measurements revealed the current density of each sample to be nearly the same (-l20±A*cm-2). This means that each enzyme bound to the CNT tip is contributing, on average, more than 60 times the electrical signal as GOx adsorbed to the nanotube side wall. A saturation assay was then performed to determine the unimolecular electron transfer rate (kET) of the tip-bound GOx-CNT conjugate system. Based on the peak current density (330pA*cm2) and the surface enzyme coverage determined
{"title":"Optimization of a redox protein-carbon nanotube conjugate biosensor by siteselective binding","authors":"G. Withey, A. Lazareck, M. Tzolov, A. Yin, P. Aich, Joanne I. Yeh, J.M. Xu","doi":"10.1109/DRC.2005.1553087","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553087","url":null,"abstract":"We report on a redox protein highly ordered carbon nanotube (CNT) array conjugate system that exhibits an exceptionally high level of bioelectrocatalytic activity. The performance of the conjugated system is dependent upon site-selective placement of the protein on the nanotube. Enzymes immobilized on the nanotube tip have generated electrical biosignals more than 60 times greater than enzymes bound to the nanotube side walls, and have shown electron transfer rates on the order of 1500 sQ1. The substrate concentration dependence of the bioelectrocatalytic signal was measured by CV, and a detection limit in the single micromolar range was achieved. We conclude that the covalent attachment of redox enzymes to CNT tips enhances electron transfer efficiency by orders of magnitude when compared to side-wall adsorption, and that the resulting system enables real-time monitoring ofbiomolecular activities. The nanoelectronic platform that has enabled this novel course of study is a hexagonally ordered array of aligned multi-walled carbon nanotubes (MWNTs). Unique features of this array critical to this study include identical exposed nanotube length across the entire array, highly regular center-to-center CNT spacing, and electrical insulation of individual nanotubes within an aluminum oxide nanopore array. This configuration of nanotubes allows us to differentiate between the two distinctly different regions of the CNTs: the side walls which are highly hydrophobic and amenable to protein adsorption, and the tips that are easily oxidized and can be covalently modified with enzymes by carboxyl-amine coupling. We have exploited these properties to independently study the bioelectrocatalytic activity of enzymes bound to the two regions. A CNT array electrode was first treated with the surfactant arabic gum (GA) to prevent protein adsorption to the side wall and then the enzyme glucose oxidase (GOx) was covalently bound to the nanotube tips. On another sample, the nanotube tips were capped with ethanolamine to remove any free carboxylic acid groups, and then GOx was adsorbed to the protein sidewall. Gold nanoparticle labeling experiments were used to visually confirm the successful selective immobilization of GOx at the CNT tips, and an ELISA was performed to quantify the extent of enzyme coverage on the tips and on the side walls. We determined there to be more than 60 times more protein adsorbed to the side walls than GOx covalently linked to the CNT tips. Cyclic voltammetry (CV) measurements revealed the current density of each sample to be nearly the same (-l20±A*cm-2). This means that each enzyme bound to the CNT tip is contributing, on average, more than 60 times the electrical signal as GOx adsorbed to the nanotube side wall. A saturation assay was then performed to determine the unimolecular electron transfer rate (kET) of the tip-bound GOx-CNT conjugate system. Based on the peak current density (330pA*cm2) and the surface enzyme coverage determined ","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134129625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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