Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553065
B. Ghosh, Xiao-Feng Fan, L. Register, S. Banerjee
As device dimensions are being scaled to their ultimate limits, channel mobility engineering seems to offer one of the best prospects of improved performance of metal oxide semiconductor field effect transistors (MOSFETs). In fact, new materials, such as Ge, with higher effective mobilities of electrons (2times) and holes (4times) than in Si are already being explored to increase the drive currents in MOSFETs. In addition, by straining the Ge channels, it is possible to further increase the mobilities of the holes. However, how this advantage in mobility translates to improved drive current in the short-channel length MOSFETs is not completely clear. For example, in the ballistic limit, it is thermal velocity that matters (Lundstrom, 1997) and these are comparable for Si and Ge. Although, there have been reports from some experimental and theoretical (in the ballistic limit) studies of the mobility and drive current enhancements of unstrained and strained Ge channel MOSFETs over Si MOSFETs, no Monte Carlo simulation taking into account full band structure, scattering, non local field effects, etc., has so far been been performed. The aim of this work was to perform a full band Monte Carlo simulation study of unstrained Ge bulk N- and P- MOSFETs and strained Ge bulk PMOSFETs and compare with their Si counterparts. Since biaxial strain along the (100) plane in Ge does not break the degeneracy of the conduction band L valleys of Ge, we have not considered strained Ge NMOSFETs
{"title":"Monte carlo study of germanium N- and P- MOSFETs","authors":"B. Ghosh, Xiao-Feng Fan, L. Register, S. Banerjee","doi":"10.1109/DRC.2005.1553065","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553065","url":null,"abstract":"As device dimensions are being scaled to their ultimate limits, channel mobility engineering seems to offer one of the best prospects of improved performance of metal oxide semiconductor field effect transistors (MOSFETs). In fact, new materials, such as Ge, with higher effective mobilities of electrons (2times) and holes (4times) than in Si are already being explored to increase the drive currents in MOSFETs. In addition, by straining the Ge channels, it is possible to further increase the mobilities of the holes. However, how this advantage in mobility translates to improved drive current in the short-channel length MOSFETs is not completely clear. For example, in the ballistic limit, it is thermal velocity that matters (Lundstrom, 1997) and these are comparable for Si and Ge. Although, there have been reports from some experimental and theoretical (in the ballistic limit) studies of the mobility and drive current enhancements of unstrained and strained Ge channel MOSFETs over Si MOSFETs, no Monte Carlo simulation taking into account full band structure, scattering, non local field effects, etc., has so far been been performed. The aim of this work was to perform a full band Monte Carlo simulation study of unstrained Ge bulk N- and P- MOSFETs and strained Ge bulk PMOSFETs and compare with their Si counterparts. Since biaxial strain along the (100) plane in Ge does not break the degeneracy of the conduction band L valleys of Ge, we have not considered strained Ge NMOSFETs","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125227767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553042
G. Atwood, R. Bez
Non-volatile memories (NVM) are playing an important role in the semiconductor market, thanks in particular to flash which is used mainly in cellular phones and other types of electronic portable equipment. In the coming years portable systems will demand even more NVM with high density and very high writing throughput for data storage application, or with fast random access for code execution. Flash memory has followed the scaling evolution, of the semiconductor map since its introduction in the late '80's but further scaling is becoming increasingly complex as some of the fundamental physical limitations are being approached. While continued research on floating gate techniques should extend the current flash technology capability through the end of this decade, there is increasing interest in new memory storage mechanisms and materials that have promise for scaling through at least the end of the next decade. Among the different NVM based on storage mechanisms alternative to the floating gate concept, phase-change memories (PCM), also called ovionic unified memory (OUM),is one of the most promising candidates, having the potential to improve the performance compared to flash as well as to be scalable beyond flash technology (Lai and Lowrey (2001), Lai (2003), Bez (2004)), In this review, the physics and operation of phase change memory is first presented, followed by discussion of current status of development. Finally, the scaling capability of the technology is absent
非易失性存储器(NVM)在半导体市场上扮演着重要的角色，特别是主要用于手机和其他类型的电子便携式设备的闪存。在未来几年，便携式系统将需要更多的NVM，这些NVM具有高密度和非常高的写入吞吐量，用于数据存储应用程序，或者具有用于代码执行的快速随机访问。闪存自上世纪80年代末问世以来，一直遵循半导体地图的缩放进化，但随着一些基本物理限制的接近，进一步的缩放变得越来越复杂。虽然对浮栅技术的持续研究将在本十年末扩展当前闪存技术的能力，但人们对新的存储器存储机制和材料的兴趣越来越大，这些机制和材料有望至少在下一个十年末实现规模扩展。在不同的基于浮动门概念替代存储机制的NVM中，相变存储器(PCM)，也称为电子统一存储器(OUM)，是最有前途的候选之一，与闪存相比，具有提高性能的潜力，并且可以超越闪存技术(Lai和Lowrey (2001)， Lai (2003)， Bez(2004))。在本文中，首先介绍了相变存储器的物理和操作。接着讨论了目前的发展现状。最后，该技术缺乏规模化能力
{"title":"Current status of chalcogenide phase change memory","authors":"G. Atwood, R. Bez","doi":"10.1109/DRC.2005.1553042","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553042","url":null,"abstract":"Non-volatile memories (NVM) are playing an important role in the semiconductor market, thanks in particular to flash which is used mainly in cellular phones and other types of electronic portable equipment. In the coming years portable systems will demand even more NVM with high density and very high writing throughput for data storage application, or with fast random access for code execution. Flash memory has followed the scaling evolution, of the semiconductor map since its introduction in the late '80's but further scaling is becoming increasingly complex as some of the fundamental physical limitations are being approached. While continued research on floating gate techniques should extend the current flash technology capability through the end of this decade, there is increasing interest in new memory storage mechanisms and materials that have promise for scaling through at least the end of the next decade. Among the different NVM based on storage mechanisms alternative to the floating gate concept, phase-change memories (PCM), also called ovionic unified memory (OUM),is one of the most promising candidates, having the potential to improve the performance compared to flash as well as to be scalable beyond flash technology (Lai and Lowrey (2001), Lai (2003), Bez (2004)), In this review, the physics and operation of phase change memory is first presented, followed by discussion of current status of development. Finally, the scaling capability of the technology is absent","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553118
Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi
Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness
具有NiSi2/Si(111)面FUSI S/D的金属/高k SOI mosfet有望用于缩小至低于10 nm栅极长度的大规模器件。我们所开发的面结技术随着栅极长度的减小而更有效地工作。该器件概念可以应用于finfet等3D结构，并且还可以减轻SOI厚度的缩放
{"title":"Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain","authors":"Y. Watanabe, S. Migita, N. Mise, T. Nabatame, H. Satake, A. Toriumi","doi":"10.1109/DRC.2005.1553118","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553118","url":null,"abstract":"Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553094
K. Long, A. Kattamis, I. Cheng, H. Gleskova, S. Wagner, J. Sturm
In this paper, the authors have developed an a-Si TFT process on clear plastic substrates which allows direct transfer of industry a-Si TFT process on glass to plastic substrate for flexible electronics applications. The high temperature process increases the reliability of the a-Si TFT's, which is critical for OLED's where one TFT must operate in a DC condition
在本文中，作者开发了透明塑料基板上的a-Si TFT工艺，该工艺允许将玻璃上的工业a-Si TFT工艺直接转移到塑料基板上，用于柔性电子应用。高温工艺提高了a- si TFT的可靠性，这对于必须在直流条件下工作的OLED至关重要
{"title":"Increased reliability of a-Si TFT's deposited on clear plastic substrates at high temperatures","authors":"K. Long, A. Kattamis, I. Cheng, H. Gleskova, S. Wagner, J. Sturm","doi":"10.1109/DRC.2005.1553094","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553094","url":null,"abstract":"In this paper, the authors have developed an a-Si TFT process on clear plastic substrates which allows direct transfer of industry a-Si TFT process on glass to plastic substrate for flexible electronics applications. The high temperature process increases the reliability of the a-Si TFT's, which is critical for OLED's where one TFT must operate in a DC condition","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133741761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553089
H. Tsai, J. Zoval, M. Madou
In this paper, a "responsive drug delivery system", in which a sensor measures a marker in the patient's body and releases medication the patient requires at any given moment is developed. In this way, we can precisely control the drug concentration in patient's body to enhance drug efficiency and lessen side effects. In order to achieve responsive drug delivery, a reliable release device (e.g., a valve) has to be developed. Biocompatibility, low energy consumption, minimal and no leakage are the main requirements for such a release method
{"title":"Bi-layer artificial muscle valves for drug delivery devices","authors":"H. Tsai, J. Zoval, M. Madou","doi":"10.1109/DRC.2005.1553089","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553089","url":null,"abstract":"In this paper, a \"responsive drug delivery system\", in which a sensor measures a marker in the patient's body and releases medication the patient requires at any given moment is developed. In this way, we can precisely control the drug concentration in patient's body to enhance drug efficiency and lessen side effects. In order to achieve responsive drug delivery, a reliable release device (e.g., a valve) has to be developed. Biocompatibility, low energy consumption, minimal and no leakage are the main requirements for such a release method","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553049
Muralikrishnan Balakrishnan, M. Kozicki, C. Gopalan, M. Mitkova
In the present work, the authors describe PMC memory devices based on Ag-Ge-S electrolytes. These have excellent temperature stability and are compatible with most BEOL processing in CMOS integrated circuits
{"title":"Germanium sulfide-based solid electrolytes for non-volatile memory","authors":"Muralikrishnan Balakrishnan, M. Kozicki, C. Gopalan, M. Mitkova","doi":"10.1109/DRC.2005.1553049","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553049","url":null,"abstract":"In the present work, the authors describe PMC memory devices based on Ag-Ge-S electrolytes. These have excellent temperature stability and are compatible with most BEOL processing in CMOS integrated circuits","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129213134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553151
C. Monier, A. Cavus, R. Sandhu, D. Li, P. Nam, B. Chan, A. Oshiro, D. Matheson, A. Gutierrez-Aitken
In bipolar logic circuits, the use of a narrow band gap Inx Ga1-xAs system with high indium content (80 < x < 100) materials in the base layer will primarily impact the device turn-on voltage VBE that could be reduced by half compared to conventional III-V technologies. This will directly translate to lower supply voltage in digital applications. This paper discusses device technology for bipolar circuit applications based on material systems with lattice parameter towards that of InAs
在双极逻辑电路中，在基层中使用具有高铟含量(80 < x < 100)材料的窄带隙Inx Ga1-xAs系统将主要影响器件的导通电压VBE，与传统的III-V技术相比，可以降低一半。这将直接转化为数字应用中的较低电源电压。本文讨论了基于晶格参数材料体系的双极电路器件技术
{"title":"High performance low power 6.0 A HBT devices and circuits","authors":"C. Monier, A. Cavus, R. Sandhu, D. Li, P. Nam, B. Chan, A. Oshiro, D. Matheson, A. Gutierrez-Aitken","doi":"10.1109/DRC.2005.1553151","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553151","url":null,"abstract":"In bipolar logic circuits, the use of a narrow band gap Inx Ga1-xAs system with high indium content (80 < x < 100) materials in the base layer will primarily impact the device turn-on voltage VBE that could be reduced by half compared to conventional III-V technologies. This will directly translate to lower supply voltage in digital applications. This paper discusses device technology for bipolar circuit applications based on material systems with lattice parameter towards that of InAs","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121579817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553092
Lisong Zhou, Sungkyu Park, Bo Bai, Jie Sun, Sheng-Chu Wu, T. Jackson, S. Nelson, D. Freeman, Yongtaek Hong
This paper reports on 48 times 48 pixels pentacene TFT driven active-matrix OLED displays on glass substrate. To our best knowledge these are the largest pentacene TFT driven displays
{"title":"All-organic active matrix oled display","authors":"Lisong Zhou, Sungkyu Park, Bo Bai, Jie Sun, Sheng-Chu Wu, T. Jackson, S. Nelson, D. Freeman, Yongtaek Hong","doi":"10.1109/DRC.2005.1553092","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553092","url":null,"abstract":"This paper reports on 48 times 48 pixels pentacene TFT driven active-matrix OLED displays on glass substrate. To our best knowledge these are the largest pentacene TFT driven displays","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115674364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553148
J. Moon, K. Wang, R. Rajavel, S. Bui, D. Wong, D. Chow, J. Jenson
In this paper, we report a prototype demonstration of room-temperature resonant tunneling-coupled transistors in FET layout (TCT), in which tunneling characteristics such as negative differential resistance (NDR) and peak current are directly controlled by surface Schottky gate with high gain and transconductance. Functionality of the device can also be switched between FET mode and tunneling transistor mode. The fabrication process is fully compatible with conventional FET processes, offering a fully integrable and scalable tunneling transistor technology. Prototype planar TCTs were fabricated with resonantly-coupled dual-channel InAlAs/InGaAs/InP HEMT heterostructures by providing independent electrical contacts to each channel. The current-voltage characteristics are determined by an interwell and intersubband tunneling. The fabrication process was done using an I-line Cannon stepper on full 3-inch wafers with implanted back-gates defined prior to MBE growth of closely-coupled dual-channel HEMT layers. The highest mobility of the closely-coupled dual-channel HEMT layers observed so far is 9600 cmWs at room temperature
{"title":"Planar tunneling-coupled field-effect transistor for low-power mixed-signal applications","authors":"J. Moon, K. Wang, R. Rajavel, S. Bui, D. Wong, D. Chow, J. Jenson","doi":"10.1109/DRC.2005.1553148","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553148","url":null,"abstract":"In this paper, we report a prototype demonstration of room-temperature resonant tunneling-coupled transistors in FET layout (TCT), in which tunneling characteristics such as negative differential resistance (NDR) and peak current are directly controlled by surface Schottky gate with high gain and transconductance. Functionality of the device can also be switched between FET mode and tunneling transistor mode. The fabrication process is fully compatible with conventional FET processes, offering a fully integrable and scalable tunneling transistor technology. Prototype planar TCTs were fabricated with resonantly-coupled dual-channel InAlAs/InGaAs/InP HEMT heterostructures by providing independent electrical contacts to each channel. The current-voltage characteristics are determined by an interwell and intersubband tunneling. The fabrication process was done using an I-line Cannon stepper on full 3-inch wafers with implanted back-gates defined prior to MBE growth of closely-coupled dual-channel HEMT layers. The highest mobility of the closely-coupled dual-channel HEMT layers observed so far is 9600 cmWs at room temperature","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125688048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-22DOI: 10.1109/DRC.2005.1553129
N. Lu, H. Li, M. Gardner, D. Kwong
Physical and electrical characteristics of HfTaTiO gate dielectric have been systematically investigated for the first time. HfTaTiO has a higher dielectric constant (kappa~56) and acceptable barrier height to Si (phi=1.0eV), and ultra-thin EOT(~9Aring) has been achieved. HfTaTiO dielectric shows higher crystallization temperature (900degC), reduced hysteresis, 50% higher mobility and improved Vth instability than HfO2. Moreover, HfTaTiO exhibits excellent SILC and breakdown characteristics
{"title":"Higher k HfTaTiO gate dielectric with improved material and electrical characteristics","authors":"N. Lu, H. Li, M. Gardner, D. Kwong","doi":"10.1109/DRC.2005.1553129","DOIUrl":"https://doi.org/10.1109/DRC.2005.1553129","url":null,"abstract":"Physical and electrical characteristics of HfTaTiO gate dielectric have been systematically investigated for the first time. HfTaTiO has a higher dielectric constant (kappa~56) and acceptable barrier height to Si (phi=1.0eV), and ultra-thin EOT(~9Aring) has been achieved. HfTaTiO dielectric shows higher crystallization temperature (900degC), reduced hysteresis, 50% higher mobility and improved Vth instability than HfO2. Moreover, HfTaTiO exhibits excellent SILC and breakdown characteristics","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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