Pub Date : 2007-08-14DOI: 10.1109/ICEPT.2007.4441413
C. Yin, Y. Lee, C. Bailey, S. Riches, C. Cartwnght, R. Sharpe, H. Ott
This paper investigated the thermal design of the light emitting diode (LED) onto the board and its packaging. The LED was a 6-lead MultiLED with 3 chips designed for LCD backlighting and other lighting purposes. A 3D finite element model of this LED was built up and thermal analysis was carried out using the multi physics software package, PHYSICA. The modeling results were presented as temperature distributions in each LED, and the predicted junction temperature was used for the thermal resistance calculation. The results for the board structure indicated that (1) removing the foil attach decreased the thermal resistance, (2) Increasing the copper foil thickness reduced the thermal resistance. Package design indicated that the SMT designed LED with integrated slug gave lower thermal resistance. Pb-free solder material gave lower thermal resistance and junction temperature when compared with conductive adhesive.
{"title":"Thermal Analysis of LEDs for Liquid Crystal Display's Backlighting","authors":"C. Yin, Y. Lee, C. Bailey, S. Riches, C. Cartwnght, R. Sharpe, H. Ott","doi":"10.1109/ICEPT.2007.4441413","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441413","url":null,"abstract":"This paper investigated the thermal design of the light emitting diode (LED) onto the board and its packaging. The LED was a 6-lead MultiLED with 3 chips designed for LCD backlighting and other lighting purposes. A 3D finite element model of this LED was built up and thermal analysis was carried out using the multi physics software package, PHYSICA. The modeling results were presented as temperature distributions in each LED, and the predicted junction temperature was used for the thermal resistance calculation. The results for the board structure indicated that (1) removing the foil attach decreased the thermal resistance, (2) Increasing the copper foil thickness reduced the thermal resistance. Package design indicated that the SMT designed LED with integrated slug gave lower thermal resistance. Pb-free solder material gave lower thermal resistance and junction temperature when compared with conductive adhesive.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130652332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441392
De-jian Zhou, H. Huang, K. Peng
That the QFP components are applied successfully depends on its heat design and analysis. So, in tins paper, facing the application of encapsulation design and assembly, a three dimensional model based on temperature field and its simulation analysis is carried out by using the finite element method under different cooling condition and structure parameters, according to such problems for QFP as cooling design the heat effect of the thickness of encapsulation layer and chip. And, some relevant results are achieved and some corresponding advices for heat design are put forward with practice. These methods and conclusions can provide the QFP designer of structure and techniques of components encapsulation and assembly a lot of references.
{"title":"The Thermal Analysis of QFP Components Geared to the Needs of the Application of Encapsulation Design and Assembly","authors":"De-jian Zhou, H. Huang, K. Peng","doi":"10.1109/ICEPT.2007.4441392","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441392","url":null,"abstract":"That the QFP components are applied successfully depends on its heat design and analysis. So, in tins paper, facing the application of encapsulation design and assembly, a three dimensional model based on temperature field and its simulation analysis is carried out by using the finite element method under different cooling condition and structure parameters, according to such problems for QFP as cooling design the heat effect of the thickness of encapsulation layer and chip. And, some relevant results are achieved and some corresponding advices for heat design are put forward with practice. These methods and conclusions can provide the QFP designer of structure and techniques of components encapsulation and assembly a lot of references.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441530
B. Schwarz
Thermo mechanical stresses in electronics can be calculated by FEM but sometimes it is faster and more comfortable to Measure the deformations of your Boards and electronic Components to see their behavior if temperature is changing. During the electronic product lifetime the soldering process is the highest thermo mechanical stress. Especially for the lead free reflow peak of more than 240degC some material combinations show a large deformation. But also later in the field at customer side the time to failure is depending from the stress & strain to the product. The differences day/night and operating/standby cause a thermo mechanic cycling and products fail if materials are getting tired and function fails. Beside other processes like diffusion and migration tins thermo mechanical stress can lead to early life time end. So it is important that the thermo-mechanical deformations are minimized and risks are noticed right in time - if possible during prototype stadium - where normally a high pressure of time and a quick measurement technique is welcome. The trend to higher application temperatures (e.g. Automotive sector: engine control) also is a main reason to care about tins land of optimizations. Due to the fact that the electronic board manufacturing in the assembly lines are consisting of many single processes but the components from the different suppliers are not known in regard to their material details and compositions, it's often not possible to start a simulation, which delivers true results, but it's much easier and faster to do a deformation measurement as a function of temperature. Three different measurement techniques (methods) are introduced: Shadow Moire or Interference Technique; Pattern Correlation Technique: Line Projection Technique. Finally some results are shown and examples from Siemens Product optimizations are given (comparison of different board materials/manufacturers, effect of preconditioning (tempering) to the warpage behavior of PBGA. examples of failures & failure modes if stress/strain is too high). Of course the measurement results are used to confirm the FEM results (No FEM without verification) and support DOE. But our experience is, that this methods of the quick measurement of deformations is used mainly as a tool to perform a kind of incoming inspection of delivered supplements like packages and boards. Often a poor thermo mechanical behavior could be proved and any changes of package properties of different date code lots could be recognized. If those male functions are detected before products reach our customers a lot of money (rework) could be saved and products of high thermo mechanical stability with few internal stresses could be delivered to market. The ratio of winning knowledge to examination costs is very high and the deformation measurements are used in all sectors of electronic product manufacturing.
{"title":"Deformation Measurements used for Design Optimization and Verification during Industrial Electronic Board (Product) Manufacturing","authors":"B. Schwarz","doi":"10.1109/ICEPT.2007.4441530","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441530","url":null,"abstract":"Thermo mechanical stresses in electronics can be calculated by FEM but sometimes it is faster and more comfortable to Measure the deformations of your Boards and electronic Components to see their behavior if temperature is changing. During the electronic product lifetime the soldering process is the highest thermo mechanical stress. Especially for the lead free reflow peak of more than 240degC some material combinations show a large deformation. But also later in the field at customer side the time to failure is depending from the stress & strain to the product. The differences day/night and operating/standby cause a thermo mechanic cycling and products fail if materials are getting tired and function fails. Beside other processes like diffusion and migration tins thermo mechanical stress can lead to early life time end. So it is important that the thermo-mechanical deformations are minimized and risks are noticed right in time - if possible during prototype stadium - where normally a high pressure of time and a quick measurement technique is welcome. The trend to higher application temperatures (e.g. Automotive sector: engine control) also is a main reason to care about tins land of optimizations. Due to the fact that the electronic board manufacturing in the assembly lines are consisting of many single processes but the components from the different suppliers are not known in regard to their material details and compositions, it's often not possible to start a simulation, which delivers true results, but it's much easier and faster to do a deformation measurement as a function of temperature. Three different measurement techniques (methods) are introduced: Shadow Moire or Interference Technique; Pattern Correlation Technique: Line Projection Technique. Finally some results are shown and examples from Siemens Product optimizations are given (comparison of different board materials/manufacturers, effect of preconditioning (tempering) to the warpage behavior of PBGA. examples of failures & failure modes if stress/strain is too high). Of course the measurement results are used to confirm the FEM results (No FEM without verification) and support DOE. But our experience is, that this methods of the quick measurement of deformations is used mainly as a tool to perform a kind of incoming inspection of delivered supplements like packages and boards. Often a poor thermo mechanical behavior could be proved and any changes of package properties of different date code lots could be recognized. If those male functions are detected before products reach our customers a lot of money (rework) could be saved and products of high thermo mechanical stability with few internal stresses could be delivered to market. The ratio of winning knowledge to examination costs is very high and the deformation measurements are used in all sectors of electronic product manufacturing.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124909509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441489
Zhen-yu Liu
The complete machine interconnection is an important domain of modern electricity interconnection technology, the complete machine wiring is one of the most important processes of entire machine interconnection, the traditional entire machine wiring relies on the manual experience, whose efficiency is low, and the existing computer aided wiring still depend on people to set the route of wire artificially. This article proposed a new three-dimensional space wiring method, firstly, construct the smallest enveloping solid of all modules, and define all of the smallest enveloping solid as wiring barrier, then carry out the shape-based non-grid dividing on the surplus barrier-free space, the A* algorithm combined with dynamic plan were used to search the most superior wiring route between two ports. This method can complete the wiring of electronic complete machine fast and automatically.
{"title":"Research on Wiring Technology of Electronic Complete Machine Interconnection","authors":"Zhen-yu Liu","doi":"10.1109/ICEPT.2007.4441489","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441489","url":null,"abstract":"The complete machine interconnection is an important domain of modern electricity interconnection technology, the complete machine wiring is one of the most important processes of entire machine interconnection, the traditional entire machine wiring relies on the manual experience, whose efficiency is low, and the existing computer aided wiring still depend on people to set the route of wire artificially. This article proposed a new three-dimensional space wiring method, firstly, construct the smallest enveloping solid of all modules, and define all of the smallest enveloping solid as wiring barrier, then carry out the shape-based non-grid dividing on the surplus barrier-free space, the A* algorithm combined with dynamic plan were used to search the most superior wiring route between two ports. This method can complete the wiring of electronic complete machine fast and automatically.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125053068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441380
Ju-Heon Yang, Young-Ho Kim, J. Moon, Won-Jong Lee
A new chip-to-chip interconnection method utilizing mechanical caulking has been developed recently. In this method, bonding between the chips is achieved by deformation-injection of Au stud bump on a chip into the through via hole in the other chip. In this paper, we introduce a modified caulking technology using reflowed Sn bumps instead Au stud bumps since Sn can be deformed more easily than Au. The chip-to-chip interconnection using reflowed Sn bumps and through via hole electrodes was successfully made at room temperature or at 270degC. The contact resistance of the solder joint was less than 35 mOmega per joint.
{"title":"Chip-To-Chip Interconnection by Mechanical Caulking Using Reflowed Sn Bumps","authors":"Ju-Heon Yang, Young-Ho Kim, J. Moon, Won-Jong Lee","doi":"10.1109/ICEPT.2007.4441380","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441380","url":null,"abstract":"A new chip-to-chip interconnection method utilizing mechanical caulking has been developed recently. In this method, bonding between the chips is achieved by deformation-injection of Au stud bump on a chip into the through via hole in the other chip. In this paper, we introduce a modified caulking technology using reflowed Sn bumps instead Au stud bumps since Sn can be deformed more easily than Au. The chip-to-chip interconnection using reflowed Sn bumps and through via hole electrodes was successfully made at room temperature or at 270degC. The contact resistance of the solder joint was less than 35 mOmega per joint.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"42 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126751612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441408
Na Chen, F. Qin, Jianyou Wei
Deformation measurement of solder joints under various loadings such thermal and drop/impact is important in reliability design of electronic packages. It is difficult to use traditional techniques such as strain gage method to measure the strain of solder joints because of their small sizes. Instead, the digital image correlation method (DICM) is applied to catch the deformation of the solder joints. The discrete displacement obtained by the digital image correlation method does not satisfy the deformation compatibility, as a result the error in strain which is calculated by deriving the displacement is enlarged. In order to reduce the error, an approach is proposed in which a continuous displacement field is constructed firstly to fit the discrete measure points by the technique used in the finite element method and the least square method, then the strain is calculated from the continuous displacement field. The results indicate that error in displacement and strain can be significantly reduced by the proposed approach.
{"title":"A Smoothing Algorithm for Strain Measurement by Digital Image Correlation Method","authors":"Na Chen, F. Qin, Jianyou Wei","doi":"10.1109/ICEPT.2007.4441408","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441408","url":null,"abstract":"Deformation measurement of solder joints under various loadings such thermal and drop/impact is important in reliability design of electronic packages. It is difficult to use traditional techniques such as strain gage method to measure the strain of solder joints because of their small sizes. Instead, the digital image correlation method (DICM) is applied to catch the deformation of the solder joints. The discrete displacement obtained by the digital image correlation method does not satisfy the deformation compatibility, as a result the error in strain which is calculated by deriving the displacement is enlarged. In order to reduce the error, an approach is proposed in which a continuous displacement field is constructed firstly to fit the discrete measure points by the technique used in the finite element method and the least square method, then the strain is calculated from the continuous displacement field. The results indicate that error in displacement and strain can be significantly reduced by the proposed approach.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"399 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115218563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441510
X. Gu, Y. Chan, B.Y. Wu, D. Yang
This study employed an electroless Ni-P-carbon nanotubes (Ni-P-CNTs) composite coating as a pad finish for electronic packaging. It aimed at investigating the effect of carbon on the mechanical behavior and microstructure of ball grid array (BGA) solder joints after multiple reflows. Electroless Ni-P and electroless Ni-P-CNTs composite coatings with the same P-content were prepared for comparison. It was found that the carbon in the coating increased the brittleness of solder joints and weakened their shear strength. After shearing tests, more brittle fractures occurred in the intermetallic compound (IMC) layer in the Sn-4Ag-0.5Cu/Ni-P-CNTs (SAC/Ni-P-CNTs) solder joints. After multiple reflows, a Ni3Sn4 IMC layer and a P-rich layer were formed in the solder joints on both coatings. The IMC layers in the SAC/Ni-P solder joints were found to be compact with chunky-shaped grains, whilst the IMC layers in the SAC/Ni-P-CNTs solder joints were porous with needle-shaped grains.
本研究采用化学镀镍- p -碳纳米管(Ni-P-CNTs)复合涂层作为电子封装的衬垫饰面。旨在研究多次回流后碳对球栅阵列(BGA)焊点力学行为和微观结构的影响。制备了相同p含量的化学Ni-P和化学Ni-P- cnts复合镀层进行比较。结果表明，涂层中的碳增加了焊点的脆性，降低了焊点的抗剪强度。剪切试验后，Sn-4Ag-0.5Cu/Ni-P-CNTs (SAC/Ni-P-CNTs)焊点的金属间化合物(IMC)层脆性断裂较多。经过多次回流后，两种涂层的焊点处均形成Ni3Sn4 IMC层和富p层。SAC/Ni-P焊点的IMC层致密，晶粒呈块状，而SAC/Ni-P- cnts焊点的IMC层多孔，晶粒呈针状。
{"title":"Effect of Carbon Inclusion in the Ni-P Coating on Shearing Behavior of Sn4Ag0.5Cu Ball Grid Array Solder Joints","authors":"X. Gu, Y. Chan, B.Y. Wu, D. Yang","doi":"10.1109/ICEPT.2007.4441510","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441510","url":null,"abstract":"This study employed an electroless Ni-P-carbon nanotubes (Ni-P-CNTs) composite coating as a pad finish for electronic packaging. It aimed at investigating the effect of carbon on the mechanical behavior and microstructure of ball grid array (BGA) solder joints after multiple reflows. Electroless Ni-P and electroless Ni-P-CNTs composite coatings with the same P-content were prepared for comparison. It was found that the carbon in the coating increased the brittleness of solder joints and weakened their shear strength. After shearing tests, more brittle fractures occurred in the intermetallic compound (IMC) layer in the Sn-4Ag-0.5Cu/Ni-P-CNTs (SAC/Ni-P-CNTs) solder joints. After multiple reflows, a Ni3Sn4 IMC layer and a P-rich layer were formed in the solder joints on both coatings. The IMC layers in the SAC/Ni-P solder joints were found to be compact with chunky-shaped grains, whilst the IMC layers in the SAC/Ni-P-CNTs solder joints were porous with needle-shaped grains.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441534
P. Shang, Z.Q. Liu, L. Zhang, D.X. Li, J. Shang
The interfacial reaction between eutectic SnBi and Cu was studied by TEM after the sample was reflowed and aged in solid state, respectively. The microstructural evolution at the SnBi/Cu interface during reflowed and solid-state aged process was analyzed. The results show that there are two layers of intermetallic compounds (IMCs), Cu3Sn and Cu6Sn5, located at the interface between solder and Cu after the sample was reflowed. The segregation of Bi at the interface between Cu3Sn and Cu was observed. Furthermore, the segregation of Bi induced the formation of voids at Cu3Sn/Cu interface during solid-state aging process.
{"title":"TEM Study of Bi Segregation in the Interconnect of Eutectic Tin-Bismuth Solder and Copper","authors":"P. Shang, Z.Q. Liu, L. Zhang, D.X. Li, J. Shang","doi":"10.1109/ICEPT.2007.4441534","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441534","url":null,"abstract":"The interfacial reaction between eutectic SnBi and Cu was studied by TEM after the sample was reflowed and aged in solid state, respectively. The microstructural evolution at the SnBi/Cu interface during reflowed and solid-state aged process was analyzed. The results show that there are two layers of intermetallic compounds (IMCs), Cu3Sn and Cu6Sn5, located at the interface between solder and Cu after the sample was reflowed. The segregation of Bi at the interface between Cu3Sn and Cu was observed. Furthermore, the segregation of Bi induced the formation of voids at Cu3Sn/Cu interface during solid-state aging process.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441521
Gaowei Xu, Jian Zhou, L. Luo
The warpage of three-dimensional multi-chip module (3D-MCM) was studied by using viscoplastic finite element (FE) and large strain theory. The results turned out that: it is the existence of the cavity in substrate that results in the double-bow warpage and the inflection point of warpage-versus-temperature curve of substrate: Cavity in the substrate center may decrease the warpage of substrate: Proper usage of underfilling material could strengthen interconnection of device and substrate and could decrease warpage of 3D-MCM. however, the too big CTE of underfilling material may incur other new failure models. Finally the moire fringes measurement validated the simulation and warpage prediction of 3D-MCM.
{"title":"Warpage and Reliability of Three-dimensional Multi-chip Module with High Density Embedded Substrate","authors":"Gaowei Xu, Jian Zhou, L. Luo","doi":"10.1109/ICEPT.2007.4441521","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441521","url":null,"abstract":"The warpage of three-dimensional multi-chip module (3D-MCM) was studied by using viscoplastic finite element (FE) and large strain theory. The results turned out that: it is the existence of the cavity in substrate that results in the double-bow warpage and the inflection point of warpage-versus-temperature curve of substrate: Cavity in the substrate center may decrease the warpage of substrate: Proper usage of underfilling material could strengthen interconnection of device and substrate and could decrease warpage of 3D-MCM. however, the too big CTE of underfilling material may incur other new failure models. Finally the moire fringes measurement validated the simulation and warpage prediction of 3D-MCM.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ICEPT.2007.4441539
Jianlei Tao, Peiyuan Fang, Jiaji Wang
IR Photon Emission Microscopy (IR-PEM) has been widely used in the failure localization of CMOS ICs and its samples include wafer-level samples and packaged devices. For the wafer-level samples, directly observing is possible, while decapsulation must be implemented for the packaged devices. However, due to an increase of the metal interconnection layers in ICs. it is difficult, if not impossible, to obtain the IR emission image from the frontside of the die. Fortunately, silicon shows good transparency to IR. so it is feasible to get the IR emission image from the backside of the chip, which means backside decapsulation and further thinning the silicon substrate of packaged devices are needed. In this paper, procedures and tools of backside decapsulation will be introduced and the usage of IR-PEM in failure localization of the chips will be revealed.
{"title":"Backside IR Photon Emission Microscopy (IR-PEM) Observation in Failure Analysis of the Packaged Devices","authors":"Jianlei Tao, Peiyuan Fang, Jiaji Wang","doi":"10.1109/ICEPT.2007.4441539","DOIUrl":"https://doi.org/10.1109/ICEPT.2007.4441539","url":null,"abstract":"IR Photon Emission Microscopy (IR-PEM) has been widely used in the failure localization of CMOS ICs and its samples include wafer-level samples and packaged devices. For the wafer-level samples, directly observing is possible, while decapsulation must be implemented for the packaged devices. However, due to an increase of the metal interconnection layers in ICs. it is difficult, if not impossible, to obtain the IR emission image from the frontside of the die. Fortunately, silicon shows good transparency to IR. so it is feasible to get the IR emission image from the backside of the chip, which means backside decapsulation and further thinning the silicon substrate of packaged devices are needed. In this paper, procedures and tools of backside decapsulation will be introduced and the usage of IR-PEM in failure localization of the chips will be revealed.","PeriodicalId":325619,"journal":{"name":"2007 8th International Conference on Electronic Packaging Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116823629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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