Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406919
J. Dobes, J. Míchal, Jakub Popp, M. Grábner, F. Vejražka, J. Kákona
Although the major parts of function blocks for the satellite navigation receivers are fully integrated in a CMOS chip in most cases, it is convenient to create an antenna preamplifier as a separate circuit based on a low-noise pHEMT. Such an RF front end can be strongly optimized to attain a trade-off between the noise figure and transducer power gain. Furthermore, as all the principal navigation systems (GPS, GLONASS, Galileo, and Compass) work in similar frequency band (roughly from 1.1 to 1.7 GHz), it is reasonable to create this low-noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multi-objective optimization. First, an extraction of pHEMT model parameters was performed, including comparisons among several models. The extraction was carried out by our original three-step robust identification procedure based on a combination of meta-heuristic and direct optimization methods. Second, a substantial improvement of a standard method for the multi-objective optimization is outlined. Third, the equations of passive elements of the circuit (including transmission lines and T splitters) were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Fourth, an optimal selection of the amplifier operating point and essential passive elements was performed using the previously improved goal attainment method. Finally, the s-parameters and noise figure of the proposed preamplifier were measured, and the third-order intermodulation products were also checked.
{"title":"Multi-objective optimization of a low-noise antenna amplifier for multi-constellation satellite-navigation receivers","authors":"J. Dobes, J. Míchal, Jakub Popp, M. Grábner, F. Vejražka, J. Kákona","doi":"10.1109/SOCC.2015.7406919","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406919","url":null,"abstract":"Although the major parts of function blocks for the satellite navigation receivers are fully integrated in a CMOS chip in most cases, it is convenient to create an antenna preamplifier as a separate circuit based on a low-noise pHEMT. Such an RF front end can be strongly optimized to attain a trade-off between the noise figure and transducer power gain. Furthermore, as all the principal navigation systems (GPS, GLONASS, Galileo, and Compass) work in similar frequency band (roughly from 1.1 to 1.7 GHz), it is reasonable to create this low-noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multi-objective optimization. First, an extraction of pHEMT model parameters was performed, including comparisons among several models. The extraction was carried out by our original three-step robust identification procedure based on a combination of meta-heuristic and direct optimization methods. Second, a substantial improvement of a standard method for the multi-objective optimization is outlined. Third, the equations of passive elements of the circuit (including transmission lines and T splitters) were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Fourth, an optimal selection of the amplifier operating point and essential passive elements was performed using the previously improved goal attainment method. Finally, the s-parameters and noise figure of the proposed preamplifier were measured, and the third-order intermodulation products were also checked.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131855865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406889
Guanyu Sun
In order to mitigate the problem of “memory wall”, various emerging non-volatile memory (NVM) technologies have been proposed to replace traditional ones. These emerging NVMs include STT-RAM, PCRAM, RRAM, RM, etc. Compared to traditional memory technologies, they have advantages of near-zero standby-power, high storage density, and non-volatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into traditional memory hierarchy. On the other hand, the unique features of these NVMs enable new memory architectures in memory subsystem and also induce new challenges to be solved at the same time. In this tutorial, we first briefly review device level background of these emerging NVMs. Then, we introduce the tool NVMSim for their circuit level modeling. At last, we investigate their implication for memory architecture design.
{"title":"Session T4B: Tutorial: Emerging non-volatile memory: Device, circuit, and architecture","authors":"Guanyu Sun","doi":"10.1109/SOCC.2015.7406889","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406889","url":null,"abstract":"In order to mitigate the problem of “memory wall”, various emerging non-volatile memory (NVM) technologies have been proposed to replace traditional ones. These emerging NVMs include STT-RAM, PCRAM, RRAM, RM, etc. Compared to traditional memory technologies, they have advantages of near-zero standby-power, high storage density, and non-volatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into traditional memory hierarchy. On the other hand, the unique features of these NVMs enable new memory architectures in memory subsystem and also induce new challenges to be solved at the same time. In this tutorial, we first briefly review device level background of these emerging NVMs. Then, we introduce the tool NVMSim for their circuit level modeling. At last, we investigate their implication for memory architecture design.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134003594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406927
Jian Hu, Tun Li, Sikun Li
The growing complexity of digital designs makes it harder to discover inconsistency between system level model (SLM) and register transfer level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. Finite State Machines with Data Paths (FSMD) based equivalence checking method is widely used in checking the equivalence between system level and RT level designs. The designs without mapping information can not be handled by many formal methods. Deep state sequences (DSS) based equivalence checking method is one of the state of the art FSMD-based methods that can handle designs without mapping information. DSS is the state sequence from start state to final state of FSMD without repeated paths. It proves the equivalence between SLM and RTL by comparing all the DSS-pairs of FSMDs in SLM and RTL. However the previous proposed DSS-based methods compared all the DSS-pairs blindly, which wasted most verification efforts on useless comparisons. This paper proposes a method to improve the DSS-based equivalence checking method by separating and comparing the corresponding potential equivalent DSS-pairs from all the generated paths to avoid blind comparisons. The promising experimental results show that the proposed method can improve the efficiency of DSS-based equivalence checking method.
{"title":"Formal equivalence checking between SLM and RTL descriptions","authors":"Jian Hu, Tun Li, Sikun Li","doi":"10.1109/SOCC.2015.7406927","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406927","url":null,"abstract":"The growing complexity of digital designs makes it harder to discover inconsistency between system level model (SLM) and register transfer level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. Finite State Machines with Data Paths (FSMD) based equivalence checking method is widely used in checking the equivalence between system level and RT level designs. The designs without mapping information can not be handled by many formal methods. Deep state sequences (DSS) based equivalence checking method is one of the state of the art FSMD-based methods that can handle designs without mapping information. DSS is the state sequence from start state to final state of FSMD without repeated paths. It proves the equivalence between SLM and RTL by comparing all the DSS-pairs of FSMDs in SLM and RTL. However the previous proposed DSS-based methods compared all the DSS-pairs blindly, which wasted most verification efforts on useless comparisons. This paper proposes a method to improve the DSS-based equivalence checking method by separating and comparing the corresponding potential equivalent DSS-pairs from all the generated paths to avoid blind comparisons. The promising experimental results show that the proposed method can improve the efficiency of DSS-based equivalence checking method.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132652454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406910
Yue Zhao, Hosoon Shin, Hai-Bao Chen, S. Tan, G. Shi, Xin Li
In this paper, we propose a new efficient statistical method for failure probability estimation of analog circuits with rate failure events, which is a time-consuming process using the existing Monte Carlo method. On top of this, the new method can also provide the estimation of parameter regions to achieve targeted performance to facilitate the design process, which is missing in the traditional fast statistical methods such as the statistical blockage based method. The new method employs two new techniques to speed up the analysis. First, to reduce the large number of samples for rare event analysis, the new approach employs a smart sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce an additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the new approach identifies the failure regions in terms of parameters to provide a good design guideline for designers and optimization tools. This is enabled by applying the variance based feature selection to find the dominant parameters. A quasi-random sampling with dominant parameters is then applied to determine in-spec boundaries of those parameters. In addition, we also provide the complete formula for the probability determinations of failure regions in the iterative failure region searching framework. We demonstrate the advantage of our proposed method using two test benches: 6T-SRAM reading failure diagnosis with 27 process parameters, charge pump operation failure diagnosis in a PLL circuit with 81 process parameters. Experimental results show that the new method can be 4X more accurate than the recently proposed REscope method. Furthermore, the new method reduces the simulation cost by 2X than the recursive statistical blockage (RSB) method with same accuracy level. Our approach also provides the precise guidance of diverse parameters with 1.21% estimation error.
{"title":"Statistical rare event analysis using smart sampling and parameter guidance","authors":"Yue Zhao, Hosoon Shin, Hai-Bao Chen, S. Tan, G. Shi, Xin Li","doi":"10.1109/SOCC.2015.7406910","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406910","url":null,"abstract":"In this paper, we propose a new efficient statistical method for failure probability estimation of analog circuits with rate failure events, which is a time-consuming process using the existing Monte Carlo method. On top of this, the new method can also provide the estimation of parameter regions to achieve targeted performance to facilitate the design process, which is missing in the traditional fast statistical methods such as the statistical blockage based method. The new method employs two new techniques to speed up the analysis. First, to reduce the large number of samples for rare event analysis, the new approach employs a smart sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce an additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the new approach identifies the failure regions in terms of parameters to provide a good design guideline for designers and optimization tools. This is enabled by applying the variance based feature selection to find the dominant parameters. A quasi-random sampling with dominant parameters is then applied to determine in-spec boundaries of those parameters. In addition, we also provide the complete formula for the probability determinations of failure regions in the iterative failure region searching framework. We demonstrate the advantage of our proposed method using two test benches: 6T-SRAM reading failure diagnosis with 27 process parameters, charge pump operation failure diagnosis in a PLL circuit with 81 process parameters. Experimental results show that the new method can be 4X more accurate than the recently proposed REscope method. Furthermore, the new method reduces the simulation cost by 2X than the recursive statistical blockage (RSB) method with same accuracy level. Our approach also provides the precise guidance of diverse parameters with 1.21% estimation error.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122730503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406936
R. Santos, Renan Marks, Rafael Alves, Felipe Araujo, Renato Santos
This work presents the design of hardware instruction decoders based on the Pattern Based Instruction Word (PBIW) encoding technique. Instruction decoder circuits have been designed in the datapath of ρ-VEX and the Leon3 soft-core embedded processors. The PBIW encoding scheme focuses on extracting out patterns from original instructions at compiler time. The PBIW hardware decoder works on the processor datapath simplifying the decoding instruction logic by exploring the hardware parallelism between instruction decoding and register read. The experiments show that the instruction decoders based on the PBIW technique present small impacts on area, dynamic power, and timing (3%-10% decrease on clock frequency) on the processor design.
{"title":"Instruction decoders based on pattern factorization","authors":"R. Santos, Renan Marks, Rafael Alves, Felipe Araujo, Renato Santos","doi":"10.1109/SOCC.2015.7406936","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406936","url":null,"abstract":"This work presents the design of hardware instruction decoders based on the Pattern Based Instruction Word (PBIW) encoding technique. Instruction decoder circuits have been designed in the datapath of ρ-VEX and the Leon3 soft-core embedded processors. The PBIW encoding scheme focuses on extracting out patterns from original instructions at compiler time. The PBIW hardware decoder works on the processor datapath simplifying the decoding instruction logic by exploring the hardware parallelism between instruction decoding and register read. The experiments show that the instruction decoders based on the PBIW technique present small impacts on area, dynamic power, and timing (3%-10% decrease on clock frequency) on the processor design.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"566 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406922
Gaurav Narang, Alexander Fell, P. Gupta, Anuj Grover
Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells depending on the timing and the power constraints, optimal memory selection is largely a manual process. We propose a framework to optimize power, performance, and area (PPA) of a memory subsystem (MSS) by including floorplan dependent delays and power consumption in interconnects and glue logic of the MSS in the pre-RTL stage. Through this framework, we demonstrate that for a 4 Mb assembly of SRAM instances, dynamic power is reduced by 44%, area by 49%, and leakage by 71% with the floorplan aware selection. The framework has the capability to use different estimates, when routing congestion is important (for example, in low cost processes with less number of metal layers). We also show that the interconnect delays are reduced by about 68% and dynamic power by 58%, if additional metal layers are available for routing compared to a low cost 6 metal process.
{"title":"Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems","authors":"Gaurav Narang, Alexander Fell, P. Gupta, Anuj Grover","doi":"10.1109/SOCC.2015.7406922","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406922","url":null,"abstract":"Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells depending on the timing and the power constraints, optimal memory selection is largely a manual process. We propose a framework to optimize power, performance, and area (PPA) of a memory subsystem (MSS) by including floorplan dependent delays and power consumption in interconnects and glue logic of the MSS in the pre-RTL stage. Through this framework, we demonstrate that for a 4 Mb assembly of SRAM instances, dynamic power is reduced by 44%, area by 49%, and leakage by 71% with the floorplan aware selection. The framework has the capability to use different estimates, when routing congestion is important (for example, in low cost processes with less number of metal layers). We also show that the interconnect delays are reduced by about 68% and dynamic power by 58%, if additional metal layers are available for routing compared to a low cost 6 metal process.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131522394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406935
Han Zhou, Xiaoyan Gui, Peng Gao
A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed in this paper. The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling capacitor is adopted to improve the precision and reduce the chip area. Through the optimization of placement and routing, the DAC achieves high precision. Besides, a multi-stage comparator is designed, and an offset calibration technique with capacitors is applied, too. The measurement results show that the effective number of bits (ENOB) of this ADC reaches 9.711 bit at Nyquist frequency with 0.83 MHz sampling frequency and the total current of the ADC is 970 μA with a 3.3 V power supply.
{"title":"Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC","authors":"Han Zhou, Xiaoyan Gui, Peng Gao","doi":"10.1109/SOCC.2015.7406935","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406935","url":null,"abstract":"A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed in this paper. The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling capacitor is adopted to improve the precision and reduce the chip area. Through the optimization of placement and routing, the DAC achieves high precision. Besides, a multi-stage comparator is designed, and an offset calibration technique with capacitors is applied, too. The measurement results show that the effective number of bits (ENOB) of this ADC reaches 9.711 bit at Nyquist frequency with 0.83 MHz sampling frequency and the total current of the ADC is 970 μA with a 3.3 V power supply.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131803235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406893
J. Cong
Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the UCLA Computer Science Department and the director of Center for Domain-Specific Computing (CDSC). He served as the department chair from 2005 to 2008. Dr. Cong's research interests include synthesis of VLSI circuits and systems, energy-efficient computer architectures, reconfigurable systems, nanotechnology and systems, and highly scalable algorithms. He has over 400 publications in these areas, including 10 best paper awards, and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System Society Technical Achievement Award “For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation.”
Jason Cong, 1985年获得北京大学计算机科学学士学位，1987年和1990年分别获得伊利诺伊大学厄巴纳-香槟分校计算机科学硕士和博士学位。目前，他是加州大学洛杉矶分校计算机科学系的校长教授和特定领域计算中心(CDSC)主任。2005年至2008年担任系主任。他的研究兴趣包括VLSI电路和系统的合成，节能计算机架构，可重构系统，纳米技术和系统，以及高度可扩展的算法。他在这些领域发表了400多篇论文，其中包括10篇最佳论文奖，以及2011年ACM/IEEE A.理查德牛顿电气设计自动化技术影响奖。2000年当选为IEEE Fellow, 2008年当选为ACM Fellow。他是2010年IEEE电路与系统学会技术成就奖的获得者，因为他对电子设计自动化的开创性贡献，特别是在FPGA合成、VLSI互连优化和物理设计自动化方面。
{"title":"\"High-level synthesis and beyond - From datacenters to IoTs\"","authors":"J. Cong","doi":"10.1109/SOCC.2015.7406893","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406893","url":null,"abstract":"Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the UCLA Computer Science Department and the director of Center for Domain-Specific Computing (CDSC). He served as the department chair from 2005 to 2008. Dr. Cong's research interests include synthesis of VLSI circuits and systems, energy-efficient computer architectures, reconfigurable systems, nanotechnology and systems, and highly scalable algorithms. He has over 400 publications in these areas, including 10 best paper awards, and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System Society Technical Achievement Award “For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation.”","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132134731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406907
Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, S. Jou, Sau-Gee Chen
This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.
{"title":"A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems","authors":"Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, S. Jou, Sau-Gee Chen","doi":"10.1109/SOCC.2015.7406907","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406907","url":null,"abstract":"This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock technology is one of the four fundamental technologies in the field of IC design. It is the timekeeper and the driver of everything inside a silicon chip. Time-Average-Frequency Direct Period Synthesis is an emerging technology in the field of on-chip frequency synthesis (clock generation). It comprises a new concept, a rigorous mathematical theory, and a novel circuit architecture. Its aim is the two long-lasting problems in this field: arbitrary frequency generation and instantaneous frequency switching. The goal is to achieve these two features on-a-chip simultaneously and at a reasonable cost so that SoC chip architects have a powerful clock generator in their hands to create their innovations at higher levels. It is a component-level enabler for chip-system-architecture level innovations. On a large scale, since clock is omnipresent in electronic system, this technology introduces a paradigm shift in electronic system design. In this tutorial, the Time-Average-Frequency concept will be explained. The circuit architecture will be briefly reviewed. Its impact, the route from component-level enabler to system level innovations, will be illustrated through real application examples. The newly published book in May 2015: “From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic System (IEEE Press Series on Microelectronic Systems)” will be provided to each tutorial attendant.
{"title":"Session T3A: Tutorial: From frequency to time-average-frequency: A paradigm shift in the design of electronic systems","authors":"Liming Xiu","doi":"10.1002/9781119102175","DOIUrl":"https://doi.org/10.1002/9781119102175","url":null,"abstract":"Clock technology is one of the four fundamental technologies in the field of IC design. It is the timekeeper and the driver of everything inside a silicon chip. Time-Average-Frequency Direct Period Synthesis is an emerging technology in the field of on-chip frequency synthesis (clock generation). It comprises a new concept, a rigorous mathematical theory, and a novel circuit architecture. Its aim is the two long-lasting problems in this field: arbitrary frequency generation and instantaneous frequency switching. The goal is to achieve these two features on-a-chip simultaneously and at a reasonable cost so that SoC chip architects have a powerful clock generator in their hands to create their innovations at higher levels. It is a component-level enabler for chip-system-architecture level innovations. On a large scale, since clock is omnipresent in electronic system, this technology introduces a paradigm shift in electronic system design. In this tutorial, the Time-Average-Frequency concept will be explained. The circuit architecture will be briefly reviewed. Its impact, the route from component-level enabler to system level innovations, will be illustrated through real application examples. The newly published book in May 2015: “From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic System (IEEE Press Series on Microelectronic Systems)” will be provided to each tutorial attendant.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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