Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406995
Na Bao, Zhe Jiang, Zhiheng Qi, Wei Zhang
This paper proposed a high throughput MQ encoder for pass-parallel EBCOT. Proposed MQ encoder can encode CX-D pairs from mixed three passes. A new extended probability estimation table (PET) is proposed. By looking up to the PET, register A can get the total shift times during renormalization. A pipelined auxiliary unit is also used in BYTEOUT procedure to minimize the critical path. Proposed MQ encoder can encode one symbol per clock cycle. It is implemented on a Xilinx FPGA and is capable of operating at 139.09MHz. It can achieve a throughput of 139.09Msymbols/sec.
{"title":"High-throughput MQ encoder for pass-parallel EBCOT in JPEG2000","authors":"Na Bao, Zhe Jiang, Zhiheng Qi, Wei Zhang","doi":"10.1109/SOCC.2015.7406995","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406995","url":null,"abstract":"This paper proposed a high throughput MQ encoder for pass-parallel EBCOT. Proposed MQ encoder can encode CX-D pairs from mixed three passes. A new extended probability estimation table (PET) is proposed. By looking up to the PET, register A can get the total shift times during renormalization. A pipelined auxiliary unit is also used in BYTEOUT procedure to minimize the critical path. Proposed MQ encoder can encode one symbol per clock cycle. It is implemented on a Xilinx FPGA and is capable of operating at 139.09MHz. It can achieve a throughput of 139.09Msymbols/sec.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130460190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406967
Soumyajit Poddar, P. Ghosal, H. Rahaman
Networks on Chip (NoC) are a scalable solution to the growing problem of multicore data communication. One of the major challenges in multicore NoCs is that the redundant multicast invalidations can easily increase the load on communication resources cumulatively and lower the overall performance of the chip. In this paper we propose a novel technique to minimize the number of redundant invalidations. Moreover, Silicon-photonics is applied in NoC to lower the energy-delay product. Performance results show 15% improvement over an electrical mesh NoC and 13% improvements over a state of the art photonic NoC.
{"title":"Adaptive CDMA based multicast method for photonic networks on chip","authors":"Soumyajit Poddar, P. Ghosal, H. Rahaman","doi":"10.1109/SOCC.2015.7406967","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406967","url":null,"abstract":"Networks on Chip (NoC) are a scalable solution to the growing problem of multicore data communication. One of the major challenges in multicore NoCs is that the redundant multicast invalidations can easily increase the load on communication resources cumulatively and lower the overall performance of the chip. In this paper we propose a novel technique to minimize the number of redundant invalidations. Moreover, Silicon-photonics is applied in NoC to lower the energy-delay product. Performance results show 15% improvement over an electrical mesh NoC and 13% improvements over a state of the art photonic NoC.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406993
Jingyan Fu, L. Hou, Jinhui Wang, Bo Lu, Wei Zhao, Yang Yang
Although thermal-aware TSV (Through Silicon Via) cluster's behavior has been studied extensively, the structure of TSV cluster, which is also important to thermal problem in 3D IC (Three Dimensional Integrate Circuit), is ignored. In this paper, a novel structure of TSV cluster is proposed to improve the thermal performance of 3D IC. Models have been established to study the effect of TSV cluster's structure on thermal performance in 3D IC. Simulation results show that the proposed TSV cluster's structure improves the thermal performance of 3D IC, which can help to alleviate the thermal problem.
{"title":"A novel thermal-aware structure of TSV cluster","authors":"Jingyan Fu, L. Hou, Jinhui Wang, Bo Lu, Wei Zhao, Yang Yang","doi":"10.1109/SOCC.2015.7406993","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406993","url":null,"abstract":"Although thermal-aware TSV (Through Silicon Via) cluster's behavior has been studied extensively, the structure of TSV cluster, which is also important to thermal problem in 3D IC (Three Dimensional Integrate Circuit), is ignored. In this paper, a novel structure of TSV cluster is proposed to improve the thermal performance of 3D IC. Models have been established to study the effect of TSV cluster's structure on thermal performance in 3D IC. Simulation results show that the proposed TSV cluster's structure improves the thermal performance of 3D IC, which can help to alleviate the thermal problem.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406913
Yanjie Gu, G. Shi
In modern systems-on-chip (SOC) technology analog modules are costly to design. This paper studies an optimal realization of switched-capacitor (SC) circuit given a transfer function (TF) in the z-domain. Among the multiple possibilities of capacitance assignments, the proposed method is more controllable in arriving at a desirable SC realization. The underlying technique applies a symbolic method to derive a cancellation-free symbolic representation for a given SC circuit topology, then uses the automatically generated symbolic coefficient expressions to synthesize a set of numerical capacitance values suitable for physical implementation. Examples demonstrate the effectiveness of the proposal.
{"title":"Optimal realization of switched-capacitor circuits by symbolic analysis","authors":"Yanjie Gu, G. Shi","doi":"10.1109/SOCC.2015.7406913","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406913","url":null,"abstract":"In modern systems-on-chip (SOC) technology analog modules are costly to design. This paper studies an optimal realization of switched-capacitor (SC) circuit given a transfer function (TF) in the z-domain. Among the multiple possibilities of capacitance assignments, the proposed method is more controllable in arriving at a desirable SC realization. The underlying technique applies a symbolic method to derive a cancellation-free symbolic representation for a given SC circuit topology, then uses the automatically generated symbolic coefficient expressions to synthesize a set of numerical capacitance values suitable for physical implementation. Examples demonstrate the effectiveness of the proposal.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116277962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406903
Ting-Li Chu, W. Chu, Yasuyoshi Fujii, Chorng-Sii Hwang
This paper presents a deskew buffer using a hybrid control scheme to reduce the locking time. The function of duty cycle correction is provided as well to meet the common requirement of the digital system clock. With the aid of time-to-digital converter and successive approximation register schemes, the proposed circuit can speed up the locking process. It is designed and implemented in TSMC 0.18-μm CMOS process to validate its feasibility with low power consumption. The core circuitry occupies an area of 0.13 mm2. The simulated results shows that the input clock rate is within 115~385 MHz with the duty cycle range of 15~85%. It can also perform the deskewing function in a closed-loop manner against the PVT variation.
{"title":"All-digital deskew buffer using a hybrid control scheme","authors":"Ting-Li Chu, W. Chu, Yasuyoshi Fujii, Chorng-Sii Hwang","doi":"10.1109/SOCC.2015.7406903","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406903","url":null,"abstract":"This paper presents a deskew buffer using a hybrid control scheme to reduce the locking time. The function of duty cycle correction is provided as well to meet the common requirement of the digital system clock. With the aid of time-to-digital converter and successive approximation register schemes, the proposed circuit can speed up the locking process. It is designed and implemented in TSMC 0.18-μm CMOS process to validate its feasibility with low power consumption. The core circuitry occupies an area of 0.13 mm2. The simulated results shows that the input clock rate is within 115~385 MHz with the duty cycle range of 15~85%. It can also perform the deskewing function in a closed-loop manner against the PVT variation.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124803720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406972
Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev K. Jain
A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.
{"title":"A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology","authors":"Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev K. Jain","doi":"10.1109/SOCC.2015.7406972","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406972","url":null,"abstract":"A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125571323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406960
Koki Ito, Y. Tamiya, M. Yanagisawa, N. Togawa
As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B - 1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.
从TCP/IP卸载引擎的数据包分析和视频/音频数据的流数据处理中可以看出，有必要从批量数据中提取特定的数据字段，我们可以使用字段数据提取器。特别是，(M, N)字段数据提取器通过使用多路复用器连接其输入/输出，从M字节寄存器中读出任意连续的N字节。然而，随着输入/输出字节长度的增加，所需的多路复用器的数量也会增加太多。如何减少其所需的多路复用器的数量是一个主要的挑战。本文针对(M, N)场数据提取器提出了一种高效的多路复用网络综合方法。我们的方法是基于在多路复用网络中插入一个(N + B - 1)字节的虚拟中间寄存器，并将其划分为上层网络和下层网络。该方法在不增加多路复用器网络深度的情况下，理论上减少了多路复用器的数量。我们还提出了如何确定虚拟中间寄存器的大小，以最大限度地减少所需多路复用器的数量。实验结果表明，与使用朴素多路复用网络的方法相比，我们的方法减少了实现现场数据提取所需的门数，最多减少了92%。
{"title":"Partitioning-based multiplexer network synthesis for field-data extractors","authors":"Koki Ito, Y. Tamiya, M. Yanagisawa, N. Togawa","doi":"10.1109/SOCC.2015.7406960","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406960","url":null,"abstract":"As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B - 1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406962
Limin Xiao, Zhenxue He, Li Ruan, Rong Zhang, Tongsheng Xia, Xiang Wang
At present, although genetic algorithm (GA) is widely used in best polarity searching of MPRM logic circuit, there are few literatures pay attention to the polarity conversion sequence of the polarity set waiting for evaluation. An improved best polarity searching approach (IBPSA) based on GA is presented to optimize the polarity conversion sequence of polarity set and speed up the best polarity searching of MPRM logic circuits. In addition, we present an improved nearest neighbor (INN) to obtain the best polarity conversion sequence of the polarity set waiting for evaluation in each generation of GA and apply elitism strategy to IBPSA to guarantee its global convergence. Our proposed IBPSA is implemented in C and a comparative analysis has been presented for MCNC benchmark circuits. The experimental results show that the IBPSA can greatly reduce the time of best polarity searching of MPRM logic circuits compared to the approaches neglecting polarity conversion sequence.
{"title":"Optimization of best polarity searching for mixed polarity reed-muller logic circuit","authors":"Limin Xiao, Zhenxue He, Li Ruan, Rong Zhang, Tongsheng Xia, Xiang Wang","doi":"10.1109/SOCC.2015.7406962","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406962","url":null,"abstract":"At present, although genetic algorithm (GA) is widely used in best polarity searching of MPRM logic circuit, there are few literatures pay attention to the polarity conversion sequence of the polarity set waiting for evaluation. An improved best polarity searching approach (IBPSA) based on GA is presented to optimize the polarity conversion sequence of polarity set and speed up the best polarity searching of MPRM logic circuits. In addition, we present an improved nearest neighbor (INN) to obtain the best polarity conversion sequence of the polarity set waiting for evaluation in each generation of GA and apply elitism strategy to IBPSA to guarantee its global convergence. Our proposed IBPSA is implemented in C and a comparative analysis has been presented for MCNC benchmark circuits. The experimental results show that the IBPSA can greatly reduce the time of best polarity searching of MPRM logic circuits compared to the approaches neglecting polarity conversion sequence.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406908
N. Gupta, A. Kumar, A. Dutta, S. Singh
This paper presents a wideband (WB) reconfigurable down-conversion mixer for multi-standard wireless receivers. The proposed mixer is re-configurable between active mixer and passive mixer modes. Reconfigurability is made through switching the input signal between gate and source terminal of input transistors and enabling/disabling the transimpedance stage at the output. The CMOS transmission gate (TG) switches are designed to provide optimum headroom in this low voltage design. The proposed circuit is designed in UMC 65nm RFCMOS technology with 1.2V supply voltage. From the simulation results, the proposed circuit shows conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.6 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. Hence this circuit will be much helpful in multi-standard receiver design in IoT perspective.
{"title":"A 1.2V wide-band reconfigurable mixer for wireless application in 65nm CMOS technology","authors":"N. Gupta, A. Kumar, A. Dutta, S. Singh","doi":"10.1109/SOCC.2015.7406908","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406908","url":null,"abstract":"This paper presents a wideband (WB) reconfigurable down-conversion mixer for multi-standard wireless receivers. The proposed mixer is re-configurable between active mixer and passive mixer modes. Reconfigurability is made through switching the input signal between gate and source terminal of input transistors and enabling/disabling the transimpedance stage at the output. The CMOS transmission gate (TG) switches are designed to provide optimum headroom in this low voltage design. The proposed circuit is designed in UMC 65nm RFCMOS technology with 1.2V supply voltage. From the simulation results, the proposed circuit shows conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.6 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. Hence this circuit will be much helpful in multi-standard receiver design in IoT perspective.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121421937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406959
Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang
Prior works have demonstrated opportunities for achieving more minimized combinational circuits by introducing combinational loops during the synthesis. However, they achieved this by using a branch-and-bound technique to explore possible cyclic dependencies of circuits, which may not scale well for complex designs. Instead of using exploration, this paper proposes a formal algorithm using logic implication to identify cyclifiable structure candidates directly, or to create them aggressively in circuits. Additionally, we also propose a SAT-based algorithm to validate whether the formed loops are combinational or not. The effectiveness and scalability of the identification and validation algorithms are demonstrated in the experimental results performed on a set of IWLS 2005 benchmarks. As compared to the state-of-the-art algorithm, our validation algorithm produces speedups ranging from 2 to 2350 times.
{"title":"Synthesis and verification of cyclic combinational circuits","authors":"Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang","doi":"10.1109/SOCC.2015.7406959","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406959","url":null,"abstract":"Prior works have demonstrated opportunities for achieving more minimized combinational circuits by introducing combinational loops during the synthesis. However, they achieved this by using a branch-and-bound technique to explore possible cyclic dependencies of circuits, which may not scale well for complex designs. Instead of using exploration, this paper proposes a formal algorithm using logic implication to identify cyclifiable structure candidates directly, or to create them aggressively in circuits. Additionally, we also propose a SAT-based algorithm to validate whether the formed loops are combinational or not. The effectiveness and scalability of the identification and validation algorithms are demonstrated in the experimental results performed on a set of IWLS 2005 benchmarks. As compared to the state-of-the-art algorithm, our validation algorithm produces speedups ranging from 2 to 2350 times.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":" 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132157748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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