Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890090
J. Miller, M. Khazhinsky, J. Weldon
The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.
{"title":"Engineering the cascoded NMOS output buffer for maximum V/sub t1/","authors":"J. Miller, M. Khazhinsky, J. Weldon","doi":"10.1109/EOSESD.2000.890090","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890090","url":null,"abstract":"The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890109
Chang-Su Kim, Hong-bae Park, Bung-Gwan Kim, D. Kang, Myoung-Goo Lee, Siwon Lee, Chan-Hee Jeon, Wan-Gu Kim, Young-Jae Yoo, H. Yoon
The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).
{"title":"A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process","authors":"Chang-Su Kim, Hong-bae Park, Bung-Gwan Kim, D. Kang, Myoung-Goo Lee, Siwon Lee, Chan-Hee Jeon, Wan-Gu Kim, Young-Jae Yoo, H. Yoon","doi":"10.1109/EOSESD.2000.890109","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890109","url":null,"abstract":"The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134105980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890097
L. G. Henry, A. Wallash
This paper presents the results of work being considered by the IDEMA ESD Standards Working Group to develop a standard for the ESD stress testing, measurement and evaluation of the ESD susceptibility and sensitivity of magnetoresistive recording (MR) heads. No ESD standard presently exists for MR heads.
{"title":"Considerations for an HBM ESD standard for measuring and testing of magneto resistive heads","authors":"L. G. Henry, A. Wallash","doi":"10.1109/EOSESD.2000.890097","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890097","url":null,"abstract":"This paper presents the results of work being considered by the IDEMA ESD Standards Working Group to develop a standard for the ESD stress testing, measurement and evaluation of the ESD susceptibility and sensitivity of magnetoresistive recording (MR) heads. No ESD standard presently exists for MR heads.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890040
T. Lesniewski, K. Yates
Measurements were done on nearly 90 products to determine their cleanliness and ESD protective properties. Categories of materials tested include floor tiles and mats, gloves, finger cots, bags and sheeting materials, garments, swabs and wipes. A variety of test methods was used to evaluate the materials. The results showed that few products had both nonvolatile residue less than 1 mg/ft/sup 2/ and static dissipative properties.
{"title":"Evaluation of materials used in cleanrooms with ESD sensitive hardware","authors":"T. Lesniewski, K. Yates","doi":"10.1109/EOSESD.2000.890040","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890040","url":null,"abstract":"Measurements were done on nearly 90 products to determine their cleanliness and ESD protective properties. Categories of materials tested include floor tiles and mats, gloves, finger cots, bags and sheeting materials, garments, swabs and wipes. A variety of test methods was used to evaluate the materials. The results showed that few products had both nonvolatile residue less than 1 mg/ft/sup 2/ and static dissipative properties.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890021
K. Yokoi, T. Watanabe
This paper describes the possibility of performing the human body model (HBM) and machine model (MM) tests on a wafer. HBM capability when performed on a wafer is almost identical to that of a package; however, MM capability performed on a wafer is almost double that of a package due to the degradation of ESD pulses by parasitics in the equipment.
{"title":"A study of wafer level ESD testing","authors":"K. Yokoi, T. Watanabe","doi":"10.1109/EOSESD.2000.890021","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890021","url":null,"abstract":"This paper describes the possibility of performing the human body model (HBM) and machine model (MM) tests on a wafer. HBM capability when performed on a wafer is almost identical to that of a package; however, MM capability performed on a wafer is almost double that of a package due to the degradation of ESD pulses by parasitics in the equipment.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117020412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890086
Tai-Ho Wang, M. Ker
A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.
{"title":"On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application","authors":"Tai-Ho Wang, M. Ker","doi":"10.1109/EOSESD.2000.890086","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890086","url":null,"abstract":"A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127653376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890085
H. Koizumi, Y. Komine, Y. Ohtomo, M. Shimaya
The effect of a tungsten (W) clad source/drain on the electrostatic discharge (ESD) protection in fully-depleted CMOS/SIMOX devices was studied. The ESD failure voltage based on the human-body model (HBM) in a CMOS input circuit was measured for three types of clad W-layer layouts. High ESD immunity of 4000 V was obtained for the fully-W-clad layout when the threshold voltage was less than 0.24 V and the threshold voltage dependence was observed. The blocked layout of the clad W layer provided an ESD protection level of over 3500 V at varied threshold voltages. A gapped W-layer layout provided 3000 V level immunity while keeping the resistance of the gate electrode low for high-speed operation in the output buffer. Based on these results, an optimized layout for the W layer in fully-depleted SOI technology is presented.
{"title":"ESD protection in fully-depleted CMOS/SIMOX with a tungsten-clad source/drain","authors":"H. Koizumi, Y. Komine, Y. Ohtomo, M. Shimaya","doi":"10.1109/EOSESD.2000.890085","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890085","url":null,"abstract":"The effect of a tungsten (W) clad source/drain on the electrostatic discharge (ESD) protection in fully-depleted CMOS/SIMOX devices was studied. The ESD failure voltage based on the human-body model (HBM) in a CMOS input circuit was measured for three types of clad W-layer layouts. High ESD immunity of 4000 V was obtained for the fully-W-clad layout when the threshold voltage was less than 0.24 V and the threshold voltage dependence was observed. The blocked layout of the clad W layer provided an ESD protection level of over 3500 V at varied threshold voltages. A gapped W-layer layout provided 3000 V level immunity while keeping the resistance of the gate electrode low for high-speed operation in the output buffer. Based on these results, an optimized layout for the W layer in fully-depleted SOI technology is presented.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124825596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890041
E. Granstrom, N. Tabat
Patterned giant magnetoresistance (GMR) films resembling shield-less sensors with varying sizes have been subjected to simulated ESD. As sensor width decreases, the failure voltage for a modified human body model (150 /spl Omega/, 150 pF) passes through a minimum before sharply increasing for narrowest devices. In contrast to adiabatic predictions, smaller width devices (<0.75 /spl mu/m) become more robust to ESD due to the thermal conductance of the sensor contacts. These results should extend to GMR heads, and suggest that for longer ESD events, changes in sensor width for higher areal density recording may partially mitigate the trend towards greater ESD sensitivity.
{"title":"Limitations of the adiabatic model for ESD failure in GMR structures","authors":"E. Granstrom, N. Tabat","doi":"10.1109/EOSESD.2000.890041","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890041","url":null,"abstract":"Patterned giant magnetoresistance (GMR) films resembling shield-less sensors with varying sizes have been subjected to simulated ESD. As sensor width decreases, the failure voltage for a modified human body model (150 /spl Omega/, 150 pF) passes through a minimum before sharply increasing for narrowest devices. In contrast to adiabatic predictions, smaller width devices (<0.75 /spl mu/m) become more robust to ESD due to the thermal conductance of the sensor contacts. These results should extend to GMR heads, and suggest that for longer ESD events, changes in sensor width for higher areal density recording may partially mitigate the trend towards greater ESD sensitivity.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890044
H. Snyder, A. Wallash
This paper summarizes a study of various methods to eliminate metal contact between the inputs of a GMR head and metal tooling by using static dissipative materials. Peak discharge currents to ground were measured for a variety of materials.
{"title":"A study of methods to eliminate metal contact in GMR head manufacturing","authors":"H. Snyder, A. Wallash","doi":"10.1109/EOSESD.2000.890044","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890044","url":null,"abstract":"This paper summarizes a study of various methods to eliminate metal contact between the inputs of a GMR head and metal tooling by using static dissipative materials. Peak discharge currents to ground were measured for a variety of materials.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132072942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890048
D. Vickers, D. Carradero
This paper presents the results of investigations into tribocharging and ESD effects of CO/sub 2/ snow jet cleaning on magnetic recording components for hard disk drives. The studies are performed at different levels of integration, including component parts, head gimbal assembly (HGA) and head stack assembly. The electrical stresses induced during the cleaning process are evaluated, followed by investigation of the effectiveness of traditional ESD protection schemes. CO/sub 2/ snow jet cleaning uses specially designed nozzles to expand liquid CO/sub 2/ into a two-phase flow. The jet stream consists of a high-density jet of solid, yet soft, CO/sub 2/ particles ('snow') immersed in a CO/sub 2/ gas. The tribocharging effect of the high velocity impact of the CO/sub 2/ particles on the surfaces of the slider, suspension, flex cable, and e-block components and assemblies is studied. This paper also includes results of process design variations, such as grounding and ionization to reduce the risk of ESD damage. A quasistatic tester was used to characterize the HGAs and HSA before and after cleaning.
{"title":"Evaluation of tribocharging and ESD protection schemes on GMR magnetic recording heads during CO2 jet cleaning","authors":"D. Vickers, D. Carradero","doi":"10.1109/EOSESD.2000.890048","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890048","url":null,"abstract":"This paper presents the results of investigations into tribocharging and ESD effects of CO/sub 2/ snow jet cleaning on magnetic recording components for hard disk drives. The studies are performed at different levels of integration, including component parts, head gimbal assembly (HGA) and head stack assembly. The electrical stresses induced during the cleaning process are evaluated, followed by investigation of the effectiveness of traditional ESD protection schemes. CO/sub 2/ snow jet cleaning uses specially designed nozzles to expand liquid CO/sub 2/ into a two-phase flow. The jet stream consists of a high-density jet of solid, yet soft, CO/sub 2/ particles ('snow') immersed in a CO/sub 2/ gas. The tribocharging effect of the high velocity impact of the CO/sub 2/ particles on the surfaces of the slider, suspension, flex cable, and e-block components and assemblies is studied. This paper also includes results of process design variations, such as grounding and ionization to reduce the risk of ESD damage. A quasistatic tester was used to characterize the HGAs and HSA before and after cleaning.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129758859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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