Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890023
K. Verhaege, C. Russ
A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.
{"title":"Wafer cost reduction through design of high performance fully silicided ESD devices","authors":"K. Verhaege, C. Russ","doi":"10.1109/EOSESD.2000.890023","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890023","url":null,"abstract":"A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced. This novel design solution can be implemented in a straightforward manner without process modifications. ESD performance levels obtained in different 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economical silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide blocked designs is presented.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128188671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890105
J. Franey
As electronic components use less material, they become more sensitive to voltage and current variations. This increases their operational speed and functionality. Corrosion that was previously inconsequential now becomes a major factor in current electronic components. These problems take on a myriad of new consequences. Of these new problems, the tribocharging and consequent discharging of differential surfaces can be significant. Defects from melted circuits that fail initially, or later in the field (latent defects), or noise generation created by microwave discharges occur. This noise can cause digital service interruption by creating catastrophic bit rate errors. This paper shows these ESD events can take place on matched metal surfaces within 5 to 30 minutes following etching.
{"title":"Corrosion induced electrostatic damage","authors":"J. Franey","doi":"10.1109/EOSESD.2000.890105","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890105","url":null,"abstract":"As electronic components use less material, they become more sensitive to voltage and current variations. This increases their operational speed and functionality. Corrosion that was previously inconsequential now becomes a major factor in current electronic components. These problems take on a myriad of new consequences. Of these new problems, the tribocharging and consequent discharging of differential surfaces can be significant. Defects from melted circuits that fail initially, or later in the field (latent defects), or noise generation created by microwave discharges occur. This noise can cause digital service interruption by creating catastrophic bit rate errors. This paper shows these ESD events can take place on matched metal surfaces within 5 to 30 minutes following etching.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127189060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890049
W. Ogle, C. Moore
In recent years, there has been a tremendous effort in the disk drive industry to produce devices with greater storage capacity and better performance. This push for increased density has led the industry to rely more and more exclusively on magnetoresistive (MR) or giant magnetoresistive (GMR) heads in drive design. These heads have significant advantages over the older inductive heads and have helped to increase area densities to new heights. Unfortunately, these devices are extremely sensitive to damage from current transients. Consequently, manufacturers of heads and disk drives have established specifications for all aspects of handling and testing of heads. These guidelines are designed to prevent the (G)MR element from ever being subjected to potentially damaging uncontrolled current transients. Test equipment used by any facility that deals with (G)MR heads must necessarily be evaluated for its potential to introduce undesirable current transients. The nature of the devices used to measure current transients can lead to misinterpretation of test equipment safety. It is important to understand both how to measure current transients and whether or not these events will damage an MR element. This paper defines and discusses the nature of a true current transient, explains the proper methods for measurement and interpretation of these events, and discusses how they may or may not relate to damage of an MR head.
{"title":"Measuring and specifying limits on current transients and understanding their relationship to MR head damage","authors":"W. Ogle, C. Moore","doi":"10.1109/EOSESD.2000.890049","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890049","url":null,"abstract":"In recent years, there has been a tremendous effort in the disk drive industry to produce devices with greater storage capacity and better performance. This push for increased density has led the industry to rely more and more exclusively on magnetoresistive (MR) or giant magnetoresistive (GMR) heads in drive design. These heads have significant advantages over the older inductive heads and have helped to increase area densities to new heights. Unfortunately, these devices are extremely sensitive to damage from current transients. Consequently, manufacturers of heads and disk drives have established specifications for all aspects of handling and testing of heads. These guidelines are designed to prevent the (G)MR element from ever being subjected to potentially damaging uncontrolled current transients. Test equipment used by any facility that deals with (G)MR heads must necessarily be evaluated for its potential to introduce undesirable current transients. The nature of the devices used to measure current transients can lead to misinterpretation of test equipment safety. It is important to understand both how to measure current transients and whether or not these events will damage an MR element. This paper defines and discusses the nature of a true current transient, explains the proper methods for measurement and interpretation of these events, and discusses how they may or may not relate to damage of an MR head.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121581026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890022
C. Duvvury, Sridhar Ramaswamy, A. Amerasekera, R. Cline, Bernhard H. Andresen, V. Gupta
The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.
{"title":"Substrate pump NMOS for ESD protection applications","authors":"C. Duvvury, Sridhar Ramaswamy, A. Amerasekera, R. Cline, Bernhard H. Andresen, V. Gupta","doi":"10.1109/EOSESD.2000.890022","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890022","url":null,"abstract":"The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121424235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890046
F.G. Zhao, R. Tao, Hong Tian
One of the key issues for ESD protection in the GMR head gimbal assembly (HGA) and head stack assembly (HSA) processes is how to prevent "metal contact", i.e. the direct contact of the GMR sensor to metal. This paper describes a very effective method for better ESD protection in the HGA and HSA processes where the "metal contact" cannot be avoided.
{"title":"The effect of bonding sequence on GMR ESD protection","authors":"F.G. Zhao, R. Tao, Hong Tian","doi":"10.1109/EOSESD.2000.890046","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890046","url":null,"abstract":"One of the key issues for ESD protection in the GMR head gimbal assembly (HGA) and head stack assembly (HSA) processes is how to prevent \"metal contact\", i.e. the direct contact of the GMR sensor to metal. This paper describes a very effective method for better ESD protection in the HGA and HSA processes where the \"metal contact\" cannot be avoided.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121208881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890028
J. L. Muñoz, J. Tan, C. Adriano, E. Roldan, J. Sadie
Electrostatic discharge (ESD) is the rapid transfer of electrostatic charge between bodies at different electrostatic potentials. In an ESD event, a short burst of radiated energy in the form of an electromagnetic pulse or electromagnetic interference (EMI) is created. In this paper, we discuss the use of a homemade loop to detect the EMI generated by an ESD event. We also report the observed correlation between three industry defined ESD stress models and the radiated EMI signal as detected by the loop antenna. A Zapmaster Keytek 512 zapper is used to simulate the ESD events and a high-speed oscilloscope is used to capture the EMI detected by the loop antenna. In the paper, we also report use of the loop antenna in solving an ESD issue that affected the 32M Boot Block flash memory device.
{"title":"Detecting ESD events using a loop antenna","authors":"J. L. Muñoz, J. Tan, C. Adriano, E. Roldan, J. Sadie","doi":"10.1109/EOSESD.2000.890028","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890028","url":null,"abstract":"Electrostatic discharge (ESD) is the rapid transfer of electrostatic charge between bodies at different electrostatic potentials. In an ESD event, a short burst of radiated energy in the form of an electromagnetic pulse or electromagnetic interference (EMI) is created. In this paper, we discuss the use of a homemade loop to detect the EMI generated by an ESD event. We also report the observed correlation between three industry defined ESD stress models and the radiated EMI signal as detected by the loop antenna. A Zapmaster Keytek 512 zapper is used to simulate the ESD events and a high-speed oscilloscope is used to capture the EMI detected by the loop antenna. In the paper, we also report use of the loop antenna in solving an ESD issue that affected the 32M Boot Block flash memory device.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890107
Y. Anand, D. Crowe, A. Feinberg, C. Jones
This paper describes a case study of GaAs IC ESD failures caused in a RF test handler. The test handler caused yield problems compared with another tester. A small insulator inside the test fixture assembly was found to generate up to 200 volt ESD pulses, causing sporadic device failures. This problem was resolved by replacing the insulator with a piece of static dissipative material. In this paper, we present tester investigation and evaluation, material investigation, experimental results, and conclusions from production follow-up.
{"title":"Random GaAs IC's ESD failures caused by RF test handler","authors":"Y. Anand, D. Crowe, A. Feinberg, C. Jones","doi":"10.1109/EOSESD.2000.890107","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890107","url":null,"abstract":"This paper describes a case study of GaAs IC ESD failures caused in a RF test handler. The test handler caused yield problems compared with another tester. A small insulator inside the test fixture assembly was found to generate up to 200 volt ESD pulses, causing sporadic device failures. This problem was resolved by replacing the insulator with a piece of static dissipative material. In this paper, we present tester investigation and evaluation, material investigation, experimental results, and conclusions from production follow-up.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128963584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890115
M. Mergens, W. Wilkening, G. Kiesewetter, S. Mettler, H. Wolf, J. Hieber, W. Fichtner
An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.
{"title":"ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior","authors":"M. Mergens, W. Wilkening, G. Kiesewetter, S. Mettler, H. Wolf, J. Hieber, W. Fichtner","doi":"10.1109/EOSESD.2000.890115","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890115","url":null,"abstract":"An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132591162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890112
Yu Wang, P. Juliano, S. Joshi, E. Rosenbaum
An electrothermal diode model intended for implementation in a SPICE-like simulator is presented. The model is valid in the high current, forward-bias and reverse-breakdown regimes where diodes operate during ESD events. We also present a procedure for extracting the temperature of an SOI diode from an I-V measurement.
{"title":"Electrothermal modeling of ESD diodes in bulk-Si and SOI technologies","authors":"Yu Wang, P. Juliano, S. Joshi, E. Rosenbaum","doi":"10.1109/EOSESD.2000.890112","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890112","url":null,"abstract":"An electrothermal diode model intended for implementation in a SPICE-like simulator is presented. The model is valid in the high current, forward-bias and reverse-breakdown regimes where diodes operate during ESD events. We also present a procedure for extracting the temperature of an SOI diode from an I-V measurement.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132158426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890033
M. Lee, C.H. Liu, Chung-Chiang Lin, Jin-Tau Chou, H. Tang, Y.J. Chang, K. Fu
In this work, we have found that the TLPG (transmission line pulse generator) can be well correlated to the HBM by adding a parasitic series resistance obtained simply from the least squares error solution method or numerically from a simplified LEM (lumped element model) method. Also, experimental evidence suggests that the HBM is best described by the log normal distribution rather than the normal distribution.
{"title":"Comparison and correlation of ESD HBM (human body model) obtained between TLPG, wafer-level, and package-level tests","authors":"M. Lee, C.H. Liu, Chung-Chiang Lin, Jin-Tau Chou, H. Tang, Y.J. Chang, K. Fu","doi":"10.1109/EOSESD.2000.890033","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890033","url":null,"abstract":"In this work, we have found that the TLPG (transmission line pulse generator) can be well correlated to the HBM by adding a parasitic series resistance obtained simply from the least squares error solution method or numerically from a simplified LEM (lumped element model) method. Also, experimental evidence suggests that the HBM is best described by the log normal distribution rather than the normal distribution.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133890496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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