Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890092
D. Guarisco, M. Li
9 Gb/in/sup 2/ GMR heads were subjected to electrical overstress using square pulses of variable duration. The pulse length was varied between 4 ns and 80 ms. For each pulse length, the magnetic and physical failure thresholds were measured via a quasi-static test. It is found that for long pulses (/spl gsim/1 /spl mu/s) the GMR sensors fail at constant power, whereas at very short times (<100 ns), the system starts to gradually transition to an adiabatic regime where failure occurs at constant energy.
{"title":"ESD sensitivity of GMR heads at variable pulse length","authors":"D. Guarisco, M. Li","doi":"10.1109/EOSESD.2000.890092","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890092","url":null,"abstract":"9 Gb/in/sup 2/ GMR heads were subjected to electrical overstress using square pulses of variable duration. The pulse length was varied between 4 ns and 80 ms. For each pulse length, the magnetic and physical failure thresholds were measured via a quasi-static test. It is found that for long pulses (/spl gsim/1 /spl mu/s) the GMR sensors fail at constant power, whereas at very short times (<100 ns), the system starts to gradually transition to an adiabatic regime where failure occurs at constant energy.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890124
C. F. Lam
The goal of this paper is to share information on the study of static-dissipative tweezers for use in giant magneto-resistive recording heads. There are two tests, one to measure the amount of energy of transient currents discharged from tweezers and the other to determine the voltage of a head gimbal assembly (HGA) at which a pair of grounded tweezers can damage the GMR head when in contact. These experiments are important because the energy of transient current discharged from tweezers directly affects the magnetic performance of the GMR head. The results of the two tests correlate relatively well. Most dissipative ceramic tweezers performed very well. Black polymer tweezers with 1.3% carbon, and metal impregnated ceramic tweezers, also performed very well. One type of dissipative copolymer tweezers was found to behave like a conductor. Some carbon-loaded polymer tweezers and stainless steel tweezers have the worst ESD performances.
{"title":"A study of static-dissipative tweezers for handling giant magneto-resistive recording heads","authors":"C. F. Lam","doi":"10.1109/EOSESD.2000.890124","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890124","url":null,"abstract":"The goal of this paper is to share information on the study of static-dissipative tweezers for use in giant magneto-resistive recording heads. There are two tests, one to measure the amount of energy of transient currents discharged from tweezers and the other to determine the voltage of a head gimbal assembly (HGA) at which a pair of grounded tweezers can damage the GMR head when in contact. These experiments are important because the energy of transient current discharged from tweezers directly affects the magnetic performance of the GMR head. The results of the two tests correlate relatively well. Most dissipative ceramic tweezers performed very well. Black polymer tweezers with 1.3% carbon, and metal impregnated ceramic tweezers, also performed very well. One type of dissipative copolymer tweezers was found to behave like a conductor. Some carbon-loaded polymer tweezers and stainless steel tweezers have the worst ESD performances.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114836994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890025
H. Hyatt, J. Harris, J. Colby, P. Bellew
Decision-making methods for choosing ESD circuit protection remain poorly understood. Selecting an IC which passed ESD device level testing does not guarantee that a particular circuit using that device will survive ESD events. We present an optimization methodology for assessment of ESD circuit protection.
{"title":"Optimizing the performance of ESD circuit protection devices","authors":"H. Hyatt, J. Harris, J. Colby, P. Bellew","doi":"10.1109/EOSESD.2000.890025","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890025","url":null,"abstract":"Decision-making methods for choosing ESD circuit protection remain poorly understood. Selecting an IC which passed ESD device level testing does not guarantee that a particular circuit using that device will survive ESD events. We present an optimization methodology for assessment of ESD circuit protection.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890094
R. Tao, F.G. Zhao
There are basically two kinds of ESD damage modes for GMR sensors in current GMR head gimbal assembly (HGA) and head stack assembly (HSA) processes: the current damage mode and the voltage damage mode. The current damage mode accounts for most of the ESD damage in actual GMR head production, which indicates that the GMR sensor gets damaged by an unexpected transient current passing through it. This paper discusses the possibility of defining a generic ESD threshold for the current damage mode.
{"title":"Threshold of ESD damage to GMR sensor","authors":"R. Tao, F.G. Zhao","doi":"10.1109/EOSESD.2000.890094","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890094","url":null,"abstract":"There are basically two kinds of ESD damage modes for GMR sensors in current GMR head gimbal assembly (HGA) and head stack assembly (HSA) processes: the current damage mode and the voltage damage mode. The current damage mode accounts for most of the ESD damage in actual GMR head production, which indicates that the GMR sensor gets damaged by an unexpected transient current passing through it. This paper discusses the possibility of defining a generic ESD threshold for the current damage mode.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890116
Jea-Chun Lee, Y. Huh, Jau-Wen Chen, P. Bendix, S. Kang
This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.
本文提出了一种用于多功率集成电路中充电器件模型(CDM)失效分析的芯片级仿真方法。提出了一种考虑CDM失效和有效仿真的电路模型，并将其与电路级ESD模拟器iETSIM相结合。分析了多功率集成电路中的CDM行为，并通过芯片级仿真预测了CDM应力的易损点。仿真结果通过0.25 /spl μ m CMOS ASIC的CDM测试得到验证，具有良好的相关性。这种全芯片级的仿真方法使我们能够在详细的芯片平面图和电网网络开始之前解决CDM故障问题。
{"title":"Chip-level simulation for CDM failures in multi-power ICs","authors":"Jea-Chun Lee, Y. Huh, Jau-Wen Chen, P. Bendix, S. Kang","doi":"10.1109/EOSESD.2000.890116","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890116","url":null,"abstract":"This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122916604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Potentially damaging charging currents and voltages in wafer-level giant magentoresistance (GMR) plasma processing tools have been measured using floating gate EEPROM (FG-EEPROM) monitor wafers. Although FG-EEPROM monitors have been used as semiconductor process monitors, this report demonstrates their use in ESD-sensitive GMR head production. Use of FG-EEPROM monitors allows quantification of plasma-induced EOS voltages and currents, and can be used in optimizing process tool EOS performance, as is demonstrated in a case study on an ion mill.
{"title":"Floating gate EEPROM as EOS indicators during wafer-level GMR processing","authors":"E. Granstrom, R. Cermak, P. Tesárek, N. Tabat","doi":"10.1109/6104.930958","DOIUrl":"https://doi.org/10.1109/6104.930958","url":null,"abstract":"Potentially damaging charging currents and voltages in wafer-level giant magentoresistance (GMR) plasma processing tools have been measured using floating gate EEPROM (FG-EEPROM) monitor wafers. Although FG-EEPROM monitors have been used as semiconductor process monitors, this report demonstrates their use in ESD-sensitive GMR head production. Use of FG-EEPROM monitors allows quantification of plasma-induced EOS voltages and currents, and can be used in optimizing process tool EOS performance, as is demonstrated in a case study on an ion mill.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116233248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890104
D.R. Stockin
The goal of this manuscript is to provide the base knowledge needed to be able to properly manage the testing and/or improvement of a facilities grounding system. Solutions for static charge problems rely on dedicated earth grounds with a resistance-to-ground typically specified at less than 5 ohms. Simple driven rods cannot normally reach this goal and often do not meet the NEC standard of 25 ohms resistance-to-ground. Proper testing and design will provide quantitative data to the EOS/ESD engineer and reduce the potential for revenue loss caused by ESD faults.
{"title":"Design and testing of facilities ground","authors":"D.R. Stockin","doi":"10.1109/EOSESD.2000.890104","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890104","url":null,"abstract":"The goal of this manuscript is to provide the base knowledge needed to be able to properly manage the testing and/or improvement of a facilities grounding system. Solutions for static charge problems rely on dedicated earth grounds with a resistance-to-ground typically specified at less than 5 ohms. Simple driven rods cannot normally reach this goal and often do not meet the NEC standard of 25 ohms resistance-to-ground. Proper testing and design will provide quantitative data to the EOS/ESD engineer and reduce the potential for revenue loss caused by ESD faults.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890090
J. Miller, M. Khazhinsky, J. Weldon
The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.
{"title":"Engineering the cascoded NMOS output buffer for maximum V/sub t1/","authors":"J. Miller, M. Khazhinsky, J. Weldon","doi":"10.1109/EOSESD.2000.890090","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890090","url":null,"abstract":"The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890100
Yong Shen, R. Leung, J.Z.F. Sun
We report a novel mechanism of baseline popping (BLP) of spin-valve (SV) magnetic recording heads induced by machine model (MM) ESD, which is characterized by short transient time (10-20 ns) and high peak current (25-35 mA). Energy required for the phenomenon is just 0.2-0.3 nJ which is significantly less than that required for pinned layer reversal induced by human body model (HBM) ESD (Takahashi et al., 1998). Our data shows that this magnetic instability is caused by a change in the magnetization state of the permanent magnetic layer near track edges and can be eliminated by magnetic field re-initialization.
本文报道了一种由机器模型ESD引起的自旋阀(SV)磁记录磁头基线爆裂(BLP)的新机制，该机制具有瞬态时间短(10-20 ns)和峰值电流高(25-35 mA)的特点。该现象所需的能量仅为0.2-0.3 nJ，明显低于人体模型(HBM) ESD诱导的钉住层反转所需的能量(Takahashi et al.， 1998)。我们的数据表明，这种磁不稳定性是由轨道边缘附近永磁层磁化状态的变化引起的，可以通过磁场重新初始化来消除。
{"title":"Baseline popping of spin-valve recording heads induced by ESD","authors":"Yong Shen, R. Leung, J.Z.F. Sun","doi":"10.1109/EOSESD.2000.890100","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890100","url":null,"abstract":"We report a novel mechanism of baseline popping (BLP) of spin-valve (SV) magnetic recording heads induced by machine model (MM) ESD, which is characterized by short transient time (10-20 ns) and high peak current (25-35 mA). Energy required for the phenomenon is just 0.2-0.3 nJ which is significantly less than that required for pinned layer reversal induced by human body model (HBM) ESD (Takahashi et al., 1998). Our data shows that this magnetic instability is caused by a change in the magnetization state of the permanent magnetic layer near track edges and can be eliminated by magnetic field re-initialization.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130740221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/EOSESD.2000.890024
S. Voldman, D. Hui, D. Young, R. Williams, D. Dreps, J. Howard, M. Sherony, F. Assaderaghi, G. Shahidi
Active clamp circuits are key to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and reliability requirements in high performance CMOS circuits. This paper discusses for the first time the electrostatic discharge (ESD) protection circuits of silicon-on-insulator (SOI) active clamp networks, dynamic threshold MOSFET SOI ESD techniques and the synthesis of DTMOS concepts, ESD protection networks, and active clamp circuitry for high-pin-count high-performance semiconductor chips.
{"title":"Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry","authors":"S. Voldman, D. Hui, D. Young, R. Williams, D. Dreps, J. Howard, M. Sherony, F. Assaderaghi, G. Shahidi","doi":"10.1109/EOSESD.2000.890024","DOIUrl":"https://doi.org/10.1109/EOSESD.2000.890024","url":null,"abstract":"Active clamp circuits are key to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and reliability requirements in high performance CMOS circuits. This paper discusses for the first time the electrostatic discharge (ESD) protection circuits of silicon-on-insulator (SOI) active clamp networks, dynamic threshold MOSFET SOI ESD techniques and the synthesis of DTMOS concepts, ESD protection networks, and active clamp circuitry for high-pin-count high-performance semiconductor chips.","PeriodicalId":332394,"journal":{"name":"Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126851314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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