Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628197
Chi-Shuen Lee, Yuan Shimeng, X. Guan, Jieying Luo, Lan Wei, H. Wong
Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the model's capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.
{"title":"Compact models of emerging devices","authors":"Chi-Shuen Lee, Yuan Shimeng, X. Guan, Jieying Luo, Lan Wei, H. Wong","doi":"10.1109/EDSSC.2013.6628197","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628197","url":null,"abstract":"Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the model's capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131522840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628086
Zhang Shuo, Wang Zongmin, Zhou Liang, Feng Wenxiao, Ding Yang
In this paper, a new design of bandgap reference is presented. Based on traditional bandgap reference circuits, the new one uses a partial supply voltage produced itself feeding back to the other part to improve PSRR. To achieve excellent temperature coefficient, this bandgap reference applies 2nd-order curvature compensated technique which based on a temperature-dependent resistor ratio scheme.
{"title":"A high-PSRR bandgap voltage reference with temperature curvature compensation used for pipeline ADC","authors":"Zhang Shuo, Wang Zongmin, Zhou Liang, Feng Wenxiao, Ding Yang","doi":"10.1109/EDSSC.2013.6628086","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628086","url":null,"abstract":"In this paper, a new design of bandgap reference is presented. Based on traditional bandgap reference circuits, the new one uses a partial supply voltage produced itself feeding back to the other part to improve PSRR. To achieve excellent temperature coefficient, this bandgap reference applies 2nd-order curvature compensated technique which based on a temperature-dependent resistor ratio scheme.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131343413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628137
Qiming Shao, Can Zhao, Can Wu, Jinyu Zhang, Li Zhang, Zhiping Yu
We present in this paper a basic compact model incorporating several key physical mechanisms in nanowire tunneling field-effect transistors (NW-tFETs), such as non-constant subthreshold swing (SS), definition of an on voltage, ballistic transport for carriers in the channel, and quantum capacitance limit (QCL). Using experimental data from [1], the validity of this model is verified. Further, to project the performance of ultra-scaled silicon NW-tFETs, we compare the state-of-the-art gate-all-around (GAA) NW MOSFETs [2] with modeling results for the same NW diameter and EOT (effective oxide thickness). It is concluded that ultra-scaled NW-tFETs can achieve high performance with low subthreshold swing (SS) and nearly the same on current as in MOSFETs.
{"title":"Compact model and projection of silicon nanowire tunneling transistors (NW-tFETs)","authors":"Qiming Shao, Can Zhao, Can Wu, Jinyu Zhang, Li Zhang, Zhiping Yu","doi":"10.1109/EDSSC.2013.6628137","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628137","url":null,"abstract":"We present in this paper a basic compact model incorporating several key physical mechanisms in nanowire tunneling field-effect transistors (NW-tFETs), such as non-constant subthreshold swing (SS), definition of an on voltage, ballistic transport for carriers in the channel, and quantum capacitance limit (QCL). Using experimental data from [1], the validity of this model is verified. Further, to project the performance of ultra-scaled silicon NW-tFETs, we compare the state-of-the-art gate-all-around (GAA) NW MOSFETs [2] with modeling results for the same NW diameter and EOT (effective oxide thickness). It is concluded that ultra-scaled NW-tFETs can achieve high performance with low subthreshold swing (SS) and nearly the same on current as in MOSFETs.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131814219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628151
Yan Li, Yu Hang, Lai Jiang, Zhen Ji, Jun Zhu, M. Niu, P. Xiao
Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.
{"title":"A CMOS time-to-digital converter for multi-voltage threshold method in positron emission tomography","authors":"Yan Li, Yu Hang, Lai Jiang, Zhen Ji, Jun Zhu, M. Niu, P. Xiao","doi":"10.1109/EDSSC.2013.6628151","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628151","url":null,"abstract":"Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133866135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628129
Wei-Xiang Tang, S. Tung, Shui-An Wen, Keng-Yu Lin
In a battery-powered device, power consumption determines the operation time and weight of the overall system. In this paper, a 10 MHz ultra-low voltage SPARK 32-bit RISC microcontroller is proposed, with low power consumption which prolongs operation time and satisfies low end applications in the meantime. The design is carried out with the TSMC 65 nm LP CMOS process, and post-layout simulation indicates the SPARK microcontroller is capable of operating at 10 MHz, and consuming 0.7 mW from a 0.45 V supply. The overall chip layout area is 920×920 μm2.
{"title":"A 70µW/MHz ultra-low voltage microcontroller SPARK","authors":"Wei-Xiang Tang, S. Tung, Shui-An Wen, Keng-Yu Lin","doi":"10.1109/EDSSC.2013.6628129","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628129","url":null,"abstract":"In a battery-powered device, power consumption determines the operation time and weight of the overall system. In this paper, a 10 MHz ultra-low voltage SPARK 32-bit RISC microcontroller is proposed, with low power consumption which prolongs operation time and satisfies low end applications in the meantime. The design is carried out with the TSMC 65 nm LP CMOS process, and post-layout simulation indicates the SPARK microcontroller is capable of operating at 10 MHz, and consuming 0.7 mW from a 0.45 V supply. The overall chip layout area is 920×920 μm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134273356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628108
H. Hussin, M. Muhamad, Y. Abdul Wahab, S. Shahabuddin, N. Soin, M. Bukhori
Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.
{"title":"A study using two stage NBTI model for 32 nm high-k PMOSFET","authors":"H. Hussin, M. Muhamad, Y. Abdul Wahab, S. Shahabuddin, N. Soin, M. Bukhori","doi":"10.1109/EDSSC.2013.6628108","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628108","url":null,"abstract":"Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628084
Zhi-hua Ning, Lenian He, Zhicheng Hu, G. Jin, W. Ng
A feedback-voltage-sensing translator for floating buck DC-DC converter is designed for CSMC's 0.5 μm 60 V BCD process. The proposed circuit utilizes one NPN, one PNP and a resistor to translate a Vin-referenced (input voltage as the reference, instead of GND) feedback voltage to a current, which is then translated to a ground-referenced voltage with another two bipolar transistors and one resistor. High precision translation is accomplished based on the equivalent base-emitter voltages of the bipolar transistors. Simulation results show that, for a Vin-referenced feedback voltage of Vfb = Vin - Vn, the proposed translator generates a ground-referenced voltage of Vn with a variation of only 0.6 mV over a wide range of Vin from 18 to 60 V. The translator also achieves a low temperature coefficient of 6.9 ppm/°C from -40 to 125 °C. Additionally, the noise of this translator is only 3.46 μVrms from 0.1 to 10 Hz and the PSR is -98 dB @ DC. The translator is verified via Spectre simulation in a floating buck converter.
{"title":"A feedback-voltage-sensing translator for floating buck DC-DC converters","authors":"Zhi-hua Ning, Lenian He, Zhicheng Hu, G. Jin, W. Ng","doi":"10.1109/EDSSC.2013.6628084","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628084","url":null,"abstract":"A feedback-voltage-sensing translator for floating buck DC-DC converter is designed for CSMC's 0.5 μm 60 V BCD process. The proposed circuit utilizes one NPN, one PNP and a resistor to translate a V<sub>in</sub>-referenced (input voltage as the reference, instead of GND) feedback voltage to a current, which is then translated to a ground-referenced voltage with another two bipolar transistors and one resistor. High precision translation is accomplished based on the equivalent base-emitter voltages of the bipolar transistors. Simulation results show that, for a V<sub>in</sub>-referenced feedback voltage of V<sub>fb</sub> = V<sub>in</sub> - V<sub>n</sub>, the proposed translator generates a ground-referenced voltage of V<sub>n</sub> with a variation of only 0.6 mV over a wide range of V<sub>in</sub> from 18 to 60 V. The translator also achieves a low temperature coefficient of 6.9 ppm/°C from -40 to 125 °C. Additionally, the noise of this translator is only 3.46 μV<sub>rms</sub> from 0.1 to 10 Hz and the PSR is -98 dB @ DC. The translator is verified via Spectre simulation in a floating buck converter.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132327713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628211
Aixi Zhang, Jin He, Xiaoan Zhu, Yue Hu, Hao Wang, W. Deng, Hongyu He, Ying Zhu, Xiangyu Zhang, M. Chan
In this paper, a nanowire tunnel field-effect transistor with dynamic threshold operation architecture (DT-NTFET) is proposed and the numerical study on its characteristics is presented. It shows that, in DT operation, the DT-NTFET can choose the threshold voltage (VT) flexibly by changing the adjust gate voltage, thus it can be applied as a multifunctional device in the future circuit design; in common mode operation, its subthreshold swing (SS) gets steeper, and its drive current is enhanced with no loss of OFF-state current.
{"title":"Numerical study on nanowire tunnel FET with dynamic threshold operation architecture","authors":"Aixi Zhang, Jin He, Xiaoan Zhu, Yue Hu, Hao Wang, W. Deng, Hongyu He, Ying Zhu, Xiangyu Zhang, M. Chan","doi":"10.1109/EDSSC.2013.6628211","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628211","url":null,"abstract":"In this paper, a nanowire tunnel field-effect transistor with dynamic threshold operation architecture (DT-NTFET) is proposed and the numerical study on its characteristics is presented. It shows that, in DT operation, the DT-NTFET can choose the threshold voltage (VT) flexibly by changing the adjust gate voltage, thus it can be applied as a multifunctional device in the future circuit design; in common mode operation, its subthreshold swing (SS) gets steeper, and its drive current is enhanced with no loss of OFF-state current.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115102283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628039
S. Tu, Hsin-Wei Yeh
A new class E switching power regulator controller for buck/boost conversion is proposed, which it has the characteristic of programmable PID look-up table. The proposed regulator controller employs hysteresis comparators, an error process unit (EPU) for voltage regulation, a programmable PID compensator and a digital PWM (DPWM). Based on the programmable table look-up mechanism, the proposed controller is able to access external memory for different look-up tables in the applications of power regulation. The proposed controller for class E buck/boost converters has been validated with simulation results.
{"title":"A PWM controller with table look-up for DC-DC class E buck/boost conversion","authors":"S. Tu, Hsin-Wei Yeh","doi":"10.1109/EDSSC.2013.6628039","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628039","url":null,"abstract":"A new class E switching power regulator controller for buck/boost conversion is proposed, which it has the characteristic of programmable PID look-up table. The proposed regulator controller employs hysteresis comparators, an error process unit (EPU) for voltage regulation, a programmable PID compensator and a digital PWM (DPWM). Based on the programmable table look-up mechanism, the proposed controller is able to access external memory for different look-up tables in the applications of power regulation. The proposed controller for class E buck/boost converters has been validated with simulation results.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628071
Bin Jiao, Ning Deng, Jie Yu, Yue Bai, Minghao Wu, Ye Zhang, H. Qian, Huaqiang Wu
Resistive random access memories (RRAM) often show large variation due to the stochastic nature of the switching process. Bilayer AlOx/WOx based RRAM cells were investigated for key parameters variations. Those AlOx/WOx memory devices were fabricated in a commercial CMOS foundry. Yield of forming process is studied with different transistor size and forming voltage. The tradeoff between array size, speed and power consumption are discussed.
{"title":"Resisitive switching variability study on 1T1R AlOx/WOx-based RRAM array","authors":"Bin Jiao, Ning Deng, Jie Yu, Yue Bai, Minghao Wu, Ye Zhang, H. Qian, Huaqiang Wu","doi":"10.1109/EDSSC.2013.6628071","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628071","url":null,"abstract":"Resistive random access memories (RRAM) often show large variation due to the stochastic nature of the switching process. Bilayer AlOx/WOx based RRAM cells were investigated for key parameters variations. Those AlOx/WOx memory devices were fabricated in a commercial CMOS foundry. Yield of forming process is studied with different transistor size and forming voltage. The tradeoff between array size, speed and power consumption are discussed.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129385998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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