Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628234
Min Tan, W. Ki
In this paper we identify the defining characteristic of a class of split-output miller-compensated (SOM) amplifiers. Existing amplifiers implementing this defining feature are identified, and new two-stage SOM amplifiers are proposed. Various transistor-level implementations of SOM amplifiers are designed in UMC130 CMOS technology and their small-signal circuits are analyzed. Simulation results show that the proposed designs outperform the simple miller-compensated two-stage amplifier in terms of both small-signal performance and large-signal performance.
{"title":"Split-output miller-compensated two-stage amplifiers","authors":"Min Tan, W. Ki","doi":"10.1109/EDSSC.2013.6628234","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628234","url":null,"abstract":"In this paper we identify the defining characteristic of a class of split-output miller-compensated (SOM) amplifiers. Existing amplifiers implementing this defining feature are identified, and new two-stage SOM amplifiers are proposed. Various transistor-level implementations of SOM amplifiers are designed in UMC130 CMOS technology and their small-signal circuits are analyzed. Simulation results show that the proposed designs outperform the simple miller-compensated two-stage amplifier in terms of both small-signal performance and large-signal performance.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130325858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628180
K. Guha, Purbashis Ganguly, S. Baishya
This paper deals with the design and simulation of low power and highly efficient RF Power Amplifiers for 4th Generation Wireless Systems. Efficient Linearization and Bandwidth Enhancement techniques are implemented to increase the performance metrics of the power amplifier under consideration. A 90nm CMOS, 60 GHz fully integrated power amplifier has been designed for the 4th Generation Wireless Systems. It has been optimized to deliver maximum linear output power and a considerable amount of gain in the VHF band around 60 GHz. The schematic of the two stage power amplifier has been designed using Agilent's Advanced Design System software. The schematic is used to plot Gain, Linearity, Noise Figure and Stability.
{"title":"Performance analysis of low power and high frequency novel RF Power Amplifier for 4G systems","authors":"K. Guha, Purbashis Ganguly, S. Baishya","doi":"10.1109/EDSSC.2013.6628180","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628180","url":null,"abstract":"This paper deals with the design and simulation of low power and highly efficient RF Power Amplifiers for 4th Generation Wireless Systems. Efficient Linearization and Bandwidth Enhancement techniques are implemented to increase the performance metrics of the power amplifier under consideration. A 90nm CMOS, 60 GHz fully integrated power amplifier has been designed for the 4th Generation Wireless Systems. It has been optimized to deliver maximum linear output power and a considerable amount of gain in the VHF band around 60 GHz. The schematic of the two stage power amplifier has been designed using Agilent's Advanced Design System software. The schematic is used to plot Gain, Linearity, Noise Figure and Stability.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628115
G. Dash, J. Pradhan, S. K. Swain, S. R. Pattanaik
The electric field and width of the avalanche region are vital while determining the performance of an IMPATT diode. In an attempt to optimize the same a new doping pattern in the form of doping steps is introduced in the avalanche zone and its effects on the terahertz characteristics of a 4H-SiC IMPATT Diode are explored. It is exciting to observe a conversion efficiency of 17.24 % from the IMPAT T diode with the proposed doping steps.
{"title":"Realization of high efficiency 4H-SiC IMPATT diode using optimized doping steps","authors":"G. Dash, J. Pradhan, S. K. Swain, S. R. Pattanaik","doi":"10.1109/EDSSC.2013.6628115","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628115","url":null,"abstract":"The electric field and width of the avalanche region are vital while determining the performance of an IMPATT diode. In an attempt to optimize the same a new doping pattern in the form of doping steps is introduced in the avalanche zone and its effects on the terahertz characteristics of a 4H-SiC IMPATT Diode are explored. It is exciting to observe a conversion efficiency of 17.24 % from the IMPAT T diode with the proposed doping steps.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115752000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628150
Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang
This paper presents a 270-V, 56-A GaN power module with three AlN substrates are prepared for the module. Each substrate is composed of three parallel connected GaN chips which incorporates six 2-A AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) cells. The substrate layout inside the module is designed to reduce package parasitic. The devices are wire-bonded in parallel connection to increase the power rating. The packaged GaN HEMTs exhibit the pulsed drain current of 0.435 A/mm. Both DC and pulsed current-voltage (ID-VDS) characteristics are measured for different connection and sizes of devices, at various of power densities, pulse lengths, and duty factors. The other static parameters like threshold voltage and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. Performance of multiple chip GaN power module package is studied. Experimental results demonstrated the ability to parallel nine GaN HEMTs die together and to verify the current sharing during the dynamic switching to attain high-current capacities.
{"title":"All GaN-on-Si high power module design and performance evaluation","authors":"Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang","doi":"10.1109/EDSSC.2013.6628150","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628150","url":null,"abstract":"This paper presents a 270-V, 56-A GaN power module with three AlN substrates are prepared for the module. Each substrate is composed of three parallel connected GaN chips which incorporates six 2-A AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) cells. The substrate layout inside the module is designed to reduce package parasitic. The devices are wire-bonded in parallel connection to increase the power rating. The packaged GaN HEMTs exhibit the pulsed drain current of 0.435 A/mm. Both DC and pulsed current-voltage (ID-VDS) characteristics are measured for different connection and sizes of devices, at various of power densities, pulse lengths, and duty factors. The other static parameters like threshold voltage and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. Performance of multiple chip GaN power module package is studied. Experimental results demonstrated the ability to parallel nine GaN HEMTs die together and to verify the current sharing during the dynamic switching to attain high-current capacities.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628165
Huang Xiaozong, Shi Jiangang, Huang Wengang, L. Fan
ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of the chip, electrical measurement determines the failure mechanism. The protection of power rail is not robust enough for shunting the ESD current under ND and PS modes. RC+BigFET clamp is used to improve the ESD robustness of whole chip to 3500V which is qualified for most applications.
{"title":"Failure analysis of output stage due to ESD stress in submicron CMOS technology","authors":"Huang Xiaozong, Shi Jiangang, Huang Wengang, L. Fan","doi":"10.1109/EDSSC.2013.6628165","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628165","url":null,"abstract":"ESD failure of an operational amplifier in submicron CMOS technology is analyzed to locate the failure mechanism and re-design the protection structure in this paper. From the experimental results, the specifications related to the output stage with large size devices are degraded or exceed the qualified range. With the deep analysis of internal circuit of the chip, electrical measurement determines the failure mechanism. The protection of power rail is not robust enough for shunting the ESD current under ND and PS modes. RC+BigFET clamp is used to improve the ESD robustness of whole chip to 3500V which is qualified for most applications.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628136
Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo
The properties of III-V compound semiconductors and their heterojunctions have been relentlessly investigated due to their wide-ranging applications in electronic and optoelectronic technologies. One of most important electronic property of heterojunctions is the band offset which describes the relative alignment of the electronic bands across the junction interface. Accurate determination of band offsets is critical for understanding quantum transport properties of the heterojuncton. For many III-V materials systems, the band offset has been carefully measured experimentally.[1]
{"title":"Band offsets of AlxGa1−xAs/GaAs heterojunction from atomistic first principles","authors":"Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo","doi":"10.1109/EDSSC.2013.6628136","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628136","url":null,"abstract":"The properties of III-V compound semiconductors and their heterojunctions have been relentlessly investigated due to their wide-ranging applications in electronic and optoelectronic technologies. One of most important electronic property of heterojunctions is the band offset which describes the relative alignment of the electronic bands across the junction interface. Accurate determination of band offsets is critical for understanding quantum transport properties of the heterojuncton. For many III-V materials systems, the band offset has been carefully measured experimentally.[1]","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114866201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628140
Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo
A charge pump with excellent current matching and negligible current variation characteristics over wide output voltage dynamic range is proposed, which is simulated in the 0.18μm standard CMOS process with the power supply 1.8V. The proposed charge pump circuit improves current matching by applying a high gain operational trans-conductance amplifier. Negligible current variation is achieved by inducing a negative feedback loop to suppress the channel modulation effect. Compared with conventional charge pump circuit, the current mismatch of the proposed charge pump circuit is less than 0.5% within the output voltage dynamic range from 0.2V to 1.7V, and the current variation is reduced to 0.8% over the output voltage dynamic range from 0.32V to 1.7V. Besides, the average power consumption of the proposed charge pump circuit is about 0.48mW making it suitable for low voltage and low power PLLs.
{"title":"A charge pump with reduced current variation and mismatch in low-voltage low-power PLLs","authors":"Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo","doi":"10.1109/EDSSC.2013.6628140","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628140","url":null,"abstract":"A charge pump with excellent current matching and negligible current variation characteristics over wide output voltage dynamic range is proposed, which is simulated in the 0.18μm standard CMOS process with the power supply 1.8V. The proposed charge pump circuit improves current matching by applying a high gain operational trans-conductance amplifier. Negligible current variation is achieved by inducing a negative feedback loop to suppress the channel modulation effect. Compared with conventional charge pump circuit, the current mismatch of the proposed charge pump circuit is less than 0.5% within the output voltage dynamic range from 0.2V to 1.7V, and the current variation is reduced to 0.8% over the output voltage dynamic range from 0.32V to 1.7V. Besides, the average power consumption of the proposed charge pump circuit is about 0.48mW making it suitable for low voltage and low power PLLs.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628226
D. Shan, Dedong Han, F. Huang, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shengdong Zhang
Fully transparent Aluminum-doped zinc oxide (AZO) thin-film transistors (TFTs) were fabricated using radio frequency sputtering at room temperature. To ensure transparency, the AZO-TFTs were fabricated on glass substrate, with SiO2 as gate insulator. Indium tin oxide (ITO) was adopted as gate and source/drain electrodes. The electrical characteristics of AZO-TFT were investigated by IDS-VDS and IDS-VGS measurements, excellent electrical properties were obtained. Furthermore, we researched the post-annealing effects on characteristics of AZO-TFT.
{"title":"Fabrication and characteristics of fully transparent Aluminum-doped zinc oxide thin-film transistors","authors":"D. Shan, Dedong Han, F. Huang, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shengdong Zhang","doi":"10.1109/EDSSC.2013.6628226","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628226","url":null,"abstract":"Fully transparent Aluminum-doped zinc oxide (AZO) thin-film transistors (TFTs) were fabricated using radio frequency sputtering at room temperature. To ensure transparency, the AZO-TFTs were fabricated on glass substrate, with SiO2 as gate insulator. Indium tin oxide (ITO) was adopted as gate and source/drain electrodes. The electrical characteristics of AZO-TFT were investigated by IDS-VDS and IDS-VGS measurements, excellent electrical properties were obtained. Furthermore, we researched the post-annealing effects on characteristics of AZO-TFT.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121676559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628113
T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha
This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.
本文研究了栅极全能(GAA)垂直纳米线晶体管(VNWFET)作为未来非易失性存储器(NVM)如电阻随机存取存储器(RRAM)、相变随机存取存储器(PCRAM)和自旋转矩传输存储器(STT-RAM或MRAM)中的存取元件的应用。我们主要选择直流(DC)参数ION和ION/IOFF作为我们的优值(FOM)，并通过考虑各种关键工艺参数(如沟道长度、鳍片掺杂、栅极重叠和纳米线晶体管的横截面形状)来优化垂直纳米线场效应管。此外，使用优化后的器件在3×3交叉棒阵列中，我们评估了由于有源器件对相邻非活动器件的读/写干扰。我们发现，优化后的存取器件可用于不同存储器件所需的电流额定值范围，离子最高可达0.19 a /μm2, IOFF低至2 nA/μm2。
{"title":"Design optimization of gate-all-around vertical nanowire transistors for future memory applications","authors":"T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha","doi":"10.1109/EDSSC.2013.6628113","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628113","url":null,"abstract":"This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121393519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628160
Zhihua Wang, Kai Yang, Wan Wang, Hanjun Jiang, Shouhao Wu, Qingliang Lin, Wen Jia
This paper proposes a wireless healthcare system architecture that uses a wearable smart sensor to record the body sounds for health monitoring and diagnosis, which can prevent the damage to human bodies by those diagnosis instruments with active energy transmission such as X-ray detection and ultrasonic monitoring. A typical implementation of heart sound monitoring sensor is presented. The designed sensor records the heart beat sounds that can be used for real-time and long-term heart rate monitoring.
{"title":"Sound monitoring based wireless healthcare and a typical implmenation for heart rate monitoring","authors":"Zhihua Wang, Kai Yang, Wan Wang, Hanjun Jiang, Shouhao Wu, Qingliang Lin, Wen Jia","doi":"10.1109/EDSSC.2013.6628160","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628160","url":null,"abstract":"This paper proposes a wireless healthcare system architecture that uses a wearable smart sensor to record the body sounds for health monitoring and diagnosis, which can prevent the damage to human bodies by those diagnosis instruments with active energy transmission such as X-ray detection and ultrasonic monitoring. A typical implementation of heart sound monitoring sensor is presented. The designed sensor records the heart beat sounds that can be used for real-time and long-term heart rate monitoring.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：