Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628223
Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu
A novel 24-sided concave-convex geometry monolithic transformer that has high self-resonant frequency and quality factor is presented. It is implemented with the top level thick Cu metal and multiple geometrical structures in 0.13 um CMOS mixed-signal 1P6M salicide back-end process. Compared to those with conventional square, hexagonal and octagonal geometry structure, the novel transformer achieves better quality factor, self-resonant frequency and less chip area. The simulation results show that 1.12, 1 and 0.58 GHz improvements in SRF, and 2.4, 0.9 and 0.3 enhancements in quality factor are obtained respectively when compared to typical square, hexagonal and octagonal transformer with the same inductance of the primary and secondary winding.
提出了一种具有高自谐振频率和高品质因数的24面凹凸几何单片变压器。它是在0.13 um CMOS混合信号1P6M salicide后端工艺中采用顶级厚铜金属和多种几何结构实现的。与传统的方形、六角形和八角形结构的变压器相比，该变压器具有更好的质量因数、自谐振频率和更小的芯片面积。仿真结果表明，与主、次绕组电感相同的典型方形、六角形和八角形变压器相比，SRF分别提高了1.12、1和0.58 GHz，品质因子分别提高了2.4、0.9和0.3。
{"title":"A high self-resonant and quality factor transformer using novel geometry for silicon based RFICs","authors":"Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu","doi":"10.1109/EDSSC.2013.6628223","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628223","url":null,"abstract":"A novel 24-sided concave-convex geometry monolithic transformer that has high self-resonant frequency and quality factor is presented. It is implemented with the top level thick Cu metal and multiple geometrical structures in 0.13 um CMOS mixed-signal 1P6M salicide back-end process. Compared to those with conventional square, hexagonal and octagonal geometry structure, the novel transformer achieves better quality factor, self-resonant frequency and less chip area. The simulation results show that 1.12, 1 and 0.58 GHz improvements in SRF, and 2.4, 0.9 and 0.3 enhancements in quality factor are obtained respectively when compared to typical square, hexagonal and octagonal transformer with the same inductance of the primary and secondary winding.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133015335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628227
Cejun Wei, Yu Zhu, D. Bartle
Multi-gate pHEMTs are key elements in switch circuits in wireless communication applications due to their low loss and high power capacity with relatively small sizes. A great concern on their high power operation is the power step-back at on-state and at certain power level with harmonics deteriorated. In this paper we discuss the mechanism of power step-back. The power that can pass through an on-state pHEMT is dependent on saturation current, or the maximum available channel current. A premature power step-back or gain collapse in a multi-gate pHEMT is due to largely reduced saturation channel current caused by self-heating in center gate or gates. We developed a self-heating thermal model for multi-gate pHEMTs that can predict power level at that the power step-back and related hysteresis occur.
{"title":"Multi-gate pHEMT modeling for high-power operation","authors":"Cejun Wei, Yu Zhu, D. Bartle","doi":"10.1109/EDSSC.2013.6628227","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628227","url":null,"abstract":"Multi-gate pHEMTs are key elements in switch circuits in wireless communication applications due to their low loss and high power capacity with relatively small sizes. A great concern on their high power operation is the power step-back at on-state and at certain power level with harmonics deteriorated. In this paper we discuss the mechanism of power step-back. The power that can pass through an on-state pHEMT is dependent on saturation current, or the maximum available channel current. A premature power step-back or gain collapse in a multi-gate pHEMT is due to largely reduced saturation channel current caused by self-heating in center gate or gates. We developed a self-heating thermal model for multi-gate pHEMTs that can predict power level at that the power step-back and related hysteresis occur.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628234
Min Tan, W. Ki
In this paper we identify the defining characteristic of a class of split-output miller-compensated (SOM) amplifiers. Existing amplifiers implementing this defining feature are identified, and new two-stage SOM amplifiers are proposed. Various transistor-level implementations of SOM amplifiers are designed in UMC130 CMOS technology and their small-signal circuits are analyzed. Simulation results show that the proposed designs outperform the simple miller-compensated two-stage amplifier in terms of both small-signal performance and large-signal performance.
{"title":"Split-output miller-compensated two-stage amplifiers","authors":"Min Tan, W. Ki","doi":"10.1109/EDSSC.2013.6628234","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628234","url":null,"abstract":"In this paper we identify the defining characteristic of a class of split-output miller-compensated (SOM) amplifiers. Existing amplifiers implementing this defining feature are identified, and new two-stage SOM amplifiers are proposed. Various transistor-level implementations of SOM amplifiers are designed in UMC130 CMOS technology and their small-signal circuits are analyzed. Simulation results show that the proposed designs outperform the simple miller-compensated two-stage amplifier in terms of both small-signal performance and large-signal performance.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130325858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628048
Xiqing Wang, J. Hong, Yandong He, Ganggang Zhang, Lin Han, Xing Zhang
A ring oscillator based structure in digital circuits is presented for measuring NBTI and PBTI effects. The proposed test structure enables simultaneous stress of all devices under tests in either NBTI or PBTI mode and measures frequency degradation or the threshold voltage shift. The threshold voltage shift due to NBTI or PBTI can be directly read out in the proposed circuit which has been designed in a 1.2V, 90nm technology.
{"title":"A ring oscillator based reliability structure for NBTI & PBTI measurement","authors":"Xiqing Wang, J. Hong, Yandong He, Ganggang Zhang, Lin Han, Xing Zhang","doi":"10.1109/EDSSC.2013.6628048","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628048","url":null,"abstract":"A ring oscillator based structure in digital circuits is presented for measuring NBTI and PBTI effects. The proposed test structure enables simultaneous stress of all devices under tests in either NBTI or PBTI mode and measures frequency degradation or the threshold voltage shift. The threshold voltage shift due to NBTI or PBTI can be directly read out in the proposed circuit which has been designed in a 1.2V, 90nm technology.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628140
Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo
A charge pump with excellent current matching and negligible current variation characteristics over wide output voltage dynamic range is proposed, which is simulated in the 0.18μm standard CMOS process with the power supply 1.8V. The proposed charge pump circuit improves current matching by applying a high gain operational trans-conductance amplifier. Negligible current variation is achieved by inducing a negative feedback loop to suppress the channel modulation effect. Compared with conventional charge pump circuit, the current mismatch of the proposed charge pump circuit is less than 0.5% within the output voltage dynamic range from 0.2V to 1.7V, and the current variation is reduced to 0.8% over the output voltage dynamic range from 0.32V to 1.7V. Besides, the average power consumption of the proposed charge pump circuit is about 0.48mW making it suitable for low voltage and low power PLLs.
{"title":"A charge pump with reduced current variation and mismatch in low-voltage low-power PLLs","authors":"Jia Yaoyao, Fang Jian, Qiao Ming, Zhou Ze-kun, Yan Wentao, Zhang Bo","doi":"10.1109/EDSSC.2013.6628140","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628140","url":null,"abstract":"A charge pump with excellent current matching and negligible current variation characteristics over wide output voltage dynamic range is proposed, which is simulated in the 0.18μm standard CMOS process with the power supply 1.8V. The proposed charge pump circuit improves current matching by applying a high gain operational trans-conductance amplifier. Negligible current variation is achieved by inducing a negative feedback loop to suppress the channel modulation effect. Compared with conventional charge pump circuit, the current mismatch of the proposed charge pump circuit is less than 0.5% within the output voltage dynamic range from 0.2V to 1.7V, and the current variation is reduced to 0.8% over the output voltage dynamic range from 0.32V to 1.7V. Besides, the average power consumption of the proposed charge pump circuit is about 0.48mW making it suitable for low voltage and low power PLLs.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628203
P. Bahubalindruni, Vítor M. Grade Tavares, P. Guedes de Oliveira, P. Barquinha, R. Martins, E. Fortunato
A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 μm CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.
{"title":"High-gain amplifier with n-type transistors","authors":"P. Bahubalindruni, Vítor M. Grade Tavares, P. Guedes de Oliveira, P. Barquinha, R. Martins, E. Fortunato","doi":"10.1109/EDSSC.2013.6628203","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628203","url":null,"abstract":"A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 μm CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134218831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628136
Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo
The properties of III-V compound semiconductors and their heterojunctions have been relentlessly investigated due to their wide-ranging applications in electronic and optoelectronic technologies. One of most important electronic property of heterojunctions is the band offset which describes the relative alignment of the electronic bands across the junction interface. Accurate determination of band offsets is critical for understanding quantum transport properties of the heterojuncton. For many III-V materials systems, the band offset has been carefully measured experimentally.[1]
{"title":"Band offsets of AlxGa1−xAs/GaAs heterojunction from atomistic first principles","authors":"Yin Wang, F. Zahid, Y. Zhu, Lei Liu, Jian Wang, Hong Guo","doi":"10.1109/EDSSC.2013.6628136","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628136","url":null,"abstract":"The properties of III-V compound semiconductors and their heterojunctions have been relentlessly investigated due to their wide-ranging applications in electronic and optoelectronic technologies. One of most important electronic property of heterojunctions is the band offset which describes the relative alignment of the electronic bands across the junction interface. Accurate determination of band offsets is critical for understanding quantum transport properties of the heterojuncton. For many III-V materials systems, the band offset has been carefully measured experimentally.[1]","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114866201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628150
Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang
This paper presents a 270-V, 56-A GaN power module with three AlN substrates are prepared for the module. Each substrate is composed of three parallel connected GaN chips which incorporates six 2-A AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) cells. The substrate layout inside the module is designed to reduce package parasitic. The devices are wire-bonded in parallel connection to increase the power rating. The packaged GaN HEMTs exhibit the pulsed drain current of 0.435 A/mm. Both DC and pulsed current-voltage (ID-VDS) characteristics are measured for different connection and sizes of devices, at various of power densities, pulse lengths, and duty factors. The other static parameters like threshold voltage and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. Performance of multiple chip GaN power module package is studied. Experimental results demonstrated the ability to parallel nine GaN HEMTs die together and to verify the current sharing during the dynamic switching to attain high-current capacities.
{"title":"All GaN-on-Si high power module design and performance evaluation","authors":"Stone Cheng, Chieh-An Wang, Po-Chien Chou, W. Chieng, E. Chang","doi":"10.1109/EDSSC.2013.6628150","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628150","url":null,"abstract":"This paper presents a 270-V, 56-A GaN power module with three AlN substrates are prepared for the module. Each substrate is composed of three parallel connected GaN chips which incorporates six 2-A AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) cells. The substrate layout inside the module is designed to reduce package parasitic. The devices are wire-bonded in parallel connection to increase the power rating. The packaged GaN HEMTs exhibit the pulsed drain current of 0.435 A/mm. Both DC and pulsed current-voltage (ID-VDS) characteristics are measured for different connection and sizes of devices, at various of power densities, pulse lengths, and duty factors. The other static parameters like threshold voltage and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. Performance of multiple chip GaN power module package is studied. Experimental results demonstrated the ability to parallel nine GaN HEMTs die together and to verify the current sharing during the dynamic switching to attain high-current capacities.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628207
D. Zhao, Jun He, Xian Huang, Li Zhang, Fang Yang, Dacheng Zhang
In this work, a monolithic integrated MEMS resonator was fabricated and tested. Surface micromachining method was employed to fabricate the cantilever MEMS resonator after a standard 3 μm CMOS process. The wet release method with dilute HF solution was chosen and compared to the anhydrous HF vapor release process. A release-monitoring structure with polysilicon/Au cantilever array was used to determine the corrosion time of the sacrificial material. Results showed that the MOSFETs function well after proposed release process.
{"title":"Fabrication of monolithic integrated MEMS resonator with wet-release-monitoring array","authors":"D. Zhao, Jun He, Xian Huang, Li Zhang, Fang Yang, Dacheng Zhang","doi":"10.1109/EDSSC.2013.6628207","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628207","url":null,"abstract":"In this work, a monolithic integrated MEMS resonator was fabricated and tested. Surface micromachining method was employed to fabricate the cantilever MEMS resonator after a standard 3 μm CMOS process. The wet release method with dilute HF solution was chosen and compared to the anhydrous HF vapor release process. A release-monitoring structure with polysilicon/Au cantilever array was used to determine the corrosion time of the sacrificial material. Results showed that the MOSFETs function well after proposed release process.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628113
T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha
This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.
本文研究了栅极全能(GAA)垂直纳米线晶体管(VNWFET)作为未来非易失性存储器(NVM)如电阻随机存取存储器(RRAM)、相变随机存取存储器(PCRAM)和自旋转矩传输存储器(STT-RAM或MRAM)中的存取元件的应用。我们主要选择直流(DC)参数ION和ION/IOFF作为我们的优值(FOM)，并通过考虑各种关键工艺参数(如沟道长度、鳍片掺杂、栅极重叠和纳米线晶体管的横截面形状)来优化垂直纳米线场效应管。此外，使用优化后的器件在3×3交叉棒阵列中，我们评估了由于有源器件对相邻非活动器件的读/写干扰。我们发现，优化后的存取器件可用于不同存储器件所需的电流额定值范围，离子最高可达0.19 a /μm2, IOFF低至2 nA/μm2。
{"title":"Design optimization of gate-all-around vertical nanowire transistors for future memory applications","authors":"T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha","doi":"10.1109/EDSSC.2013.6628113","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628113","url":null,"abstract":"This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121393519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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