This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.
本文介绍了一种用于384×288红外焦平面阵列(IRFPA)读出链的低功耗自动归零比较器。为了克服柱并联应用的高功耗问题，提出了一种新型的基于逆变器的前置放大器。采用基于0.35um cmos工艺技术开发的14位列并行逐次逼近寄存器(SAR) a /D转换器验证了该比较器的性能。在采样时钟为31.25 KHz，输入信号为1.009 KHz时，A/D转换器的SFDR高达93dB。384列并联adc的总静态功率小于50mW。
{"title":"A low-power auto-zeroed comparator for column-paralleled 14b SAR ADCs of 384×288 IRFPA ROIC","authors":"Meng Chen, Wengao Lu, Tingting Tao, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2013.6628037","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628037","url":null,"abstract":"This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122209162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628132
Diahai Zhang, Siyang Liu, Weifeng Sun
With the trend towards ever-powerful chip and evermore-intense heat fluxes, the thermal issues of packages are becoming increasingly important for power ICs. One of the most effective approach to improve thermal management of ICs is leadframe optimization. In this paper, we present a revised leadframe of DIP8 package which includes a bigger die pad connecting to two pins. The simulation results and experimental data both indicate the new leadframe has a much better thermal performance than the old one. Due to the lower thermal resistance and more heat conductive paths with low thermal resistance, the junction temperature has dramatically declined in the same ambient condition.
{"title":"Reducing thermal resistance of DIP8 package based on leadframe optimization","authors":"Diahai Zhang, Siyang Liu, Weifeng Sun","doi":"10.1109/EDSSC.2013.6628132","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628132","url":null,"abstract":"With the trend towards ever-powerful chip and evermore-intense heat fluxes, the thermal issues of packages are becoming increasingly important for power ICs. One of the most effective approach to improve thermal management of ICs is leadframe optimization. In this paper, we present a revised leadframe of DIP8 package which includes a bigger die pad connecting to two pins. The simulation results and experimental data both indicate the new leadframe has a much better thermal performance than the old one. Due to the lower thermal resistance and more heat conductive paths with low thermal resistance, the junction temperature has dramatically declined in the same ambient condition.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121058472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628191
P. Ray, V. Seena, V. Rao
This work focusses on the development of a ZnO based piezo-resistive polymer cantilever sensor platform. Two different approaches have been taken, one based on Al-doped ZnO transistor (TFT) embedded in a polymeric micro-cantilever and another with a ZnO nanowire embedded microcantilever. Low Young's modulus of SU-8, low process temperature and high strain sensing capability of ZnO makes this platform an attractive option for sensor applications. For both the approaches, electromechanical and mechanical characterization results are reported in this work.
{"title":"A TFT embedded cantilever (CantiFET) platform for sensor applications","authors":"P. Ray, V. Seena, V. Rao","doi":"10.1109/EDSSC.2013.6628191","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628191","url":null,"abstract":"This work focusses on the development of a ZnO based piezo-resistive polymer cantilever sensor platform. Two different approaches have been taken, one based on Al-doped ZnO transistor (TFT) embedded in a polymeric micro-cantilever and another with a ZnO nanowire embedded microcantilever. Low Young's modulus of SU-8, low process temperature and high strain sensing capability of ZnO makes this platform an attractive option for sensor applications. For both the approaches, electromechanical and mechanical characterization results are reported in this work.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628222
Chang Qi, Xinzhi Shi, Ye Shuangli, Jinguang Jiang
In this paper, a new equivalent circuit-level model of QCLs is introduced to overcome drawbacks of the previous models. The photon gain coefficient and injection current efficiency both depend on the injector doping density in the model. A revised three-level rate equations that permit a compact and computationally efficient implementation. The electron scattering time, relaxation time and escape time between the corresponding levels are obtained by employing a fully non-equilibrium self-consistent Schrödinger-Poisson analysis of the scattering rate and energy balance equations. A general diode sub-circuit is adopted to model the current-voltage relationship. This new circuit-level model can be readily incorporated into a standard circuit simulation environment such as SPICE, which enables electronic integrated circuit designers to simultaneously evaluate the performance of both QCL and electronic devices.
{"title":"Circuit model of quantum cascade lasers for simulation of influence of doping density","authors":"Chang Qi, Xinzhi Shi, Ye Shuangli, Jinguang Jiang","doi":"10.1109/EDSSC.2013.6628222","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628222","url":null,"abstract":"In this paper, a new equivalent circuit-level model of QCLs is introduced to overcome drawbacks of the previous models. The photon gain coefficient and injection current efficiency both depend on the injector doping density in the model. A revised three-level rate equations that permit a compact and computationally efficient implementation. The electron scattering time, relaxation time and escape time between the corresponding levels are obtained by employing a fully non-equilibrium self-consistent Schrödinger-Poisson analysis of the scattering rate and energy balance equations. A general diode sub-circuit is adopted to model the current-voltage relationship. This new circuit-level model can be readily incorporated into a standard circuit simulation environment such as SPICE, which enables electronic integrated circuit designers to simultaneously evaluate the performance of both QCL and electronic devices.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116596378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628034
N. Yu
Summary form only given. Mobile wireless devices have become a necessity in everyday life, are redefining mobile possibilities for people everywhere, and are enabling significant societal changes. They have also become important product drivers for the semiconductor industry. The product market landscape has been driven by an insatiable demand for data speeds, device features, sleek appearances and increased battery life. By integrating the functionality of the CPU, the GPU, connectivity, multimedia and GPS with optimal performance and power consumption, Qualcomm's chipsets are finding applications in Smartphones as well as other Mobile Computing applications. This talk will outline the key technology elements required in the implementation of Qualcomm's chip sets. The development and cost-effective fabrication of ever more complex chip sets to meet the needs of future products requires increased innovation and integration in critical areas such as architecture, circuit design, process technology and packaging. In addition a continued focus on evolving the successful fabless model and managing cost will be discussed.
{"title":"The future of computing is mobile","authors":"N. Yu","doi":"10.1109/EDSSC.2013.6628034","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628034","url":null,"abstract":"Summary form only given. Mobile wireless devices have become a necessity in everyday life, are redefining mobile possibilities for people everywhere, and are enabling significant societal changes. They have also become important product drivers for the semiconductor industry. The product market landscape has been driven by an insatiable demand for data speeds, device features, sleek appearances and increased battery life. By integrating the functionality of the CPU, the GPU, connectivity, multimedia and GPS with optimal performance and power consumption, Qualcomm's chipsets are finding applications in Smartphones as well as other Mobile Computing applications. This talk will outline the key technology elements required in the implementation of Qualcomm's chip sets. The development and cost-effective fabrication of ever more complex chip sets to meet the needs of future products requires increased innovation and integration in critical areas such as architecture, circuit design, process technology and packaging. In addition a continued focus on evolving the successful fabless model and managing cost will be discussed.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121701096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628215
Tse-Hsu Wu, Jiann-Jong Chen, Yuh-Shyan Hwang
A high-efficiency wide workload hysteresis buck converter using auto selectable frequency-locked techniques is designed with the TSMC 0.18-μm 1P6M process. The proposed buck converter yields fast-response by using hysteresis control. The workload range, power efficiency, and EMI noise problem are improved by auto-selectable frequency and frequency-locked techniques. The selected switching frequency is determined with load current. Simulation results show that this buck converter's switching frequency is locked at four frequencies for the load current between 10 and 400mA: 250k, 500k, 1M, and 2MHz. Furthermore, it achieves more than 90% power efficiency over 95% of the load range, with a peak efficiency of 96.27%.
{"title":"A high-efficiency hysteresis buck converter using auto selectable frequency-locked techniques","authors":"Tse-Hsu Wu, Jiann-Jong Chen, Yuh-Shyan Hwang","doi":"10.1109/EDSSC.2013.6628215","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628215","url":null,"abstract":"A high-efficiency wide workload hysteresis buck converter using auto selectable frequency-locked techniques is designed with the TSMC 0.18-μm 1P6M process. The proposed buck converter yields fast-response by using hysteresis control. The workload range, power efficiency, and EMI noise problem are improved by auto-selectable frequency and frequency-locked techniques. The selected switching frequency is determined with load current. Simulation results show that this buck converter's switching frequency is locked at four frequencies for the load current between 10 and 400mA: 250k, 500k, 1M, and 2MHz. Furthermore, it achieves more than 90% power efficiency over 95% of the load range, with a peak efficiency of 96.27%.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121562674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628173
Zhijin Hu, Congwei Liao, C. Zheng, Shengdong Zhang
A high-speed and reliable TFT integrated shift register for high-resolution display is proposed. By inhibiting the leakage current in pull-up period and enhancing the discharge ability of driving TFT in pull-down period, the operating frequency is improved by 49%. Besides, the proposed circuit is expected to have high reliability due to the lowered gate voltages on the critical TFTs biased through capacitor coupling.
{"title":"A high-speed and reliable TFT integrated shift register","authors":"Zhijin Hu, Congwei Liao, C. Zheng, Shengdong Zhang","doi":"10.1109/EDSSC.2013.6628173","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628173","url":null,"abstract":"A high-speed and reliable TFT integrated shift register for high-resolution display is proposed. By inhibiting the leakage current in pull-up period and enhancing the discharge ability of driving TFT in pull-down period, the operating frequency is improved by 49%. Besides, the proposed circuit is expected to have high reliability due to the lowered gate voltages on the critical TFTs biased through capacitor coupling.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115173619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628174
K. Ho, C. H. Chen, C. Lu, Chao-Sung Lai, Chun Chang, A. Cho, J. Chang, M. Chiang
Electrolyte-insulator-semiconductor (EIS) and Extended-gate Field Effect Transistor (EGFET) devices with programmable HfO2/Si3N4/SiO2 structures are demonstrated for pH detection. The proposed programmable EIS and EGFET sensors with pH sensing membranes exhibit a high pH sensitivity (larger than the ideal Nernstain response, 59.16 mV/pH at 25°C) owing to the hydrogen ions attraction by electrons trapped within the embedded trapping layer(Si3N4) after programming. When compared with the conventional devices, the programmable sensors with programming provide the possibility for the small pH fluctuation detection and can be used in future pH sensor applications owing to its high pH sensing response.
{"title":"Sensitivity enhancement of ion sensors by charge trapping on Extended Gate Field Effect Transistors","authors":"K. Ho, C. H. Chen, C. Lu, Chao-Sung Lai, Chun Chang, A. Cho, J. Chang, M. Chiang","doi":"10.1109/EDSSC.2013.6628174","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628174","url":null,"abstract":"Electrolyte-insulator-semiconductor (EIS) and Extended-gate Field Effect Transistor (EGFET) devices with programmable HfO2/Si3N4/SiO2 structures are demonstrated for pH detection. The proposed programmable EIS and EGFET sensors with pH sensing membranes exhibit a high pH sensitivity (larger than the ideal Nernstain response, 59.16 mV/pH at 25°C) owing to the hydrogen ions attraction by electrons trapped within the embedded trapping layer(Si3N4) after programming. When compared with the conventional devices, the programmable sensors with programming provide the possibility for the small pH fluctuation detection and can be used in future pH sensor applications owing to its high pH sensing response.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133642371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628223
Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu
A novel 24-sided concave-convex geometry monolithic transformer that has high self-resonant frequency and quality factor is presented. It is implemented with the top level thick Cu metal and multiple geometrical structures in 0.13 um CMOS mixed-signal 1P6M salicide back-end process. Compared to those with conventional square, hexagonal and octagonal geometry structure, the novel transformer achieves better quality factor, self-resonant frequency and less chip area. The simulation results show that 1.12, 1 and 0.58 GHz improvements in SRF, and 2.4, 0.9 and 0.3 enhancements in quality factor are obtained respectively when compared to typical square, hexagonal and octagonal transformer with the same inductance of the primary and secondary winding.
提出了一种具有高自谐振频率和高品质因数的24面凹凸几何单片变压器。它是在0.13 um CMOS混合信号1P6M salicide后端工艺中采用顶级厚铜金属和多种几何结构实现的。与传统的方形、六角形和八角形结构的变压器相比，该变压器具有更好的质量因数、自谐振频率和更小的芯片面积。仿真结果表明，与主、次绕组电感相同的典型方形、六角形和八角形变压器相比，SRF分别提高了1.12、1和0.58 GHz，品质因子分别提高了2.4、0.9和0.3。
{"title":"A high self-resonant and quality factor transformer using novel geometry for silicon based RFICs","authors":"Hua-Bin Zhang, M. Cai, Xiao-Yong He, Gui-Hui Chen, Haijun Wu","doi":"10.1109/EDSSC.2013.6628223","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628223","url":null,"abstract":"A novel 24-sided concave-convex geometry monolithic transformer that has high self-resonant frequency and quality factor is presented. It is implemented with the top level thick Cu metal and multiple geometrical structures in 0.13 um CMOS mixed-signal 1P6M salicide back-end process. Compared to those with conventional square, hexagonal and octagonal geometry structure, the novel transformer achieves better quality factor, self-resonant frequency and less chip area. The simulation results show that 1.12, 1 and 0.58 GHz improvements in SRF, and 2.4, 0.9 and 0.3 enhancements in quality factor are obtained respectively when compared to typical square, hexagonal and octagonal transformer with the same inductance of the primary and secondary winding.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133015335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628227
Cejun Wei, Yu Zhu, D. Bartle
Multi-gate pHEMTs are key elements in switch circuits in wireless communication applications due to their low loss and high power capacity with relatively small sizes. A great concern on their high power operation is the power step-back at on-state and at certain power level with harmonics deteriorated. In this paper we discuss the mechanism of power step-back. The power that can pass through an on-state pHEMT is dependent on saturation current, or the maximum available channel current. A premature power step-back or gain collapse in a multi-gate pHEMT is due to largely reduced saturation channel current caused by self-heating in center gate or gates. We developed a self-heating thermal model for multi-gate pHEMTs that can predict power level at that the power step-back and related hysteresis occur.
{"title":"Multi-gate pHEMT modeling for high-power operation","authors":"Cejun Wei, Yu Zhu, D. Bartle","doi":"10.1109/EDSSC.2013.6628227","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628227","url":null,"abstract":"Multi-gate pHEMTs are key elements in switch circuits in wireless communication applications due to their low loss and high power capacity with relatively small sizes. A great concern on their high power operation is the power step-back at on-state and at certain power level with harmonics deteriorated. In this paper we discuss the mechanism of power step-back. The power that can pass through an on-state pHEMT is dependent on saturation current, or the maximum available channel current. A premature power step-back or gain collapse in a multi-gate pHEMT is due to largely reduced saturation channel current caused by self-heating in center gate or gates. We developed a self-heating thermal model for multi-gate pHEMTs that can predict power level at that the power step-back and related hysteresis occur.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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