Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628048
Xiqing Wang, J. Hong, Yandong He, Ganggang Zhang, Lin Han, Xing Zhang
A ring oscillator based structure in digital circuits is presented for measuring NBTI and PBTI effects. The proposed test structure enables simultaneous stress of all devices under tests in either NBTI or PBTI mode and measures frequency degradation or the threshold voltage shift. The threshold voltage shift due to NBTI or PBTI can be directly read out in the proposed circuit which has been designed in a 1.2V, 90nm technology.
{"title":"A ring oscillator based reliability structure for NBTI & PBTI measurement","authors":"Xiqing Wang, J. Hong, Yandong He, Ganggang Zhang, Lin Han, Xing Zhang","doi":"10.1109/EDSSC.2013.6628048","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628048","url":null,"abstract":"A ring oscillator based structure in digital circuits is presented for measuring NBTI and PBTI effects. The proposed test structure enables simultaneous stress of all devices under tests in either NBTI or PBTI mode and measures frequency degradation or the threshold voltage shift. The threshold voltage shift due to NBTI or PBTI can be directly read out in the proposed circuit which has been designed in a 1.2V, 90nm technology.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628167
P. Sirinamaratana, E. Leelarasmee
A DC series connection of photo-voltaic panels in Solar with the converter can b e treated as forming a DC loop. This allows AC current signal to flow and become carrier for data transmission. Circuits that implement this approach are presented. This technique does not require additional wires or radio frequency link.
{"title":"Circuits for data communication through DC power line in solar farm","authors":"P. Sirinamaratana, E. Leelarasmee","doi":"10.1109/EDSSC.2013.6628167","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628167","url":null,"abstract":"A DC series connection of photo-voltaic panels in Solar with the converter can b e treated as forming a DC loop. This allows AC current signal to flow and become carrier for data transmission. Circuits that implement this approach are presented. This technique does not require additional wires or radio frequency link.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125751072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628064
Q. Tao, P. Lai
In this work, we proposed Zn-doped Zr oxynitride (ZrZnON) as a new charge-trapping layer for flash memory applications and investigated its memory characteristics based on the capacitor structure of Al/Al2O3/ZrZnON/SiO2/Si. The high-K dielectric film, ZrON, was used as the control group. The effects of incorporating ZnO in ZrON were studied by comparing the differences of memory properties between the two charge-trapping layers. Measured data showed that the memory device containing ZrZnON had much larger C-V hysteresis window, higher programming/erasing speeds and much better charge retention properties than the one containing ZrON. These improvements should result from charge traps created by ZnO incorporation and deeper quantum wells built by the band-gap alignment of ZrZnON to the SiO2 tunnel layer and Al2O3 blocking layer.
{"title":"Zn-doped Zr oxynitride as charge-trapping layer for flash memory applications","authors":"Q. Tao, P. Lai","doi":"10.1109/EDSSC.2013.6628064","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628064","url":null,"abstract":"In this work, we proposed Zn-doped Zr oxynitride (ZrZnON) as a new charge-trapping layer for flash memory applications and investigated its memory characteristics based on the capacitor structure of Al/Al2O3/ZrZnON/SiO2/Si. The high-K dielectric film, ZrON, was used as the control group. The effects of incorporating ZnO in ZrON were studied by comparing the differences of memory properties between the two charge-trapping layers. Measured data showed that the memory device containing ZrZnON had much larger C-V hysteresis window, higher programming/erasing speeds and much better charge retention properties than the one containing ZrON. These improvements should result from charge traps created by ZnO incorporation and deeper quantum wells built by the band-gap alignment of ZrZnON to the SiO2 tunnel layer and Al2O3 blocking layer.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130172879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628097
Po-Ying Chen, W. Yeh
The effect of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide. The distribution of COPs, measured by optical shallow defect analysis and the use of a particle counter, was compared with the results of time-independent dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) for gate oxides with thicknesses of 2.5 -5 nm. The results reveal no appreciable oxide degradation below an oxide thickness of approximately 3 nm; above this threshold value, the defect density depends strongly on the presence of crystal-originated particles. The COPs are a major factor in the degradation of ultra-thin gate oxide (less than 5 nm) in ULSI devices.
{"title":"Study on the theorem of pits created in 12-inch raw wafering","authors":"Po-Ying Chen, W. Yeh","doi":"10.1109/EDSSC.2013.6628097","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628097","url":null,"abstract":"The effect of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide. The distribution of COPs, measured by optical shallow defect analysis and the use of a particle counter, was compared with the results of time-independent dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) for gate oxides with thicknesses of 2.5 -5 nm. The results reveal no appreciable oxide degradation below an oxide thickness of approximately 3 nm; above this threshold value, the defect density depends strongly on the presence of crystal-originated particles. The COPs are a major factor in the degradation of ultra-thin gate oxide (less than 5 nm) in ULSI devices.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130161001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628054
Y. Liu, J. Yu, F. Cai, W. Tang, P. Lai
In this work, we investigate the static and dynamic gas response of Schottky diode based hydrogen sensor employing a Pt/WO3/n-type Si configuration. The role and importance of tungsten trioxide as an insulating layer within the device is discussed with respect to the measured electronic properties. The WO3 thin films were deposited using RF reactive magnetron sputtering. The surface morphology was studied by an atomic force microscopy (AFM) and the scan results indicated a smooth film with a roughness of 0.18 Å. From the X-ray photoelectron spectroscopy (XPS) characterization, it can be confirmed that the films were stoichiometric WO3 with a thickness of about 4 nm (as measured by an ellipsometer). The I-V characteristics and dynamic response with respect to H2 gas were measured at elevated temperatures from 50°C to 150°C and the results indicate that the H2 sensitivity of this device can exceed approximately 1000 % with an average response time of less than 10 seconds. We discuss and explain these observations in terms of current transportation mechanisms using the thermionic emission model and the change in the Schottky barrier height.
{"title":"A novel hydrogen sensor based on Pt/WO3/Si MIS Schottky diode","authors":"Y. Liu, J. Yu, F. Cai, W. Tang, P. Lai","doi":"10.1109/EDSSC.2013.6628054","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628054","url":null,"abstract":"In this work, we investigate the static and dynamic gas response of Schottky diode based hydrogen sensor employing a Pt/WO3/n-type Si configuration. The role and importance of tungsten trioxide as an insulating layer within the device is discussed with respect to the measured electronic properties. The WO3 thin films were deposited using RF reactive magnetron sputtering. The surface morphology was studied by an atomic force microscopy (AFM) and the scan results indicated a smooth film with a roughness of 0.18 Å. From the X-ray photoelectron spectroscopy (XPS) characterization, it can be confirmed that the films were stoichiometric WO3 with a thickness of about 4 nm (as measured by an ellipsometer). The I-V characteristics and dynamic response with respect to H2 gas were measured at elevated temperatures from 50°C to 150°C and the results indicate that the H2 sensitivity of this device can exceed approximately 1000 % with an average response time of less than 10 seconds. We discuss and explain these observations in terms of current transportation mechanisms using the thermionic emission model and the change in the Schottky barrier height.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628207
D. Zhao, Jun He, Xian Huang, Li Zhang, Fang Yang, Dacheng Zhang
In this work, a monolithic integrated MEMS resonator was fabricated and tested. Surface micromachining method was employed to fabricate the cantilever MEMS resonator after a standard 3 μm CMOS process. The wet release method with dilute HF solution was chosen and compared to the anhydrous HF vapor release process. A release-monitoring structure with polysilicon/Au cantilever array was used to determine the corrosion time of the sacrificial material. Results showed that the MOSFETs function well after proposed release process.
{"title":"Fabrication of monolithic integrated MEMS resonator with wet-release-monitoring array","authors":"D. Zhao, Jun He, Xian Huang, Li Zhang, Fang Yang, Dacheng Zhang","doi":"10.1109/EDSSC.2013.6628207","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628207","url":null,"abstract":"In this work, a monolithic integrated MEMS resonator was fabricated and tested. Surface micromachining method was employed to fabricate the cantilever MEMS resonator after a standard 3 μm CMOS process. The wet release method with dilute HF solution was chosen and compared to the anhydrous HF vapor release process. A release-monitoring structure with polysilicon/Au cantilever array was used to determine the corrosion time of the sacrificial material. Results showed that the MOSFETs function well after proposed release process.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628238
Vikash Kumar, A. Aminulloh, Shao-Ming Yang, G. Sheu
A circuit analysis is introduced to detect the value of the substrate resistance and the capacitance, which is mainly caused by p-n junction diode. The effect of the substrate resistance on RF application is reported in this paper. When trench number increases the substrate resistance decreases. Effect of the inductance on the capacitor is also investigated. The inductance should be low value in the high frequency range to minimize inductance effect for Radio Frequency (RF) application. A two-port admittance parameter is used to extract the value of capacitance, inductance and substrate resistance.
{"title":"Investigation of substrate resistance and inductance on deep trench capacitor for RF application","authors":"Vikash Kumar, A. Aminulloh, Shao-Ming Yang, G. Sheu","doi":"10.1109/EDSSC.2013.6628238","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628238","url":null,"abstract":"A circuit analysis is introduced to detect the value of the substrate resistance and the capacitance, which is mainly caused by p-n junction diode. The effect of the substrate resistance on RF application is reported in this paper. When trench number increases the substrate resistance decreases. Effect of the inductance on the capacitor is also investigated. The inductance should be low value in the high frequency range to minimize inductance effect for Radio Frequency (RF) application. A two-port admittance parameter is used to extract the value of capacitance, inductance and substrate resistance.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125965903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628077
Jun Shi, Lianming Li, T. Cui
This paper presents a 60 GHz broadband Gilbert-cell down conversion mixer in a 65 nm CMOS. To enhance the mixer gain, bandwidth, and noise performance, an inter-stage inductor is introduced between the switching pair and the transconductance stage. Driven by a 48 GHz 0-dBm LO, the mixer achieves a conversion gain of 14 dB. The measured IF 3dB bandwidth is about 4GHz and the input 1dB compression point is about -10dBm. Besides, simulation results show that the noise figure is lower than 12 dB and the input referred IP3 point is about 2.5 dBm. The mixer draws 11mA (Gilbert-cell) and 21mA (IF buffer) from a 1.2V supply.
{"title":"A 60-GHz broadband Gilbert-cell down conversion mixer in a 65-nm CMOS","authors":"Jun Shi, Lianming Li, T. Cui","doi":"10.1109/EDSSC.2013.6628077","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628077","url":null,"abstract":"This paper presents a 60 GHz broadband Gilbert-cell down conversion mixer in a 65 nm CMOS. To enhance the mixer gain, bandwidth, and noise performance, an inter-stage inductor is introduced between the switching pair and the transconductance stage. Driven by a 48 GHz 0-dBm LO, the mixer achieves a conversion gain of 14 dB. The measured IF 3dB bandwidth is about 4GHz and the input 1dB compression point is about -10dBm. Besides, simulation results show that the noise figure is lower than 12 dB and the input referred IP3 point is about 2.5 dBm. The mixer draws 11mA (Gilbert-cell) and 21mA (IF buffer) from a 1.2V supply.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628205
Gaobo Xu, Qiuxia Xu, H. Yin, Huajie Zhou, Tao Yang, J. Niu, Lingkuan Meng, Xiaobin He, Guilei Wang, Yu Jiahan, Dahai Wang, Junfeng Li, Jiang Yan, Chao Zhao, Dapeng Chen
HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.
{"title":"High-quality HfSiON gate dielectric and its application in a gate-last NMOSFET fabrication","authors":"Gaobo Xu, Qiuxia Xu, H. Yin, Huajie Zhou, Tao Yang, J. Niu, Lingkuan Meng, Xiaobin He, Guilei Wang, Yu Jiahan, Dahai Wang, Junfeng Li, Jiang Yan, Chao Zhao, Dapeng Chen","doi":"10.1109/EDSSC.2013.6628205","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628205","url":null,"abstract":"HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125321087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628204
A. Zjajo
This paper reports design, efficiency and measurement results of time interleaved sample and hold circuit based on closed loop switched capacitor technique. The prototype sample and hold with 84 dB dynamic range at 120 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 8 mW at 1.2 V power supply and measures 0.22 mm2.
{"title":"A 1.2V 84dB 8mW time-interleaved sample and hold circuit in 90 nm CMOS","authors":"A. Zjajo","doi":"10.1109/EDSSC.2013.6628204","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628204","url":null,"abstract":"This paper reports design, efficiency and measurement results of time interleaved sample and hold circuit based on closed loop switched capacitor technique. The prototype sample and hold with 84 dB dynamic range at 120 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 8 mW at 1.2 V power supply and measures 0.22 mm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128776638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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