Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628142
Jing Xue, K. Ngo, Hoi Lee
A zero-voltage-switching (ZVS) boost converter using normally-off GaN power transistors and an on-chip gate driver are presented in this paper. The ZVS and adaptive dead-time control are developed to minimize the capacitive switching loss and body-diode recovery loss of the boost converter. Both high-side and low-side gate drivers provide ~6.8-ns propagation delays and ~2-ns rise/fall time, enabling MHz operation of the converter. With the proposed on-chip adaptive dead-time controlled gate drivers implemented in a 0.35-μm high-voltage CMOS process and 600-V normally-off GaN power transistors, the proposed 400-V ZVS boost converter delivers an output power of 1.6 kW and achieves a peak power efficiency of 99.2% at 1-MHz switching frequency.
介绍了一种采用常关式GaN功率晶体管和片上栅极驱动器的零电压开关(ZVS)升压变换器。为了减小升压变换器的电容开关损耗和体二极管恢复损耗，提出了ZVS和自适应死区时间控制。高侧和低侧栅极驱动器都提供~6.8 ns的传播延迟和~2 ns的上升/下降时间，使转换器能够在MHz范围内工作。采用0.35 μm高压CMOS工艺和600 v常关GaN功率晶体管实现片上自适应死区控制栅极驱动器，400 v ZVS升压转换器在1 mhz开关频率下输出功率为1.6 kW，峰值功率效率为99.2%。
{"title":"A 99%-efficiency 1-MHz 1.6-kW zero-voltage-switching boost converter using normally-off GaN power transistors and adaptive dead-time controlled gate drivers","authors":"Jing Xue, K. Ngo, Hoi Lee","doi":"10.1109/EDSSC.2013.6628142","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628142","url":null,"abstract":"A zero-voltage-switching (ZVS) boost converter using normally-off GaN power transistors and an on-chip gate driver are presented in this paper. The ZVS and adaptive dead-time control are developed to minimize the capacitive switching loss and body-diode recovery loss of the boost converter. Both high-side and low-side gate drivers provide ~6.8-ns propagation delays and ~2-ns rise/fall time, enabling MHz operation of the converter. With the proposed on-chip adaptive dead-time controlled gate drivers implemented in a 0.35-μm high-voltage CMOS process and 600-V normally-off GaN power transistors, the proposed 400-V ZVS boost converter delivers an output power of 1.6 kW and achieves a peak power efficiency of 99.2% at 1-MHz switching frequency.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628085
W. Lau, O. Wong, H. Wong
It has been difficult to distinguish whether the leakage current mechanism is Schottky emission or Poole-Frenkel effect for high-k capacitors. We would like to point out that the two mechanisms can be combined into a unified theory as illustrated by some examples involving hafnium oxide capacitors.
{"title":"Some examples of the application of a unified Schottky-Poole-Frenkel theory to high-k dielectric capacitor structures","authors":"W. Lau, O. Wong, H. Wong","doi":"10.1109/EDSSC.2013.6628085","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628085","url":null,"abstract":"It has been difficult to distinguish whether the leakage current mechanism is Schottky emission or Poole-Frenkel effect for high-k capacitors. We would like to point out that the two mechanisms can be combined into a unified theory as illustrated by some examples involving hafnium oxide capacitors.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126111578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628047
Md Nur Kutubul Alam, M. Islam, Md.R. Islam
In1-xGaxSb XOI nFET is proposed and its capacitance-voltage (CV) characteristics are investigated. One dimensional coupled Schrödinger-Poisson equation is solved to calculate charge and hence to the capacitance. Well known SILVACO's ATLAS device simulation package is used to carry out the simulation. It is found that the CV characteristic as well as the threshold voltage of the proposed device depend on different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness, and operating temperature. Doping dependent threshold voltage shift is related with maximum allowable doping level, and which is also important for understanding enhancement mode operation.
{"title":"Self-consistent quasi-static C-V characteristics of In1−xGaxSb XOI FET","authors":"Md Nur Kutubul Alam, M. Islam, Md.R. Islam","doi":"10.1109/EDSSC.2013.6628047","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628047","url":null,"abstract":"In1-xGaxSb XOI nFET is proposed and its capacitance-voltage (CV) characteristics are investigated. One dimensional coupled Schrödinger-Poisson equation is solved to calculate charge and hence to the capacitance. Well known SILVACO's ATLAS device simulation package is used to carry out the simulation. It is found that the CV characteristic as well as the threshold voltage of the proposed device depend on different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness, and operating temperature. Doping dependent threshold voltage shift is related with maximum allowable doping level, and which is also important for understanding enhancement mode operation.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628050
Y. Hou, B. Chen, B. Gao, Z. Lun, Z. Xin, R. Liu, L. Liu, D. Han, Y. Wang, X. Liu, J. Kang
TiN/HfOx/Al/Pt resistive switching random access memory (RRAM) devices were fabricated and investigated. The HfOx based RRAM with Al inserted layer showed bipolar resistive switching phenomenon. As a result of the improvement of uniformity contributed by Al atoms' diffusion into HfOx film, robust self-compliance multilevel operation during set and reset process was reported. The possible mechanism was also discussed.
{"title":"Self-compliance multilevel resistive switching characteristics in TiN/HfOx/Al/Pt RRAM devices","authors":"Y. Hou, B. Chen, B. Gao, Z. Lun, Z. Xin, R. Liu, L. Liu, D. Han, Y. Wang, X. Liu, J. Kang","doi":"10.1109/EDSSC.2013.6628050","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628050","url":null,"abstract":"TiN/HfOx/Al/Pt resistive switching random access memory (RRAM) devices were fabricated and investigated. The HfOx based RRAM with Al inserted layer showed bipolar resistive switching phenomenon. As a result of the improvement of uniformity contributed by Al atoms' diffusion into HfOx film, robust self-compliance multilevel operation during set and reset process was reported. The possible mechanism was also discussed.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124933577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628194
K. Chou, Chun‐Hu Cheng, A. Chin
We report a resistive random-access memory (RRAM) using stacked GeO2 and PZT. Under unipolar mode operation, the Ni/GeO2/PZT/TaN RRAM shows a good DC cycling of 2×103 cycles, 85°C retention, and large resistance window about 120x, which is better than that shown by the single-layer Ni/PZT/TaN RRAM without the covalent-bond-dielectric GeO2.
{"title":"GeO2/PZT resistive random access memory devices with Ni electrode","authors":"K. Chou, Chun‐Hu Cheng, A. Chin","doi":"10.1109/EDSSC.2013.6628194","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628194","url":null,"abstract":"We report a resistive random-access memory (RRAM) using stacked GeO<sub>2</sub> and PZT. Under unipolar mode operation, the Ni/GeO<sub>2</sub>/PZT/TaN RRAM shows a good DC cycling of 2×10<sup>3</sup> cycles, 85°C retention, and large resistance window about 120x, which is better than that shown by the single-layer Ni/PZT/TaN RRAM without the covalent-bond-dielectric GeO<sub>2</sub>.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124414239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628106
Xiarong Hu, Bo Zhang, X. Luo, Yongheng Jiang, K. Zhou, Zhaoji Li
An analytical model for the extended field plate effect on trench LDMOS with high-k permittivity is presented in this paper. The RESURF criterion for the trench LDMOS with extended field plate is derived, both analytical and numerical results show the drift doping is increased with high-k dielectric layer. The analysis of the breakdown mechanism is researched, and an optimal design is achieved that the voltage supported by dielectric layer is equal to the voltage supported by the drift region. The relative dielectric coefficient of high-k materials are in the range of 4~12 when the thickness of the dielectric layer is below 600nm. The breakdown voltage is decreased for a too high permittivity of the high-k material.
{"title":"Analytical model for an extended field plate effect on trench LDMOS with high-k permittivity","authors":"Xiarong Hu, Bo Zhang, X. Luo, Yongheng Jiang, K. Zhou, Zhaoji Li","doi":"10.1109/EDSSC.2013.6628106","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628106","url":null,"abstract":"An analytical model for the extended field plate effect on trench LDMOS with high-k permittivity is presented in this paper. The RESURF criterion for the trench LDMOS with extended field plate is derived, both analytical and numerical results show the drift doping is increased with high-k dielectric layer. The analysis of the breakdown mechanism is researched, and an optimal design is achieved that the voltage supported by dielectric layer is equal to the voltage supported by the drift region. The relative dielectric coefficient of high-k materials are in the range of 4~12 when the thickness of the dielectric layer is below 600nm. The breakdown voltage is decreased for a too high permittivity of the high-k material.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123499633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an improved double delta sampling (DDS) circuit and the architecture and readout sequence are introduced in detail. Meanwhile, a new method to evaluate the Fixed Pattern Noise (FPN) cancellation for readout circuit before fabricated is proposed. Thus, we can evaluate DDS or other readout circuit in another view. Compared with the conventional DDS circuit, the new architecture is better overall performance. Simulation results indicate the improved DDS circuit can achieve SNR (Signal Noise Ratio) of 72.12 dB and SFDR (Spurious Free Dynamic Range) of 73.39 dB with a sampling frequency of 10MHz. Through the proposed method, we calculated that the level of FPN cancellation achieves 11.6 bits on average and 15.2 bits on maximum.
{"title":"The analyze and design of low FPN double delta sampling circuit for CMOS image sensor","authors":"Xiaohui Liu, Yuanfu Zhao, Liyan Liu, Xiaofeng Jin, Chunfang Wang, Yue Zhao","doi":"10.1109/EDSSC.2013.6628186","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628186","url":null,"abstract":"This paper presents an improved double delta sampling (DDS) circuit and the architecture and readout sequence are introduced in detail. Meanwhile, a new method to evaluate the Fixed Pattern Noise (FPN) cancellation for readout circuit before fabricated is proposed. Thus, we can evaluate DDS or other readout circuit in another view. Compared with the conventional DDS circuit, the new architecture is better overall performance. Simulation results indicate the improved DDS circuit can achieve SNR (Signal Noise Ratio) of 72.12 dB and SFDR (Spurious Free Dynamic Range) of 73.39 dB with a sampling frequency of 10MHz. Through the proposed method, we calculated that the level of FPN cancellation achieves 11.6 bits on average and 15.2 bits on maximum.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122466792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628062
Chio-in Ieong, Mingzhong Li, M. Law, Pu Mak, M. Vai, P. Mak, F. Wan, R. Martins
This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V.
{"title":"Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications","authors":"Chio-in Ieong, Mingzhong Li, M. Law, Pu Mak, M. Vai, P. Mak, F. Wan, R. Martins","doi":"10.1109/EDSSC.2013.6628062","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628062","url":null,"abstract":"This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628122
Hualin Cai, Changjian Zhou, Yihan Zhang, Yi Yang, T. Ren, Cangran Guo, Jing Liu
In this paper, a Surface Acoustic Wave (SAW) biosensor with gold coated delay area detecting DNA sequences is proposed. By well-designed procedures of device structure and parameters, we manufactured a simple and high-performance SAW on LiNbO3 substrate. The SAW biosensor with gold delay area that is connected to PCB board through bonding wires could be used for the direct measurement and sonic path comparative measurement of S11 parameter by using Network Analyzer. The device works near 65MHz. The loading mass of DNA probe and target DNA sequences are obtained from frequency shift, which is big enough in this work due to an effective biological treatment method. The testing result shows that the SAW sensor has a high sensitivity of 1.2pg/ml/Hz.
{"title":"SAW based mass-loading biosensor for DNA detection","authors":"Hualin Cai, Changjian Zhou, Yihan Zhang, Yi Yang, T. Ren, Cangran Guo, Jing Liu","doi":"10.1109/EDSSC.2013.6628122","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628122","url":null,"abstract":"In this paper, a Surface Acoustic Wave (SAW) biosensor with gold coated delay area detecting DNA sequences is proposed. By well-designed procedures of device structure and parameters, we manufactured a simple and high-performance SAW on LiNbO3 substrate. The SAW biosensor with gold delay area that is connected to PCB board through bonding wires could be used for the direct measurement and sonic path comparative measurement of S11 parameter by using Network Analyzer. The device works near 65MHz. The loading mass of DNA probe and target DNA sequences are obtained from frequency shift, which is big enough in this work due to an effective biological treatment method. The testing result shows that the SAW sensor has a high sensitivity of 1.2pg/ml/Hz.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628163
S. Salahuddin, Hailong Jiao, V. Kursun
Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors are evaluated in this paper under process parameter fluctuations. The strengths of the asymmetrical bitline access transistors are weakened during read operations and enhanced during write operations as the direction of current flow is reversed. The average read static noise margin of the statistical samples with the asymmetrical memory cells is up to 75.8% higher as compared to the standard symmetrical six-FinFET SRAM cell under process parameter fluctuations. Furthermore, the average leakage power consumption with the asymmetrical memory cells is reduced by up to 19% as compared to the standard symmetrical six-FinFET SRAM cell under process variations in a 15nm FinFET technology.
{"title":"Characterization of FinFET SRAM cells with asymmetrically gate underlapped bitline access transistors under process parameter fluctuations","authors":"S. Salahuddin, Hailong Jiao, V. Kursun","doi":"10.1109/EDSSC.2013.6628163","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628163","url":null,"abstract":"Two new six-FinFET memory circuits with asymmetrically gate underlapped bitline access transistors are evaluated in this paper under process parameter fluctuations. The strengths of the asymmetrical bitline access transistors are weakened during read operations and enhanced during write operations as the direction of current flow is reversed. The average read static noise margin of the statistical samples with the asymmetrical memory cells is up to 75.8% higher as compared to the standard symmetrical six-FinFET SRAM cell under process parameter fluctuations. Furthermore, the average leakage power consumption with the asymmetrical memory cells is reduced by up to 19% as compared to the standard symmetrical six-FinFET SRAM cell under process variations in a 15nm FinFET technology.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131462529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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