Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628208
Qing Lei, Zhaohui Wu, Bin Li, Haijun Wu
In this paper, a digital background error-correction technique for pipelined successive approximation analogue-to-digital converter (SAR ADC) based on Least Mean Square (LMS) algorithm is presented. This technique uses a slow but accurate ADC as a reference ADC and combines with LMS algorithm to calibrate the capacitor mismatch, gain error, reference voltage offset error of the inaccurate pipelined SAR ADC. The simulation validates the effectiveness of this technique for a pipelined SAR ADC with 16 bit resolution. The effective number of bits(ENOB) is improved from 10.31 bits to 15.66 bits.
{"title":"Digital background calibration for pipelined SAR ADC based on LMS algorithm","authors":"Qing Lei, Zhaohui Wu, Bin Li, Haijun Wu","doi":"10.1109/EDSSC.2013.6628208","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628208","url":null,"abstract":"In this paper, a digital background error-correction technique for pipelined successive approximation analogue-to-digital converter (SAR ADC) based on Least Mean Square (LMS) algorithm is presented. This technique uses a slow but accurate ADC as a reference ADC and combines with LMS algorithm to calibrate the capacitor mismatch, gain error, reference voltage offset error of the inaccurate pipelined SAR ADC. The simulation validates the effectiveness of this technique for a pipelined SAR ADC with 16 bit resolution. The effective number of bits(ENOB) is improved from 10.31 bits to 15.66 bits.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628201
Haijun Wu, Bin Li, Huabin Zhang, Linli Zou, Longyue Zeng, Zhengpin Li
A 1.2 V 16-bit 2-2 mash delta-sigma analog-to-digital converter (ADC) for temperature sensor or audio application is implemented. For power saving, three methods are used to adjust the ADC's consumption. The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the OSR in order to change the dynamic power consumption and then ADC's dynamic performance could be changed. Besides, the key block's bias current could be minimized in order to save the static power according to the specific application. The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm2 and a power of 5.2 mW. The measurement results show that the DR of the proposed ADC can change from 95dB to 67dB with the configurable OSR from 1024 to 32. The spurious free dynamic range and signal-to-noise distortion ratio can get 99dB and 86.5 dB, respectively.
{"title":"A 1.2V power adaptable 95-to-67dB DR 2-2 mash delta-sigma ADC with configurable OSR","authors":"Haijun Wu, Bin Li, Huabin Zhang, Linli Zou, Longyue Zeng, Zhengpin Li","doi":"10.1109/EDSSC.2013.6628201","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628201","url":null,"abstract":"A 1.2 V 16-bit 2-2 mash delta-sigma analog-to-digital converter (ADC) for temperature sensor or audio application is implemented. For power saving, three methods are used to adjust the ADC's consumption. The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the OSR in order to change the dynamic power consumption and then ADC's dynamic performance could be changed. Besides, the key block's bias current could be minimized in order to save the static power according to the specific application. The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm2 and a power of 5.2 mW. The measurement results show that the DR of the proposed ADC can change from 95dB to 67dB with the configurable OSR from 1024 to 32. The spurious free dynamic range and signal-to-noise distortion ratio can get 99dB and 86.5 dB, respectively.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124647646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628121
Yujuan He, Yuan Liu, Xiaolan Zhou
Total ionizing dose irradiation effect in NMOS Devices with 0.18μm, 0.35μm and 1μm feature size was studied. Due to the thickness of gate oxide, radiation threshold voltage induced by total dose irradiation became lower as feature size increased. But the leakage current of NMOS devices induced by TID irradiation increased obviously because of trench sidewall leakage.
{"title":"Feature size dependence of total dose effects in the irradiated NMOS devices","authors":"Yujuan He, Yuan Liu, Xiaolan Zhou","doi":"10.1109/EDSSC.2013.6628121","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628121","url":null,"abstract":"Total ionizing dose irradiation effect in NMOS Devices with 0.18μm, 0.35μm and 1μm feature size was studied. Due to the thickness of gate oxide, radiation threshold voltage induced by total dose irradiation became lower as feature size increased. But the leakage current of NMOS devices induced by TID irradiation increased obviously because of trench sidewall leakage.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130536192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a backside silicon-embedded inductor (BSEI) using a magnetic layer is proposed and studied for magnetic flux shielding and inductance enhancement. With the magnetic layer, the magnetic flux that goes under the BSEI chip is reduced by 2 to 3 times, and consequently the significant BSEI performance degradation in presence of a Cu die pad is effectively suppressed. The inductance of the BSEI is also enhanced by 30% with the magnetic layer. This makes the BSEI more promising for power supply-on-chip applications.
{"title":"Backside silicon-embedded inductor using magnetic layer for shielding and inductance enhancement","authors":"Rongxiang Wu, Wei Li, Yong Ren, Heping Luo, Guojun Zhang","doi":"10.1109/EDSSC.2013.6628231","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628231","url":null,"abstract":"In this paper, a backside silicon-embedded inductor (BSEI) using a magnetic layer is proposed and studied for magnetic flux shielding and inductance enhancement. With the magnetic layer, the magnetic flux that goes under the BSEI chip is reduced by 2 to 3 times, and consequently the significant BSEI performance degradation in presence of a Cu die pad is effectively suppressed. The inductance of the BSEI is also enhanced by 30% with the magnetic layer. This makes the BSEI more promising for power supply-on-chip applications.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130607352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628046
M. N. Alam, M. Islam, Md.R. Islam
Self consistent quasi-static capacitance-voltage (CV) characteristics of InAsSb XOI nFET are investigated. Well known SILVACO's ATLAS device simulation package is used to solve one dimensional coupled Schrödinger-Poisson equation by correlating Fermi function and carrier concentration with growth co-ordinates. It is found that device operating temperature and different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness have strong influence on CV profiles and threshold voltage. It is also reported that there is a limit of doping concentration and channel thickness to ensure enhancement mode operation.
{"title":"Capacitance-Voltage characterization of InAsySb1−y XOI FET","authors":"M. N. Alam, M. Islam, Md.R. Islam","doi":"10.1109/EDSSC.2013.6628046","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628046","url":null,"abstract":"Self consistent quasi-static capacitance-voltage (CV) characteristics of InAsSb XOI nFET are investigated. Well known SILVACO's ATLAS device simulation package is used to solve one dimensional coupled Schrödinger-Poisson equation by correlating Fermi function and carrier concentration with growth co-ordinates. It is found that device operating temperature and different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness have strong influence on CV profiles and threshold voltage. It is also reported that there is a limit of doping concentration and channel thickness to ensure enhancement mode operation.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628125
M. Muhamad, N. Soin, H. Ramiah, N. Noh, W. Chong
This paper present design and simulation of differential low noise amplifier that utilized inductively degenerated common-source (CS) open drain cascode topology. The operating frequency for the design was at 2.4GHz for IEEE 802.11b standard. The LNA has been implemented in RF 0.13um CMOS process. Power constraint noise optimization method has been used to obtain the optimized width of the transistor with a low noise figure and good power gain. Post layout simulation provides a forward gain (S21) of 18.56dB, S11 of -27.63dB with a noise figure (NF) of 1.85dB and IIP3 = -7.75. The total current consumed by the circuit is 7.59mA thus making the power consumption is 9mW.
{"title":"Design of CMOS differential LNA at 2.4GHz","authors":"M. Muhamad, N. Soin, H. Ramiah, N. Noh, W. Chong","doi":"10.1109/EDSSC.2013.6628125","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628125","url":null,"abstract":"This paper present design and simulation of differential low noise amplifier that utilized inductively degenerated common-source (CS) open drain cascode topology. The operating frequency for the design was at 2.4GHz for IEEE 802.11b standard. The LNA has been implemented in RF 0.13um CMOS process. Power constraint noise optimization method has been used to obtain the optimized width of the transistor with a low noise figure and good power gain. Post layout simulation provides a forward gain (S21) of 18.56dB, S11 of -27.63dB with a noise figure (NF) of 1.85dB and IIP3 = -7.75. The total current consumed by the circuit is 7.59mA thus making the power consumption is 9mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126685331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628190
R. Shi, X. Huang, C. Leung, P. Lai
The charge-trapping properties of niobium-doped La2O3 have been investigated based on MONOS capacitors. The memory device with niobium-doped La2O3 CTL shows better characteristics than that with pure La2O3 CTL in memory window and P/E properties. It also shows good retention characteristics. Therefore, the niobium-doped La2O3 is a promising candidate as CTL for nonvolatile memory applications.
{"title":"Charge-trapping characteristics of niobium-doped La2O3 for nonvolatile memory applications","authors":"R. Shi, X. Huang, C. Leung, P. Lai","doi":"10.1109/EDSSC.2013.6628190","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628190","url":null,"abstract":"The charge-trapping properties of niobium-doped La<sub>2</sub>O<sub>3</sub> have been investigated based on MONOS capacitors. The memory device with niobium-doped La<sub>2</sub>O<sub>3</sub> CTL shows better characteristics than that with pure La<sub>2</sub>O<sub>3</sub> CTL in memory window and P/E properties. It also shows good retention characteristics. Therefore, the niobium-doped La<sub>2</sub>O<sub>3</sub> is a promising candidate as CTL for nonvolatile memory applications.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126774778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628089
L. Qian, P. Lai
In this work, the influence of Ar/O2 ratio during InGaZnO (IGZO) deposition on the electrical characteristics of a-IGZO thin-film transistor (TFT) with HfLaO gate dielectric has been investigated. It is found that lowering the oxygen concentration in the a-IGZO sputtering ambient can effectively improve the device performance, including carrier mobility (μsat), threshold voltage (Vth), sub-threshold slope (SS) and on-off current ratio (Ion/Ioff). Moreover, the hysteresis (ΔVH) of the transfer characteristics of the device under forward and reverse sweepings of gate bias voltage can be suppressed, and improvement on its low-frequency noise properties has been found for lower oxygen concentration in the sputtering ambient. As a result, a high saturation mobility of 12.5 cm2/Vs, a low sub-threshold slope of 0.260 V/dec and a small Hooge's parameter (αH) of 0.4 have been achieved for the sample with an Ar/O2 ratio of 24 sccm/1 sccm. All these improvements can be ascribed to the fact that more oxygen vacancies exist in the a-IGZO film deposited in an ambient with less oxygen. These positively-charged oxygen vacancies can induce a higher electron concentration in the a-IGZO film and thus fill up more electron traps at the interface between a-IGZO and HtLaO.
{"title":"Influence of Ar/O2 ratio during IGZO deposition on the electrical characteristics of a-IGZO TFT with HfLaO gate dielectric","authors":"L. Qian, P. Lai","doi":"10.1109/EDSSC.2013.6628089","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628089","url":null,"abstract":"In this work, the influence of Ar/O2 ratio during InGaZnO (IGZO) deposition on the electrical characteristics of a-IGZO thin-film transistor (TFT) with HfLaO gate dielectric has been investigated. It is found that lowering the oxygen concentration in the a-IGZO sputtering ambient can effectively improve the device performance, including carrier mobility (μsat), threshold voltage (Vth), sub-threshold slope (SS) and on-off current ratio (Ion/Ioff). Moreover, the hysteresis (ΔVH) of the transfer characteristics of the device under forward and reverse sweepings of gate bias voltage can be suppressed, and improvement on its low-frequency noise properties has been found for lower oxygen concentration in the sputtering ambient. As a result, a high saturation mobility of 12.5 cm2/Vs, a low sub-threshold slope of 0.260 V/dec and a small Hooge's parameter (αH) of 0.4 have been achieved for the sample with an Ar/O2 ratio of 24 sccm/1 sccm. All these improvements can be ascribed to the fact that more oxygen vacancies exist in the a-IGZO film deposited in an ambient with less oxygen. These positively-charged oxygen vacancies can induce a higher electron concentration in the a-IGZO film and thus fill up more electron traps at the interface between a-IGZO and HtLaO.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121540026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628094
Guannan Wang, Wengao Lu, Yacong Zhang, Zhongjian Chen, L. Ji
To meet the interest in low power, low cost and small volume, uncooled Infrared Focal Plane Array(IRFPA) and Readout Integrated Circuit(ROIC) with ADC are both emphases for the third generation IRFPA. This paper presents a prototype verification of ROIC with a 14-bit column-level ADC for pyroelectric array. The architecture of ADC is not sensitive to comparator's delay. Therefore, low power and low noise design can be achieved. A prototype of ROIC with column-level ADC is implemented with a 0.5μm DPTM process. And the circuit can be expended to 384×288 array operating at 60Hz. The current of each column ADC is about 6μA.
{"title":"A prototype of ROIC for pyroelectric uncooled IRFPA with colume-level ADC","authors":"Guannan Wang, Wengao Lu, Yacong Zhang, Zhongjian Chen, L. Ji","doi":"10.1109/EDSSC.2013.6628094","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628094","url":null,"abstract":"To meet the interest in low power, low cost and small volume, uncooled Infrared Focal Plane Array(IRFPA) and Readout Integrated Circuit(ROIC) with ADC are both emphases for the third generation IRFPA. This paper presents a prototype verification of ROIC with a 14-bit column-level ADC for pyroelectric array. The architecture of ADC is not sensitive to comparator's delay. Therefore, low power and low noise design can be achieved. A prototype of ROIC with column-level ADC is implemented with a 0.5μm DPTM process. And the circuit can be expended to 384×288 array operating at 60Hz. The current of each column ADC is about 6μA.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122552247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628087
Y. Teh, P. Mok
This paper presents a coupled inductor-based converter capable of self-starting and has consistent conversion efficiency independent of input voltage and source resistance. Instead of using a customized high turns-ratio miniature transformer, existing compact profile pulse transformer commonly available for telecommunication circuits can be used. Simulation results with a standard CMOS 0.13-μm technology confirmed that using the proposed topology, power conversion efficiency can be improved to over 60% and is sustainable over wide input voltage range.
{"title":"Design of coupled inductor-based boost converter for ultra low power thermoelectric energy harvesting using pulse transformer with 75mV start-up voltage","authors":"Y. Teh, P. Mok","doi":"10.1109/EDSSC.2013.6628087","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628087","url":null,"abstract":"This paper presents a coupled inductor-based converter capable of self-starting and has consistent conversion efficiency independent of input voltage and source resistance. Instead of using a customized high turns-ratio miniature transformer, existing compact profile pulse transformer commonly available for telecommunication circuits can be used. Simulation results with a standard CMOS 0.13-μm technology confirmed that using the proposed topology, power conversion efficiency can be improved to over 60% and is sustainable over wide input voltage range.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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