Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147724
S. Isukapati, S. Jang, Woongje Sung
This paper demonstrates and presents an enhanced design architecture to suppress the leakage from the high-voltage (HV) lateral MOSFETs in 4H-SiC. The demonstrated MOSFETs were fabricated on an N-epi/P-epi/N+ substrate. A comparative analysis was conducted between the performance of the improved design architecture and the conventional architecture, and the outcomes exhibit a notable decrease in the magnitude of the leakage current. The proposed device architecture possesses the capability to effectively fulfill the design specifications of a durable lateral power MOSFET to be used in silicon carbide (SiC) power integrated circuits (ICs).
{"title":"Enhanced Design Architecture to Suppress Leakage Current of High-Voltage (HV) Lateral nMOSFETs in 4H-SiC","authors":"S. Isukapati, S. Jang, Woongje Sung","doi":"10.1109/ISPSD57135.2023.10147724","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147724","url":null,"abstract":"This paper demonstrates and presents an enhanced design architecture to suppress the leakage from the high-voltage (HV) lateral MOSFETs in 4H-SiC. The demonstrated MOSFETs were fabricated on an N-epi/P-epi/N+ substrate. A comparative analysis was conducted between the performance of the improved design architecture and the conventional architecture, and the outcomes exhibit a notable decrease in the magnitude of the leakage current. The proposed device architecture possesses the capability to effectively fulfill the design specifications of a durable lateral power MOSFET to be used in silicon carbide (SiC) power integrated circuits (ICs).","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134410655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147409
Elizabeth Kho Ching Tee, M. Antoniou, D. Green, A. Hölke, F. Udrea
This paper investigates novel techniques of extending the breakdown voltage (BDS) capability of the partial silicon-on-insulator SJ LDNMOS up to 460V. This is based on a unique combination of two different concepts and technologies, namely the Partial Silicon-On-Insulator (PSOI) and Superjunction (SJ) to achieve a highly effective platform for Power Integrated Circuit. The device BDS sensitivity to the handle wafer diode voltage is mitigated by using a novel 3D design based on “domain decomposition” 3D TCAD simulations. The hot spot location in the complex termination area, which is due to out-of-plane (90°) bending of electrostatic potential lines towards the midpoint of the device area, is successfully identified and eliminated.
{"title":"3D simulation study of 375V partial SOI SJ LDNMOS BDS limitation","authors":"Elizabeth Kho Ching Tee, M. Antoniou, D. Green, A. Hölke, F. Udrea","doi":"10.1109/ISPSD57135.2023.10147409","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147409","url":null,"abstract":"This paper investigates novel techniques of extending the breakdown voltage (BDS) capability of the partial silicon-on-insulator SJ LDNMOS up to 460V. This is based on a unique combination of two different concepts and technologies, namely the Partial Silicon-On-Insulator (PSOI) and Superjunction (SJ) to achieve a highly effective platform for Power Integrated Circuit. The device BDS sensitivity to the handle wafer diode voltage is mitigated by using a novel 3D design based on “domain decomposition” 3D TCAD simulations. The hot spot location in the complex termination area, which is due to out-of-plane (90°) bending of electrostatic potential lines towards the midpoint of the device area, is successfully identified and eliminated.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147725
S. Race, Piyush Kumar, P. Natzke, Ivana Kovacevic-Badstuebner, M. E. Bathen, U. Grossner, G. Romano, Y. Arango, Sami Bolat, S. Wirths, L. Knoll, A. Mihaila
This paper shows how the gate impedance $Z_{text{gg}}$ characterization of a SiC-power MOSFET can be used to investigate its dielectric-semiconductor interface quality distinguishing the channel and JFET contributions. The $Z_{text{gg}}$ characterization is performed for SiC power MOSFETs with SiO2 and with high-k gate dielectrics. Different voltage- and temperature-dependencies of $Z_{text{gg}}$ are identified in the respective SiC MOSFETs. The newer designs show an improvement with respect to the near semiconductor interface-traps. Experimental characterization and TCAD device simulations are carried out to support the conclusions.
{"title":"Gate Impedance Analysis of SiC power MOSFETs with SiO2 and High-k Dielectric","authors":"S. Race, Piyush Kumar, P. Natzke, Ivana Kovacevic-Badstuebner, M. E. Bathen, U. Grossner, G. Romano, Y. Arango, Sami Bolat, S. Wirths, L. Knoll, A. Mihaila","doi":"10.1109/ISPSD57135.2023.10147725","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147725","url":null,"abstract":"This paper shows how the gate impedance $Z_{text{gg}}$ characterization of a SiC-power MOSFET can be used to investigate its dielectric-semiconductor interface quality distinguishing the channel and JFET contributions. The $Z_{text{gg}}$ characterization is performed for SiC power MOSFETs with SiO2 and with high-k gate dielectrics. Different voltage- and temperature-dependencies of $Z_{text{gg}}$ are identified in the respective SiC MOSFETs. The newer designs show an improvement with respect to the near semiconductor interface-traps. Experimental characterization and TCAD device simulations are carried out to support the conclusions.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147503
T. Nanjo, S. Yamamoto, T. Imazawa, A. Kiyoi, T. Shinagawa, T. Watahiki, N. Miura, M. Furuhashi, K. Nishikawa, T. Egawa
Planer-type HEMTs using fully depleted AlGaN/GaN epitaxial layers called EID (Extrinsically electron Induced by Dielectric) AlGaN/GaN MOS-HEMTs are expected to be stable and reliable E-mode operation thanks to its damage-less fabrication process. Fundamental characteristics of the EID-HEMTs for power switching applications were investigated in this study. The fabricated EID-HEMTs exhibited E-mode operation with threshold voltage of 0.5 V, on-resistance of $210 mathrm{m}Omega$ and break-down voltage of 1.1 kV. Furthermore, clear 400 V/10 A switching operation without any harmful symptoms was also demonstrated.
使用完全耗尽的AlGaN/GaN外延层(称为EID (extrically electron Induced by Dielectric))的平板型hemt，由于其无损伤的制造工艺，有望实现稳定可靠的e模式操作。本文研究了用于功率开关应用的eid - hemt的基本特性。所制备的eid - hemt具有e模式工作，阈值电压为0.5 V，导通电阻为210 mathrm{m}Omega$，击穿电压为1.1 kV。此外，还演示了清晰的400v / 10a开关操作，没有任何有害症状。
{"title":"Demonstration of Fundamental Characteristics for Power Switching Application in Planer Type E-mode MOS-HEMT Using Normally Depleted AlGaN GaN Epitaxial Layer On Si Substrate","authors":"T. Nanjo, S. Yamamoto, T. Imazawa, A. Kiyoi, T. Shinagawa, T. Watahiki, N. Miura, M. Furuhashi, K. Nishikawa, T. Egawa","doi":"10.1109/ISPSD57135.2023.10147503","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147503","url":null,"abstract":"Planer-type HEMTs using fully depleted AlGaN/GaN epitaxial layers called EID (Extrinsically electron Induced by Dielectric) AlGaN/GaN MOS-HEMTs are expected to be stable and reliable E-mode operation thanks to its damage-less fabrication process. Fundamental characteristics of the EID-HEMTs for power switching applications were investigated in this study. The fabricated EID-HEMTs exhibited E-mode operation with threshold voltage of 0.5 V, on-resistance of $210 mathrm{m}Omega$ and break-down voltage of 1.1 kV. Furthermore, clear 400 V/10 A switching operation without any harmful symptoms was also demonstrated.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147444
Ji Shu, Jiahui Sun, Zheyang Zheng, K. J. Chen
The false turn-on induced by the gate loop parasitic and Miller capacitance during the fast switching transient of SiC MOSFET leads to increased switching loss, circuit oscillation and even shoot-through. Using a negative OFF-state gate voltage $V_{text{GS}-} text{off}$ can effectively mitigate the false turn-on issue. However, this approach also raises the magnitude of negative gate voltage spikes that occur during the fall of $V_{text{DS}}$, leading to unwanted negative gate overstress. In this work, a simple GaN-HEMT-based gate clamping circuit (GCC) is designed for SiC MOSFET negative gate voltage spike clamping. Thanks to the fast switching speed of GaN HEMT, GCC can clamp the negative spike effectively even at a high slew rate of $V_{text{DS}}$ (120 V/ns), protecting the gate from overstress when negative $V_{text{GS}-text{off}}$ is applied to suppress false turn-on.
{"title":"Protection of SiC MOSFET from Negative Gate Voltage Spikes with a Low-Voltage GaN HEMT","authors":"Ji Shu, Jiahui Sun, Zheyang Zheng, K. J. Chen","doi":"10.1109/ISPSD57135.2023.10147444","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147444","url":null,"abstract":"The false turn-on induced by the gate loop parasitic and Miller capacitance during the fast switching transient of SiC MOSFET leads to increased switching loss, circuit oscillation and even shoot-through. Using a negative OFF-state gate voltage $V_{text{GS}-} text{off}$ can effectively mitigate the false turn-on issue. However, this approach also raises the magnitude of negative gate voltage spikes that occur during the fall of $V_{text{DS}}$, leading to unwanted negative gate overstress. In this work, a simple GaN-HEMT-based gate clamping circuit (GCC) is designed for SiC MOSFET negative gate voltage spike clamping. Thanks to the fast switching speed of GaN HEMT, GCC can clamp the negative spike effectively even at a high slew rate of $V_{text{DS}}$ (120 V/ns), protecting the gate from overstress when negative $V_{text{GS}-text{off}}$ is applied to suppress false turn-on.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128568653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147433
Xinyu Wang, Zuoheng Jiang, Junting Chen, Junlei Zhao, Han Wang, Chengcai Wang, Haohao Chen, Jun Ma, Xiaolong Chen, M. Hua
The frozen trap effect can influence the threshold voltage of $p$-GaN gate HEMT when the temperature decreases to 15 K. The freezing of hole traps occurs at a higher temperature since their energy levels are deeper than that of electron traps, leading to a turning point of the threshold voltage and gate capacitance depending on temperatures. A high gate bias facilitates the emission of frozen carriers, which has a barrier-lowering effect, counteracting the frozen trap effect. At cryogenic temperatures, the threshold voltage of $p$-GaN gate HEMT becomes stable after long-time gate stress, showing promising potential for cryogenic applications.
{"title":"Threshold Voltage Instability of Schottky-type p-GaN Gate HEMT down to Cryogenic Temperatures","authors":"Xinyu Wang, Zuoheng Jiang, Junting Chen, Junlei Zhao, Han Wang, Chengcai Wang, Haohao Chen, Jun Ma, Xiaolong Chen, M. Hua","doi":"10.1109/ISPSD57135.2023.10147433","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147433","url":null,"abstract":"The frozen trap effect can influence the threshold voltage of $p$-GaN gate HEMT when the temperature decreases to 15 K. The freezing of hole traps occurs at a higher temperature since their energy levels are deeper than that of electron traps, leading to a turning point of the threshold voltage and gate capacitance depending on temperatures. A high gate bias facilitates the emission of frozen carriers, which has a barrier-lowering effect, counteracting the frozen trap effect. At cryogenic temperatures, the threshold voltage of $p$-GaN gate HEMT becomes stable after long-time gate stress, showing promising potential for cryogenic applications.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147667
M. Qiao, Dican Hou, Yue Gao, Dingxiang Ma, Jiawei Wang, Bo Zhang
A new generation 700 V Bipolar-CMOS-DMOS (BCD) technology is reported in this work, which integrates quadruple-RESURF LDMOS with best-in-class specific on-resistance ($R_{text{on},text{sp}}$). By introducing PNPN layer in the drift region to locally increase the doping concentration of deep N-type well (DNW) and provide lower on-resistance conduction paths, the quadruple-RESURF LDMOS with PNPN layer (PNPN LDMOS) can achieve low $R_{text{on},text{sp}}$ of 62.5 m Ω.cm2 and high breakdown voltage (BV) of 739 V, whose $R_{text{on},text{sp}}$ is 40.8% lower than that of the mass-produced triple-RESURF LDMOS. The corresponding analytical silicon limit of PNPN LDMOS is derived as $R_{text{on},text{sp}}= 5.93times 10^{-6}times 153times BV^{l.67}$, which is well verified by simulated and measured results at 500 to 700 V breakdown level. Besides, parasitic or independent JFET with competitive saturation drain current ($I_{text{Dsat}}$) is also fabricated in the BCD technology. The measured results indicate that the fabricated JFET can achieve competitive $I_{text{Dsat}}$ of 66.5 µA/µm.
{"title":"A New Generation 700 V BCD Technology that Integrates Quadruple-RESURF LDMOS with Best-in-Class Specific On-Resistance","authors":"M. Qiao, Dican Hou, Yue Gao, Dingxiang Ma, Jiawei Wang, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147667","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147667","url":null,"abstract":"A new generation 700 V Bipolar-CMOS-DMOS (BCD) technology is reported in this work, which integrates quadruple-RESURF LDMOS with best-in-class specific on-resistance ($R_{text{on},text{sp}}$). By introducing PNPN layer in the drift region to locally increase the doping concentration of deep N-type well (DNW) and provide lower on-resistance conduction paths, the quadruple-RESURF LDMOS with PNPN layer (PNPN LDMOS) can achieve low $R_{text{on},text{sp}}$ of 62.5 m Ω.cm2 and high breakdown voltage (BV) of 739 V, whose $R_{text{on},text{sp}}$ is 40.8% lower than that of the mass-produced triple-RESURF LDMOS. The corresponding analytical silicon limit of PNPN LDMOS is derived as $R_{text{on},text{sp}}= 5.93times 10^{-6}times 153times BV^{l.67}$, which is well verified by simulated and measured results at 500 to 700 V breakdown level. Besides, parasitic or independent JFET with competitive saturation drain current ($I_{text{Dsat}}$) is also fabricated in the BCD technology. The measured results indicate that the fabricated JFET can achieve competitive $I_{text{Dsat}}$ of 66.5 µA/µm.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126356546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel low loss Insulated Gate Bipolar Transistor (IGBT) with variable conductance path (VCP) is proposed in this paper. The conductance of P-doped VCP is controlled by the depletion region generated around the depletion gate (DG). In the blocking state, VCP has high conductance and shorts P-well to the emitter. In the on-state, VCP has low conductance and the current can hardly flow through. Accordingly, the highly doped carrier stored (CS) layer would not affect the breakdown voltage (BV) of VCP-IGBT while it can effectively form the hole barrier to obtain low on-state voltage ($V_{on}$). In addition, when VCP-IGBT is turning off, the depletion region near DG vanished. VCP changes to the high-conductance state and extracts carriers directly out of the device, contributing to a low turn-off loss ($E_{off}$). Simulation results show that, under the same $E_{off}$, VCP-IGBT reduces $V_{on}$ by 20% compared to CSTBT and 17% compared to SBL-IGBT without decreasing static and dynamic blocking capability.
{"title":"A Novel IGBT with Variable Conductance Path Realizing Both Low $V_{on}$ and Turn-off Loss","authors":"Yuxiao Yang, Wanjun Chen, Xinqi Sun, Xiaorui Xu, Yun Xia, Chao Liu, Zhaoji Li, Bo Zhang, Meng Wei, Ping Zhang, Zhong Ren","doi":"10.1109/ISPSD57135.2023.10147482","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147482","url":null,"abstract":"A novel low loss Insulated Gate Bipolar Transistor (IGBT) with variable conductance path (VCP) is proposed in this paper. The conductance of P-doped VCP is controlled by the depletion region generated around the depletion gate (DG). In the blocking state, VCP has high conductance and shorts P-well to the emitter. In the on-state, VCP has low conductance and the current can hardly flow through. Accordingly, the highly doped carrier stored (CS) layer would not affect the breakdown voltage (BV) of VCP-IGBT while it can effectively form the hole barrier to obtain low on-state voltage ($V_{on}$). In addition, when VCP-IGBT is turning off, the depletion region near DG vanished. VCP changes to the high-conductance state and extracts carriers directly out of the device, contributing to a low turn-off loss ($E_{off}$). Simulation results show that, under the same $E_{off}$, VCP-IGBT reduces $V_{on}$ by 20% compared to CSTBT and 17% compared to SBL-IGBT without decreasing static and dynamic blocking capability.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121474087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147681
O. Hilt, F. Brunner, M. Wolf, Eldad Bahat Treidel, J. Würfl, A. Thies, A. Mogilatenko
AlN-based semiconductor devices are considered to outperform lateral AlGaN/GaN HFETs for power-electronic switching applications due to the high AlN-material breakdown field strength. We present an AlGaN/GaN /AlN-HFET transistor without any compensation doping in the AlN-buffer layer. Breakdown voltage scaling as function of the gate-drain separation of 140 V/µm and power figure-of-merit of 2.4 GW/cm2 were achieved which is superior to most other GaN device technologies. 120 m Ω power transistors demonstrated 10 A switching transients up to 950 V off-state voltage and thus meet basic requirements for kW-range power switching. The origin of still present dispersion effects during high voltage switching could be attributed to a high structural defect density at the AlN-buffer / GaN channel material interface.
{"title":"10 A/950 V switching of GaN-channel HFETs with non-doped AlN buffer","authors":"O. Hilt, F. Brunner, M. Wolf, Eldad Bahat Treidel, J. Würfl, A. Thies, A. Mogilatenko","doi":"10.1109/ISPSD57135.2023.10147681","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147681","url":null,"abstract":"AlN-based semiconductor devices are considered to outperform lateral AlGaN/GaN HFETs for power-electronic switching applications due to the high AlN-material breakdown field strength. We present an AlGaN/GaN /AlN-HFET transistor without any compensation doping in the AlN-buffer layer. Breakdown voltage scaling as function of the gate-drain separation of 140 V/µm and power figure-of-merit of 2.4 GW/cm2 were achieved which is superior to most other GaN device technologies. 120 m Ω power transistors demonstrated 10 A switching transients up to 950 V off-state voltage and thus meet basic requirements for kW-range power switching. The origin of still present dispersion effects during high voltage switching could be attributed to a high structural defect density at the AlN-buffer / GaN channel material interface.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147568
Haifeng Zhang, Dibo Zhang, Hiromu Yamasaki, Katsuhiro Hata, K. Wada, Kan Akatsu, I. Omura, M. Takamiya
To achieve low-cost overcurrent protection for IGBTs without using external components such as high-voltage diodes, a gate driver IC with a fully integrated overcurrent protection function by measuring gate-to-emitter voltage ($V_{text{GE}}$) during IGBT conduction is proposed. In the proposed gate driver IC, while the IGBTs are ON, constant gate charge is periodically discharged and charged, and when $V_{text{GE}}$ dropped by each discharge is less than the reference voltage, it is detected as the overcurrent and the IGBTs are immediately turned off to protect from the overcurrent. In a single-pulse test of an inductive load at 300 V for an IGBT with a pulse rating of 200 A, the proposed gate driver IC fabricated with 180-nm BCD process successfully protected the overcurrent of 370 A with the protection delay of 810 ns.
{"title":"Gate Driver IC with Fully Integrated Overcurrent Protection Function by Measuring Gate-to-Emitter Voltage During IGBT Conduction","authors":"Haifeng Zhang, Dibo Zhang, Hiromu Yamasaki, Katsuhiro Hata, K. Wada, Kan Akatsu, I. Omura, M. Takamiya","doi":"10.1109/ISPSD57135.2023.10147568","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147568","url":null,"abstract":"To achieve low-cost overcurrent protection for IGBTs without using external components such as high-voltage diodes, a gate driver IC with a fully integrated overcurrent protection function by measuring gate-to-emitter voltage ($V_{text{GE}}$) during IGBT conduction is proposed. In the proposed gate driver IC, while the IGBTs are ON, constant gate charge is periodically discharged and charged, and when $V_{text{GE}}$ dropped by each discharge is less than the reference voltage, it is detected as the overcurrent and the IGBTs are immediately turned off to protect from the overcurrent. In a single-pulse test of an inductive load at 300 V for an IGBT with a pulse rating of 200 A, the proposed gate driver IC fabricated with 180-nm BCD process successfully protected the overcurrent of 370 A with the protection delay of 810 ns.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130488971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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