Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147398
Jiahui Sun, Zheyang Zheng, Li Zhang, Yat Hon Ng, Ji Shu, Tao Chen, K. J. Chen
To further reduce the forward gate current of Schottky-type $p$-GaN gate HEMTs, inadequate Mg activation in $p$-GaN is deployed in this work, which tends to convert the conventional $p$-GaN into insulating GaN with high concentration of Mg passivated by hydrogens. The free hole concentration in $p$-GaN is reduced, and so is the hole deficiency effect that is the main cause of dynamic threshold voltage ($V_{text{TH}}$) in commercial Schottky-type $p$-GaN gate HEMTs. However, plenty of electron traps left in $p$-GaN lead to more significant dynamic $V_{text{TH}}$ shift (up to 6 V) under reverse gate bias ($V_{text{GSQ}}$, up to -13 V), as revealed by the $V_{text{TH}}$ recovery processes under different conditions of light illumination and forward gate bias. Fortunately, under forward $V_{text{GSQ}}$, the fully depleted $p$-GaN layer facilitates electron acceleration by the electric field, suppressing the electron trapping and consequent dynamic $V_{text{TH}}$ shift. Besides, deeper-level electron trapping in AlGaN may account for the slight dynamic $V_{text{TH}}$ shift under $V_{text{GSQ}}geq 7mathrm{V}$.
{"title":"Impact of Inadequate Mg Activation on Dynamic Threshold Voltage of Schottky-type $p$-GaN Gate HEMTs","authors":"Jiahui Sun, Zheyang Zheng, Li Zhang, Yat Hon Ng, Ji Shu, Tao Chen, K. J. Chen","doi":"10.1109/ISPSD57135.2023.10147398","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147398","url":null,"abstract":"To further reduce the forward gate current of Schottky-type <tex>$p$</tex>-GaN gate HEMTs, inadequate Mg activation in <tex>$p$</tex>-GaN is deployed in this work, which tends to convert the conventional <tex>$p$</tex>-GaN into insulating GaN with high concentration of Mg passivated by hydrogens. The free hole concentration in <tex>$p$</tex>-GaN is reduced, and so is the hole deficiency effect that is the main cause of dynamic threshold voltage (<tex>$V_{text{TH}}$</tex>) in commercial Schottky-type <tex>$p$</tex>-GaN gate HEMTs. However, plenty of electron traps left in <tex>$p$</tex>-GaN lead to more significant dynamic <tex>$V_{text{TH}}$</tex> shift (up to 6 V) under reverse gate bias (<tex>$V_{text{GSQ}}$</tex>, up to -13 V), as revealed by the <tex>$V_{text{TH}}$</tex> recovery processes under different conditions of light illumination and forward gate bias. Fortunately, under forward <tex>$V_{text{GSQ}}$</tex>, the fully depleted <tex>$p$</tex>-GaN layer facilitates electron acceleration by the electric field, suppressing the electron trapping and consequent dynamic <tex>$V_{text{TH}}$</tex> shift. Besides, deeper-level electron trapping in AlGaN may account for the slight dynamic <tex>$V_{text{TH}}$</tex> shift under <tex>$V_{text{GSQ}}geq 7mathrm{V}$</tex>.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131299587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147654
Huan Wang, Yulian Yin, Fengwei Ji, Jiahong Du, Haoran Li, Changhui Zhao, Baikui Li, Cungang Hu, Wenping Cao, Xi Tang, Shu-Ting Yang
In this work, enhanced gate breakdown under pulsed switching conditions were observed and investigated in Schottky-type p-GaN gate HEMTs. The pulsed time-dependent breakdown (TDB) and pulsed gate breakdown characteristics both featured a positive frequency dependence. At a gate bias of 10 V, the effective total lifetime extended from 170 s to 670 s with the switching frequency increased from 5 Hz to 10 kHz. By time-dependent electroluminescence (TDEL) characteristics on devices with semi-transparent gate electrodes, the high-energy ultraviolet emission increased at a higher switching frequency, indicating an enhanced hole injection into the p-GaN/AlGaN/GaN heterostructure. The enhanced hole injection annihilated more injected electrons, leading to the suppressed hot-electron effect, as well as the enhanced gate breakdown.
{"title":"Enhanced gate breakdown and electroluminescence in p-GaN gate HEMTs under pulsed switching conditions","authors":"Huan Wang, Yulian Yin, Fengwei Ji, Jiahong Du, Haoran Li, Changhui Zhao, Baikui Li, Cungang Hu, Wenping Cao, Xi Tang, Shu-Ting Yang","doi":"10.1109/ISPSD57135.2023.10147654","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147654","url":null,"abstract":"In this work, enhanced gate breakdown under pulsed switching conditions were observed and investigated in Schottky-type p-GaN gate HEMTs. The pulsed time-dependent breakdown (TDB) and pulsed gate breakdown characteristics both featured a positive frequency dependence. At a gate bias of 10 V, the effective total lifetime extended from 170 s to 670 s with the switching frequency increased from 5 Hz to 10 kHz. By time-dependent electroluminescence (TDEL) characteristics on devices with semi-transparent gate electrodes, the high-energy ultraviolet emission increased at a higher switching frequency, indicating an enhanced hole injection into the p-GaN/AlGaN/GaN heterostructure. The enhanced hole injection annihilated more injected electrons, leading to the suppressed hot-electron effect, as well as the enhanced gate breakdown.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147544
Dominik Koch, V. Polezhaev, Ankit Sharma, K. M. Barón, T. Huesgen, I. Kallfass
Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a $7 mathrm{m}Omega$, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a $5 mathrm{m}Omega$, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both $7 mathrm{m}Omega$ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the $5 mathrm{m}Omega$ GaN transistor. With its combination of improved thermal characteristics and low-inductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density.
与硅基器件相比，氮化镓晶体管具有更小的芯片面积，这可能导致高电流密度应用中的热挑战。因此，需要具有高散热能力和小寄生的热优化封装。本研究研究了$7 mathm {m}Omega$， 100 V GaN HEMT在具有集成RTD的热优化单芯片封装中的热性能，并将其与商业同类产品进行了比较。热优化后的封装显示出更好的瞬态热阻抗，静态热阻为3.1 K/W，与COTS封装相比降低了20%。集成的RTD走线的相对反应时间为590 ms，与结温相比慢了30倍。为了显示相同的电气行为，虽然单芯片封装更大，但它与商业现成封装和$5 mathm {m}Omega$， 100 V GaN单芯片封装在300 kHz, 48 V降压转换器中进行比较。两款$7 maththrm {m}Omega$版本在50 A输出电流下具有相同的效率≈97.5%，略优于$5 maththrm {m}Omega$ GaN晶体管。GaN器件的热优化封装结合了改进的热特性和低电感，为功率转换器的设计提供了更多的自由度，以实现更长的寿命、更高的温度工作和功率密度之间的权衡。
{"title":"Application-Oriented Characterization of Thermally Optimized, Asymmetrical Single Chip Packages for 100 V GaN HEMTs","authors":"Dominik Koch, V. Polezhaev, Ankit Sharma, K. M. Barón, T. Huesgen, I. Kallfass","doi":"10.1109/ISPSD57135.2023.10147544","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147544","url":null,"abstract":"Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a $7 mathrm{m}Omega$, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a $5 mathrm{m}Omega$, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both $7 mathrm{m}Omega$ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the $5 mathrm{m}Omega$ GaN transistor. With its combination of improved thermal characteristics and low-inductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123426797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a vertical $beta$-Ga2O3 heterojunction barrier Schottky diode (HJBS) with hybrid unipolar and bipolar operation has been demonstrated by implementing p-type NiO. HJBS exhibits a low on-state voltage similar to the traditional Schottky barrier diode, and a low reverse leakage current close to NiO/$beta$-Ga2O3 heterojunction diode (HJD). The current conduction mode shifts from unipolar mode with high conduction resistance to bipolar mode with low conduction resistance when the forward voltage exceeds the turn-on voltage of the HJD. In addition, the hybrid operating mode of HJBS was further elaborated through temperature dependent electrical characteristics. These results preliminarily prove the existence of bipolar behavior in $beta$-Ga2O3 HJBS.
{"title":"1 kV Vertical $beta$-Ga2O3 Heterojunction Barrier Schottky Diode with Hybrid Unipolar and Bipolar Operation","authors":"Weibing Hao, Qiming He, Zhao Han, Xiaolong Zhao, Guangwei Xu, Shu-Ting Yang, Shibing Long","doi":"10.1109/ISPSD57135.2023.10147686","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147686","url":null,"abstract":"In this work, a vertical <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> heterojunction barrier Schottky diode (HJBS) with hybrid unipolar and bipolar operation has been demonstrated by implementing p-type NiO. HJBS exhibits a low on-state voltage similar to the traditional Schottky barrier diode, and a low reverse leakage current close to NiO/<tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> heterojunction diode (HJD). The current conduction mode shifts from unipolar mode with high conduction resistance to bipolar mode with low conduction resistance when the forward voltage exceeds the turn-on voltage of the HJD. In addition, the hybrid operating mode of HJBS was further elaborated through temperature dependent electrical characteristics. These results preliminarily prove the existence of bipolar behavior in <tex>$beta$</tex>-Ga<inf>2</inf>O<inf>3</inf> HJBS.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127264419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147604
M. Boccarossa, L. Maresca, A. Borghese, M. Riccio, G. Breglio, A. Irace, G. Salvatore
In this paper, TCAD simulations provide insights on the effect of a non-linear dielectric gate stack on the short-circuit performance of silicon carbide (SiC) power MOSFETs. In particular, the regular gate oxide was replaced by a stack formed by silicon dioxide and a non-linear dielectric whose permittivity varies with temperature, in order to counterbalance the reduction of the threshold voltage due to temperature. Simulations show that the presented device has a higher ruggedness to short-circuit events, thanks to the reduction of the maximum temperature arising in the device during those events.
{"title":"Short-Circuit Rugged 1.2 kV SiC MOSFET with a Non-Linear Dielectric Gate Stack","authors":"M. Boccarossa, L. Maresca, A. Borghese, M. Riccio, G. Breglio, A. Irace, G. Salvatore","doi":"10.1109/ISPSD57135.2023.10147604","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147604","url":null,"abstract":"In this paper, TCAD simulations provide insights on the effect of a non-linear dielectric gate stack on the short-circuit performance of silicon carbide (SiC) power MOSFETs. In particular, the regular gate oxide was replaced by a stack formed by silicon dioxide and a non-linear dielectric whose permittivity varies with temperature, in order to counterbalance the reduction of the threshold voltage due to temperature. Simulations show that the presented device has a higher ruggedness to short-circuit events, thanks to the reduction of the maximum temperature arising in the device during those events.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130785937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147642
C. Piotrowic, B. Mohamad, P. F. P. P. Rocha, N. Malbert, S. Ruel, P. Pimenta-Barros, M. Jaud, L. Vauche, C. L. Royer
In this paper, we study the effect of the gate morphology and the impact of the crystallographic channel orientation on the on-state electrical performances of the GaN-on-Si MOS-HEMTs with a fully recessed gate. By combining physical and chemical characterizations (TEM, EDX, and AFM), experimental measurements and TCAD simulations, the effect of dry-etching and wet cleaning on the gate morphology and their consequences on electrical performances are studied. Moreover, an anisotropy behavior with the Atomic Layer Etching (ALE) and wet processes between $(11overline{2}0)$ and $(1overline{1}00)$ planes is highlighted. Using the new partitioning methodology, the contributions of the bottom and sidewall regions are evaluated separately in terms of resistance and mobility. The good agreement between TCAD simulations and experimental $I_{D}(V_{G}$) characteristics validates the methodology and highlights the gate morphology importance for the device's on-state performances in terms of resistance, mobility, threshold voltage and subthreshold slope.
在本文中，我们研究了栅极形态的影响和晶体学通道的取向对GaN-on-Si mos - hemt具有全凹槽栅极的电学性能的影响。通过结合物理和化学表征(TEM, EDX和AFM)，实验测量和TCAD模拟，研究了干法蚀刻和湿法清洗对栅极形貌的影响及其对电性能的影响。此外，原子层蚀刻(ALE)和湿工艺在$(11overline{2}0)$和$(1overline{1}00)$平面之间的各向异性行为被强调。利用新的划分方法，底部和侧壁区域的贡献分别在阻力和流动性方面进行了评估。TCAD仿真与实验$I_{D}(V_{G}$)特性之间的良好一致性验证了该方法，并强调了栅极形态对器件在电阻、迁移率、阈值电压和亚阈值斜率方面的导通性能的重要性。
{"title":"Impact of Gate Morphology on Electrical Performances of Recessed GaN-on Si MOS channel-HEMT for Different Channel Orientations","authors":"C. Piotrowic, B. Mohamad, P. F. P. P. Rocha, N. Malbert, S. Ruel, P. Pimenta-Barros, M. Jaud, L. Vauche, C. L. Royer","doi":"10.1109/ISPSD57135.2023.10147642","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147642","url":null,"abstract":"In this paper, we study the effect of the gate morphology and the impact of the crystallographic channel orientation on the on-state electrical performances of the GaN-on-Si MOS-HEMTs with a fully recessed gate. By combining physical and chemical characterizations (TEM, EDX, and AFM), experimental measurements and TCAD simulations, the effect of dry-etching and wet cleaning on the gate morphology and their consequences on electrical performances are studied. Moreover, an anisotropy behavior with the Atomic Layer Etching (ALE) and wet processes between $(11overline{2}0)$ and $(1overline{1}00)$ planes is highlighted. Using the new partitioning methodology, the contributions of the bottom and sidewall regions are evaluated separately in terms of resistance and mobility. The good agreement between TCAD simulations and experimental $I_{D}(V_{G}$) characteristics validates the methodology and highlights the gate morphology importance for the device's on-state performances in terms of resistance, mobility, threshold voltage and subthreshold slope.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147669
Y. Barazi, F. Richardeau, S. Vinnac, N. Rouger
This article presents an alternative solution to the short circuit challenges commonly faced by ultra-fast power transistors. Specially 650V p-GaN HEMTs, where the short-circuit timing capability is very critical, and the presence of thermal run-aways is very sensitive. In response to this issue, a dedicated approach to detect the short-circuit inserting an on-line monitoring gate-resistor through a dual-channel segmented CMOS Gate Driver is proposed. The short-circuit indicator under Hard Switch Fault is based on the Gate-Schottky-Barrier leakage current, which is translated on a voltage drop at the gate-source voltage. The detection circuit can be fully integrated in the IC with a low monitoring voltage. A dual-buffer IC prototype including impedance state and monitoring integrated circuit using XFAB XT018 0.18um CMOS SOI technology was performed. Parametric results show a robust and quick detection propagation delay around 580ns under VDS = 400V and V GS = 5V.
{"title":"p-GaN HEMT Hard Switching Fault Type Short-Circuit Detection Based on the Gate Schottky-Barrier Leakage Current and Using a Dual-Channel Segmented CMOS buffer Gate-Driver","authors":"Y. Barazi, F. Richardeau, S. Vinnac, N. Rouger","doi":"10.1109/ISPSD57135.2023.10147669","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147669","url":null,"abstract":"This article presents an alternative solution to the short circuit challenges commonly faced by ultra-fast power transistors. Specially 650V p-GaN HEMTs, where the short-circuit timing capability is very critical, and the presence of thermal run-aways is very sensitive. In response to this issue, a dedicated approach to detect the short-circuit inserting an on-line monitoring gate-resistor through a dual-channel segmented CMOS Gate Driver is proposed. The short-circuit indicator under Hard Switch Fault is based on the Gate-Schottky-Barrier leakage current, which is translated on a voltage drop at the gate-source voltage. The detection circuit can be fully integrated in the IC with a low monitoring voltage. A dual-buffer IC prototype including impedance state and monitoring integrated circuit using XFAB XT018 0.18um CMOS SOI technology was performed. Parametric results show a robust and quick detection propagation delay around 580ns under VDS = 400V and V GS = 5V.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147704
M. Xiao, Boyan Wang, Ruizhe Zhang, Q. Song, Joseph Spencer, Z. Du, Yuan Qin, K. Sasaki, Han Wang, M. Tadjer, Yuhao Zhang
This work investigates the blocking electric field, capacitance, and switching speed of the p-type NiO based junction termination extension (JTE) for vertical Ga2O3 devices. The JTE comprises multiple NiO layers sputtered on the surface of Ga2O3 drift region, the acceptor concentration and length of which are carefully optimized. This NiO JTE enabled a breakdown voltage over 3 kV in vertical Ga2O3 diodes with a parallel-plate junction field of 4.2 MV/cm. Large-area Ga2O3 p-n diodes with a current over 1 A were fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only, ~11 % of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-ON/OFF speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes. These results show the good promise of NiO JTE as an effective edge termination for Ga2O3 power devices.
{"title":"NiO Junction Termination Extension for Ga2O3 Devices: High Blocking Field, Low Capacitance, and Fast Switching Speed","authors":"M. Xiao, Boyan Wang, Ruizhe Zhang, Q. Song, Joseph Spencer, Z. Du, Yuan Qin, K. Sasaki, Han Wang, M. Tadjer, Yuhao Zhang","doi":"10.1109/ISPSD57135.2023.10147704","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147704","url":null,"abstract":"This work investigates the blocking electric field, capacitance, and switching speed of the p-type NiO based junction termination extension (JTE) for vertical Ga<inf>2</inf>O<inf>3</inf> devices. The JTE comprises multiple NiO layers sputtered on the surface of Ga<inf>2</inf>O<inf>3</inf> drift region, the acceptor concentration and length of which are carefully optimized. This NiO JTE enabled a breakdown voltage over 3 kV in vertical Ga<inf>2</inf>O<inf>3</inf> diodes with a parallel-plate junction field of 4.2 MV/cm. Large-area Ga<inf>2</inf>O<inf>3</inf> p-n diodes with a current over 1 A were fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only, ~11 % of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-ON/OFF speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes. These results show the good promise of NiO JTE as an effective edge termination for Ga<inf>2</inf>O<inf>3</inf> power devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"140 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121005116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147671
Dingxiang Ma, Yue Gao, Dican Hou, Zhangyi’an Yuan, M. Qiao, Shaowei Zhen, Bo Zhang
This study investigates design of two kinds of JFET by experiment based on a standard 0.18µm BCD platform, satisfying the 60V on-state application. Meanwhile a range of pinch-off voltage (VP) from -IV to −6V is achieved and off-state breakdown voltage (BVoFF) reaches 107V even extending to 117V. By utilizing the P-type buried layer (PBL), maximum output current fabricated realizes 1.45mA without sacrificing BVoFF and VP. What's more, drain induced barrier lowering (DIBL) effect is analyzed with different applied voltages. Considering yield, BV OFF and V p of both structures are measured from different dies to illustrate its stability of layout design.
{"title":"Isolated JFET Design and Performance Analyze by Experiment Based on Standard 0.18µm BCD Platform","authors":"Dingxiang Ma, Yue Gao, Dican Hou, Zhangyi’an Yuan, M. Qiao, Shaowei Zhen, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147671","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147671","url":null,"abstract":"This study investigates design of two kinds of JFET by experiment based on a standard 0.18µm BCD platform, satisfying the 60V on-state application. Meanwhile a range of pinch-off voltage (VP) from -IV to −6V is achieved and off-state breakdown voltage (BVoFF) reaches 107V even extending to 117V. By utilizing the P-type buried layer (PBL), maximum output current fabricated realizes 1.45mA without sacrificing BVoFF and VP. What's more, drain induced barrier lowering (DIBL) effect is analyzed with different applied voltages. Considering yield, BV OFF and V p of both structures are measured from different dies to illustrate its stability of layout design.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125292460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-28DOI: 10.1109/ISPSD57135.2023.10147583
Chengcai Wang, Haohao Chen, Zuoheng Jiang, Junting Chen, M. Hua
In this work, the $p-n$ junction (PNJ)/AlGaN/GaN HEMTs with different effective $n$-GaN doping concentrations ($N_{mathrm{D}}$) of $1.7times 10^{20}$ cm−3, $2.6times 10^{19}$ cm−3 and $1times 10^{17}$ cm−3 are comparatively studied to reveal the impacts of $N_{mathrm{D}}$ on gate reliability. With lower $N_{mathrm{D}}$, gate leakage reduces, and forward gate breakdown voltage boosts up to 18.6 V, whereas the maximum applicable gate voltage for a 10-year lifetime will not continually increase when $N_{mathrm{D}}$ decreases to $1times 10^{17}$ cm−3. This feature is attributed to premature breakdown caused by electric-field crowding at the surface of the fully depleted n-GaN. To fully exploit the reliability of the PNJ-HEMTs, it is suggested that the $N_{mathrm{D}}$ of PNJ-HEMTs should be carefully designed to widen the depletion region in $p-n$ junction appropriately, while premature breakdown caused by electric-field crowding at the surface should be avoided.
{"title":"Impacts of $n$-GaN Doping Concentration on Gate Reliability of $p-n$ Junction/AlGaN/GaN HEMTs","authors":"Chengcai Wang, Haohao Chen, Zuoheng Jiang, Junting Chen, M. Hua","doi":"10.1109/ISPSD57135.2023.10147583","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147583","url":null,"abstract":"In this work, the <tex>$p-n$</tex> junction (PNJ)/AlGaN/GaN HEMTs with different effective <tex>$n$</tex>-GaN doping concentrations (<tex>$N_{mathrm{D}}$</tex>) of <tex>$1.7times 10^{20}$</tex> cm<sup>−3</sup>, <tex>$2.6times 10^{19}$</tex> cm<sup>−3</sup> and <tex>$1times 10^{17}$</tex> cm<sup>−3</sup> are comparatively studied to reveal the impacts of <tex>$N_{mathrm{D}}$</tex> on gate reliability. With lower <tex>$N_{mathrm{D}}$</tex>, gate leakage reduces, and forward gate breakdown voltage boosts up to 18.6 V, whereas the maximum applicable gate voltage for a 10-year lifetime will not continually increase when <tex>$N_{mathrm{D}}$</tex> decreases to <tex>$1times 10^{17}$</tex> cm<sup>−3</sup>. This feature is attributed to premature breakdown caused by electric-field crowding at the surface of the fully depleted n-GaN. To fully exploit the reliability of the PNJ-HEMTs, it is suggested that the <tex>$N_{mathrm{D}}$</tex> of PNJ-HEMTs should be carefully designed to widen the depletion region in <tex>$p-n$</tex> junction appropriately, while premature breakdown caused by electric-field crowding at the surface should be avoided.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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