Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145747
K. Sukegawa, H. Matsuoka, T. Sasaki, K. Park, S. Kawamura, M. Nakano
Generally in SOS (silicon on sapphire) films, the density of Si defects such as twins and stacking faults is quite high, especially near the Si/sapphire interface, mainly due to the lattice mismatch between Si and sapphire. This leads to inferior electrical properties compared to their bulk counterparts. Although it has been reported that the characteristics of SOS devices can be improved by a pulse laser irradiation, the quality of laser-irradiated SOS films has not been investigated in detail. It is demonstrated that the SOS films have been significantly improved by CW-Ar laser recrystallization, resulting in almost defect-free SOS films. The defect-free SOS films reduce back-channel leakage currents in both n- and p-MOSFETs, while at the same time improving carrier mobilities by 30-50%.<>
通常在SOS (silicon on sapphire)薄膜中，Si缺陷(如孪晶和层错)的密度相当高，特别是在Si/蓝宝石界面附近，主要是由于Si和蓝宝石之间的晶格不匹配。这导致电性能较差相比，他们的散装同行。虽然有报道称脉冲激光照射可以改善SOS器件的特性，但尚未对激光照射SOS薄膜的质量进行详细研究。结果表明，通过CW-Ar激光再结晶，SOS薄膜的质量得到了显著改善，SOS薄膜几乎没有缺陷。无缺陷的SOS薄膜减少了n-和p- mosfet的背道泄漏电流，同时将载流子迁移率提高了30-50%。
{"title":"Significant improvement in characteristics of SOS/MOSFETs by CW-Ar laser-recrystallization","authors":"K. Sukegawa, H. Matsuoka, T. Sasaki, K. Park, S. Kawamura, M. Nakano","doi":"10.1109/SOSSOI.1990.145747","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145747","url":null,"abstract":"Generally in SOS (silicon on sapphire) films, the density of Si defects such as twins and stacking faults is quite high, especially near the Si/sapphire interface, mainly due to the lattice mismatch between Si and sapphire. This leads to inferior electrical properties compared to their bulk counterparts. Although it has been reported that the characteristics of SOS devices can be improved by a pulse laser irradiation, the quality of laser-irradiated SOS films has not been investigated in detail. It is demonstrated that the SOS films have been significantly improved by CW-Ar laser recrystallization, resulting in almost defect-free SOS films. The defect-free SOS films reduce back-channel leakage currents in both n- and p-MOSFETs, while at the same time improving carrier mobilities by 30-50%.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145699
J. Chen, P. Fang, P. Ko, C. Hu, R. Solomon, T. Chan, C. Sodini
The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (separation by implantation of oxygen) wafers fabricated with conventional submicron CMOS technology. The SOI film thickness, the buried-oxide thickness, and the gate oxide are 100 nm, 300 nm, and 11.5 nm, respectively. A computer-controlled test system was used to conduct the I-V and noise measurement automatically. A model explaining the occurrence of the noise overshoot and the noise peak is proposed.<>
{"title":"Noise overshoot at drain current kink in SOI MOSFET","authors":"J. Chen, P. Fang, P. Ko, C. Hu, R. Solomon, T. Chan, C. Sodini","doi":"10.1109/SOSSOI.1990.145699","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145699","url":null,"abstract":"The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (separation by implantation of oxygen) wafers fabricated with conventional submicron CMOS technology. The SOI film thickness, the buried-oxide thickness, and the gate oxide are 100 nm, 300 nm, and 11.5 nm, respectively. A computer-controlled test system was used to conduct the I-V and noise measurement automatically. A model explaining the occurrence of the noise overshoot and the noise peak is proposed.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"307 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116405646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145740
B. Tillack, R. Banisch, H. Richter, K. Hoeppner, O. Joachim, J. Knopke, U. Retzlaf
The aim is to demonstrate that it is possible to create completely dielectrically isolated Si using the zone-melted recrystallization (ZMR) technique and that the material quality allows application to high-voltage devices. In the first case the seeding windows were etched into the thermal oxide in the area between the tub-shaped grooves. Polycrystalline silicon films of different thicknesses (up to 80 mu m) were deposited. In the second case a thin polycrystalline silicon film (1 mu m) acts as a connection between the single-crystalline substrate and poly-Si in the grooves. The seeding recrystallization results in single-crystalline silicon
{"title":"Completely dielectrically isolated silicon for high voltage application produced by ZMR of poly Si on SiO/sub 2/","authors":"B. Tillack, R. Banisch, H. Richter, K. Hoeppner, O. Joachim, J. Knopke, U. Retzlaf","doi":"10.1109/SOSSOI.1990.145740","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145740","url":null,"abstract":"The aim is to demonstrate that it is possible to create completely dielectrically isolated Si using the zone-melted recrystallization (ZMR) technique and that the material quality allows application to high-voltage devices. In the first case the seeding windows were etched into the thermal oxide in the area between the tub-shaped grooves. Polycrystalline silicon films of different thicknesses (up to 80 mu m) were deposited. In the second case a thin polycrystalline silicon film (1 mu m) acts as a connection between the single-crystalline substrate and poly-Si in the grooves. The seeding recrystallization results in single-crystalline silicon","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123812880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145715
D. Chandler-Horowitz, J. Marchiando, M. Doss, S. Krause, S. Visitserngtrakul
Spectroscopic ellipsometry as a nondestructive probe for multilayer SIMOX materials is considered. TEM micrographs of high flux single implant SIMOX annealed at 1300 degrees C for 6 h show islands of silicon precipitates near the bottom of the buried oxide layer. Spectroscopic ellipsometric measurements were performed on these samples at various implant doses and beam current densities to observe how the measured data fit the data theoretically predicted for various models of SIMOX that lead to the presence of these islands. Three distinct models of increasing complexity were used in the analysis: a 3-layer model having a silicon dioxide cap layer, upper silicon layer, and buried or implanted silicon dioxide layer; 4-layer model in which a new layer between the silicon substrate and buried silicon dioxide was added where the islands exist; and a 5-layer model that raised the island layer off the top of the substrate by adding a thin pure silicon dioxide layer above the substrate.<>
{"title":"Sensitivity of ellipsometric modeling to the 'islands' of silicon precipitates at the bottom of the buried oxide layer in annealed SIMOX","authors":"D. Chandler-Horowitz, J. Marchiando, M. Doss, S. Krause, S. Visitserngtrakul","doi":"10.1109/SOSSOI.1990.145715","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145715","url":null,"abstract":"Spectroscopic ellipsometry as a nondestructive probe for multilayer SIMOX materials is considered. TEM micrographs of high flux single implant SIMOX annealed at 1300 degrees C for 6 h show islands of silicon precipitates near the bottom of the buried oxide layer. Spectroscopic ellipsometric measurements were performed on these samples at various implant doses and beam current densities to observe how the measured data fit the data theoretically predicted for various models of SIMOX that lead to the presence of these islands. Three distinct models of increasing complexity were used in the analysis: a 3-layer model having a silicon dioxide cap layer, upper silicon layer, and buried or implanted silicon dioxide layer; 4-layer model in which a new layer between the silicon substrate and buried silicon dioxide was added where the islands exist; and a 5-layer model that raised the island layer off the top of the substrate by adding a thin pure silicon dioxide layer above the substrate.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145729
R. Lawrence, G. Campisi, G.J. Shontz, G. Pollack, R. Sundaresan
The authors demonstrate the mobility and threshold voltage behavior for fully depleted transistors of various geometries on various epitaxial silicon thicknesses. Electrical characterization techniques were used to examine fully depleted SIMOX SOI front- and back-gate transistors of gate geometries between 0.6 and 3 mu m on epitaxial silicon of thicknesses between 150 and 300 nm. Degradation in N-channel mobilities and threshold voltages was observed for short channel lengths and decreasing epitaxial silicon thickness. The decrease in mobility was attributed to the higher electric fields for small geometries. SOI is better than bulk, and fully depleted SOI is better than non-fully depleted SOI. Ultra thin SOI, synonymous with fully depleted, uses narrow gates, and thus the problem of degradation in mobility will be observed. Fully depleted SOI mitigates but does not remove the field dependence of mobility.<>
{"title":"Limitations to fully-depleted SOI structures","authors":"R. Lawrence, G. Campisi, G.J. Shontz, G. Pollack, R. Sundaresan","doi":"10.1109/SOSSOI.1990.145729","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145729","url":null,"abstract":"The authors demonstrate the mobility and threshold voltage behavior for fully depleted transistors of various geometries on various epitaxial silicon thicknesses. Electrical characterization techniques were used to examine fully depleted SIMOX SOI front- and back-gate transistors of gate geometries between 0.6 and 3 mu m on epitaxial silicon of thicknesses between 150 and 300 nm. Degradation in N-channel mobilities and threshold voltages was observed for short channel lengths and decreasing epitaxial silicon thickness. The decrease in mobility was attributed to the higher electric fields for small geometries. SOI is better than bulk, and fully depleted SOI is better than non-fully depleted SOI. Ultra thin SOI, synonymous with fully depleted, uses narrow gates, and thus the problem of degradation in mobility will be observed. Fully depleted SOI mitigates but does not remove the field dependence of mobility.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129055002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145710
S.T. Liu, P. Fechner, R. L. Roisen
Physical and electrical properties of incoming low-defect SIMOX SOI wafers were characterized by fast turn techniques to determine their suitability for device applications. Physical properties were evaluated extensively with optical reflectometry and cross-sectional transmission electron microscopy. To facilitate evaluation of the back channel property with minimal processing. Schottky barrier MOS and simple regular MOS test structures were made. Schottky barrier behavior was noted in the characteristics near the origin and the conduction at zero gate bias. Back channel properties were evaluated first, and then the device was subjected to irradiation using a 10-keV ARACOR/4100 X-ray source with doses in the Mrad (SiO/sub 2/) region. The threshold voltage shift and the subthreshold voltage swing were measured. The radiation induced interface states in the Mrad (SiO/sub 2/) region were determined.<>
{"title":"Fast turn characterization of SIMOX wafers","authors":"S.T. Liu, P. Fechner, R. L. Roisen","doi":"10.1109/SOSSOI.1990.145710","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145710","url":null,"abstract":"Physical and electrical properties of incoming low-defect SIMOX SOI wafers were characterized by fast turn techniques to determine their suitability for device applications. Physical properties were evaluated extensively with optical reflectometry and cross-sectional transmission electron microscopy. To facilitate evaluation of the back channel property with minimal processing. Schottky barrier MOS and simple regular MOS test structures were made. Schottky barrier behavior was noted in the characteristics near the origin and the conduction at zero gate bias. Back channel properties were evaluated first, and then the device was subjected to irradiation using a 10-keV ARACOR/4100 X-ray source with doses in the Mrad (SiO/sub 2/) region. The threshold voltage shift and the subthreshold voltage swing were measured. The radiation induced interface states in the Mrad (SiO/sub 2/) region were determined.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132465705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145722
Jong-Sun Lyu, S.-W. Kang, C. Lee
The floating substrate effects of p-channel MOSFETs fabricated on SOI substrates formed by oxygen implantation are studied. The kink effect occurs in the saturation regime for p-channel SOI MOSFETs when electrons are generated by impact ionization near the drain and swept by the electric field into the neutral floating substrate. This lowers substrate potential and thus changes the threshold voltage through the back-bias effect. Generally, the p-channel SOI MOSFET has lower impact ionization than its n-channel counterpart. However, as the channel doping density increases and/or the channel length becomes shorter, more impact ionization occurs. Therefore, optimal conditions in device parameters must be chosen to realize VLSI SOI CMOS circuits.<>
研究了氧注入形成的SOI衬底上制备的p沟道mosfet的浮衬底效应。在p沟道SOI mosfet的饱和状态下，当电子在漏极附近的冲击电离产生并被电场扫入中性浮动衬底时，会发生扭转效应。这降低了衬底电位，从而通过反偏置效应改变了阈值电压。一般来说，p沟道SOI MOSFET比n沟道的对应物具有更低的冲击电离。然而，随着通道掺杂密度的增加和/或通道长度的缩短，会发生更多的冲击电离。因此，要实现VLSI SOI CMOS电路，必须选择器件参数的最佳条件。
{"title":"Substrate floating effects of p-channel SOI MOSFETs","authors":"Jong-Sun Lyu, S.-W. Kang, C. Lee","doi":"10.1109/SOSSOI.1990.145722","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145722","url":null,"abstract":"The floating substrate effects of p-channel MOSFETs fabricated on SOI substrates formed by oxygen implantation are studied. The kink effect occurs in the saturation regime for p-channel SOI MOSFETs when electrons are generated by impact ionization near the drain and swept by the electric field into the neutral floating substrate. This lowers substrate potential and thus changes the threshold voltage through the back-bias effect. Generally, the p-channel SOI MOSFET has lower impact ionization than its n-channel counterpart. However, as the channel doping density increases and/or the channel length becomes shorter, more impact ionization occurs. Therefore, optimal conditions in device parameters must be chosen to realize VLSI SOI CMOS circuits.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145714
A. K. Robinson, U. Bussmann, P. Hemment, V. Sharma, J. Kilner
Experiments were performed to determine the transport properties, electrical activity, and redistribution of dopants implanted into SIMOX samples with different silicon layer thicknesses. High temperature annealed SIMOX samples with silicon film thicknesses of 2000 AA (SIMOX1) and 3000 AA (SIMOX2) were implanted with As/sup +/, Sb/sup +/, B/sup +/, and P/sup +/ ions. Activation of the dopant was achieved by annealing samples at either 950 degrees C or 1150 degrees C in flowing nitrogen gas in a resistivity heated furnace. Temperature dependence of the sheet resistance following As/sup +/ ion implantation into the same set of samples is presented. The main difference is seen above 800 degrees C when significant As diffusion occurs, which leads to uniform doping in the silicon layer and a value of sheet resistance which is temperature independent above 1000 degrees C.<>
通过实验确定了注入不同硅层厚度的SIMOX样品中的掺杂剂的输运性质、电活动和再分布。将硅膜厚度分别为2000 AA (SIMOX1)和3000 AA (SIMOX2)的高温退火SIMOX样品注入As/sup +/、Sb/sup +/、B/sup +/和P/sup +/离子。通过在电阻率加热炉中流动的氮气中在950℃或1150℃下退火样品来实现掺杂剂的活化。研究了在同一组样品中注入As/sup +/离子后，薄片电阻的温度依赖性。当显著的As扩散发生时，在800℃以上可以看到主要的差异，这导致硅层中均匀掺杂，并且片电阻值在1000℃以上与温度无关。
{"title":"Dopant redistribution and activation in thin film SOI/SIMOX substrates","authors":"A. K. Robinson, U. Bussmann, P. Hemment, V. Sharma, J. Kilner","doi":"10.1109/SOSSOI.1990.145714","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145714","url":null,"abstract":"Experiments were performed to determine the transport properties, electrical activity, and redistribution of dopants implanted into SIMOX samples with different silicon layer thicknesses. High temperature annealed SIMOX samples with silicon film thicknesses of 2000 AA (SIMOX1) and 3000 AA (SIMOX2) were implanted with As/sup +/, Sb/sup +/, B/sup +/, and P/sup +/ ions. Activation of the dopant was achieved by annealing samples at either 950 degrees C or 1150 degrees C in flowing nitrogen gas in a resistivity heated furnace. Temperature dependence of the sheet resistance following As/sup +/ ion implantation into the same set of samples is presented. The main difference is seen above 800 degrees C when significant As diffusion occurs, which leads to uniform doping in the silicon layer and a value of sheet resistance which is temperature independent above 1000 degrees C.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145704
F. Namavar, E. Cortesi, N. Kalkhoran, J. Manke, B. Buchanan
Formation of ultra-thin SOI material using the SIMOX process is addressed. Research has been carried out to determine the effect of total dose, dose step, dose rate, implantation temperature, and energy on the formation of ultra-thin SIMOX material. Attempts were made to determine the lowest energy possible for the implantation of oxygen which results in the formation of high quality, thin SIMOX material. All samples were annealed at 1300 degrees C for 6 h in N/sub 2/ and analyzed using a variety of techniques, including TEM. The electrical properties of the LES samples were characterized and compared with those of standard SIMOX samples. An empirical curve of voltage breakdown versus oxide thickness for both LES and standard SIMOX samples was developed. The results show the formation of high quality SOI structures by oxygen implantation at 20-80 keV.<>
{"title":"Characterization of low energy SIMOX (LES) structures","authors":"F. Namavar, E. Cortesi, N. Kalkhoran, J. Manke, B. Buchanan","doi":"10.1109/SOSSOI.1990.145704","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145704","url":null,"abstract":"Formation of ultra-thin SOI material using the SIMOX process is addressed. Research has been carried out to determine the effect of total dose, dose step, dose rate, implantation temperature, and energy on the formation of ultra-thin SIMOX material. Attempts were made to determine the lowest energy possible for the implantation of oxygen which results in the formation of high quality, thin SIMOX material. All samples were annealed at 1300 degrees C for 6 h in N/sub 2/ and analyzed using a variety of techniques, including TEM. The electrical properties of the LES samples were characterized and compared with those of standard SIMOX samples. An empirical curve of voltage breakdown versus oxide thickness for both LES and standard SIMOX samples was developed. The results show the formation of high quality SOI structures by oxygen implantation at 20-80 keV.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116189264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-10-02DOI: 10.1109/SOSSOI.1990.145730
T. Elewa, B. Boukriss, A. Chovet, S. Cristoloveanu
The analysis of the low-frequency noise in SOI MOSFETs is addressed. A simple model is presented which takes into consideration the parallel combination of three sources of noise, associated respectively with the two interfaces and the SI film volume. This model is also convenient for the analysis of depletion-mode SOI transistors. The original point in partially-depleted N N/sup +/ N MOSFETs is that the noise contribution of the volume can be isolated by inverting the two interfaces. This model allowed the characterization of various types of SIMOX substrates fabricated by varying the implantation and annealing conditions.<>
对SOI mosfet中的低频噪声进行了分析。提出了一个简单的模型，该模型考虑了三个噪声源的并行组合，分别与两个界面和SI薄膜体积相关联。该模型也便于对耗尽型SOI晶体管进行分析。在部分耗尽的N/ N/sup +/ N mosfet中，原始点是体积的噪声贡献可以通过反转两个接口来隔离。该模型允许通过改变注入和退火条件来表征各种类型的SIMOX衬底。
{"title":"Low frequency noise spectroscopy in thin SIMOX MOS transistors","authors":"T. Elewa, B. Boukriss, A. Chovet, S. Cristoloveanu","doi":"10.1109/SOSSOI.1990.145730","DOIUrl":"https://doi.org/10.1109/SOSSOI.1990.145730","url":null,"abstract":"The analysis of the low-frequency noise in SOI MOSFETs is addressed. A simple model is presented which takes into consideration the parallel combination of three sources of noise, associated respectively with the two interfaces and the SI film volume. This model is also convenient for the analysis of depletion-mode SOI transistors. The original point in partially-depleted N N/sup +/ N MOSFETs is that the noise contribution of the volume can be isolated by inverting the two interfaces. This model allowed the characterization of various types of SIMOX substrates fabricated by varying the implantation and annealing conditions.<<ETX>>","PeriodicalId":344373,"journal":{"name":"1990 IEEE SOS/SOI Technology Conference. Proceedings","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122834556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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