Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476194
M. Tadayoni, S. Martinie, O. Rozeau, S. Hariharan, C. Raynaud, N. Do
In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.
{"title":"Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor","authors":"M. Tadayoni, S. Martinie, O. Rozeau, S. Hariharan, C. Raynaud, N. Do","doi":"10.1109/ICMTS.2016.7476194","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476194","url":null,"abstract":"In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129998151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476168
R. D’Esposito, S. Frégonèse, T. Zimmer, A. Chakravorty
This paper presents a study on the thermal impact of the back-end-of-line (BEOL) in a state-of-the-art SiGe HBT technology for high power applications. A recursive RC network is proposed to model the thermal behavior of the BEOL and is validated with measurements on dedicated test-structures in the time and frequency domain.
{"title":"Dedicated test-structures for investigation of the thermal impact of the BEOL in advanced SiGe HBTs in time and frequency domain","authors":"R. D’Esposito, S. Frégonèse, T. Zimmer, A. Chakravorty","doi":"10.1109/ICMTS.2016.7476168","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476168","url":null,"abstract":"This paper presents a study on the thermal impact of the back-end-of-line (BEOL) in a state-of-the-art SiGe HBT technology for high power applications. A recursive RC network is proposed to model the thermal behavior of the BEOL and is validated with measurements on dedicated test-structures in the time and frequency domain.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116665511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476177
Jean-Baptiste Henry, A. Cros, J. Rosa, Q. Rafhay, G. Ghibaudo
In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.
{"title":"New access resistance extraction methodology for 14nm FD-SOI technology","authors":"Jean-Baptiste Henry, A. Cros, J. Rosa, Q. Rafhay, G. Ghibaudo","doi":"10.1109/ICMTS.2016.7476177","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476177","url":null,"abstract":"In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476182
Manuel Potércau, A. Curutchet, R. D’Esposito, M. De matos, S. Frégonèse, T. Zimmer
This paper presents a new test structure set for on-wafer 3D-TRL calibration. It permits to define the reference plane below the Back-End-of-Line on Metal 1 level. Only one additional test structure is necessary to account for the coupling between input and output ports. Measurement accuracy below 1fF has been achieved.
{"title":"A test structure set for on-wafer 3D-TRL calibration","authors":"Manuel Potércau, A. Curutchet, R. D’Esposito, M. De matos, S. Frégonèse, T. Zimmer","doi":"10.1109/ICMTS.2016.7476182","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476182","url":null,"abstract":"This paper presents a new test structure set for on-wafer 3D-TRL calibration. It permits to define the reference plane below the Back-End-of-Line on Metal 1 level. Only one additional test structure is necessary to account for the coupling between input and output ports. Measurement accuracy below 1fF has been achieved.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476172
R. Kuroda, A. Teramoto, S. Sugawa
Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.
{"title":"Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors","authors":"R. Kuroda, A. Teramoto, S. Sugawa","doi":"10.1109/ICMTS.2016.7476172","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476172","url":null,"abstract":"Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129591192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476189
Nitin Dhamija, Gaurav Lalani, M. Nelson, J. Brown, Henning Spruth, P. Sharma
This paper will explain the design methodology to accurately measure the setup/hold/access time/Vmin & Fmax of memories on silicon. This architecture scheme implements the high resolution fine-tune delays of a few pico-seconds along with the coarse step sizes of ten's to hundreds of pico-seconds depending on technology, along with BIST for memory Vmin & Fmax characterization. This architecture has been implemented on one of our test-chip and silicon measurements show that measured parameters results are within 10% range of the simulated values. Implemented design scheme also ensures the serial as well as parallel measurement of these parameters of the memory instances in order to save the expensive tester time.
{"title":"Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers","authors":"Nitin Dhamija, Gaurav Lalani, M. Nelson, J. Brown, Henning Spruth, P. Sharma","doi":"10.1109/ICMTS.2016.7476189","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476189","url":null,"abstract":"This paper will explain the design methodology to accurately measure the setup/hold/access time/Vmin & Fmax of memories on silicon. This architecture scheme implements the high resolution fine-tune delays of a few pico-seconds along with the coarse step sizes of ten's to hundreds of pico-seconds depending on technology, along with BIST for memory Vmin & Fmax characterization. This architecture has been implemented on one of our test-chip and silicon measurements show that measured parameters results are within 10% range of the simulated values. Implemented design scheme also ensures the serial as well as parallel measurement of these parameters of the memory instances in order to save the expensive tester time.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132682279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476195
Shine C. Chung, Wen-Kuan Fang, Y. Hsu, J. Hsiao, L. Lin, Wen-Hua Yu
I-fuse is a fuse-based technology having (a) 1R1D cell, (b) limited programming below a critical current, and (c) small cell to improve program efficiency to pass qualification at 300°C for 4,290 hours. Test structures consist of single 1R1D structure and mini-arrays are used to characterize (a) critical current, (b) diode characteristics, and (c) cell current distribution.
{"title":"Ultra-small and ultra-reliable innovative fuses scalable from 0.35um to 28nm","authors":"Shine C. Chung, Wen-Kuan Fang, Y. Hsu, J. Hsiao, L. Lin, Wen-Hua Yu","doi":"10.1109/ICMTS.2016.7476195","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476195","url":null,"abstract":"I-fuse is a fuse-based technology having (a) 1R1D cell, (b) limited programming below a critical current, and (c) small cell to improve program efficiency to pass qualification at 300°C for 4,290 hours. Test structures consist of single 1R1D structure and mini-arrays are used to characterize (a) critical current, (b) diode characteristics, and (c) cell current distribution.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133178907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476163
Y. Okamoto, E. Lebrasseur, I. Mori, Y. Mita
We propose a test structure for an easy visual check of the progress of a MEMS dry release process. The release process of MEMS on a silicon-on-insulator (SOI) wafer is done by plasma etching of the silicon substrate (SOI handle). The Si MEMS movable structure is protected from etching by the underneath buried oxide (BOX) layer and by a Teflon layer on the walls. Improper etching conditions, however, damage the Teflon layer and harm MEMS structure. Therefore, a check method of the progress of process is essential to release MEMS structure successfully. The test structure has two purposes. First, it enables the detection of the completion of the release process. Second, it helps determining the undercut speed according to the opening sizes and plasma conditions.
{"title":"An end-point visualization test structure for all plasma dry release of Deep-RIE MEMS","authors":"Y. Okamoto, E. Lebrasseur, I. Mori, Y. Mita","doi":"10.1109/ICMTS.2016.7476163","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476163","url":null,"abstract":"We propose a test structure for an easy visual check of the progress of a MEMS dry release process. The release process of MEMS on a silicon-on-insulator (SOI) wafer is done by plasma etching of the silicon substrate (SOI handle). The Si MEMS movable structure is protected from etching by the underneath buried oxide (BOX) layer and by a Teflon layer on the walls. Improper etching conditions, however, damage the Teflon layer and harm MEMS structure. Therefore, a check method of the progress of process is essential to release MEMS structure successfully. The test structure has two purposes. First, it enables the detection of the completion of the release process. Second, it helps determining the undercut speed according to the opening sizes and plasma conditions.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476170
C. McAndrew, Alexandra Lorenzo-Cassagnes, O. Hartin
This paper presents a simple technique to correct measured transistor output characteristics for the effect of self-heating. The advantage of the proposed technique is that, unlike previous methods, it does not require special test structures, but can be applied to DC data measured from standard transistor DC measurement test structures. The technique also quantifies the thermal conductance gth. The accuracy of the technique is verified by comparison with TCAD simulations, both including and excluding self-heating, and with measured data.
{"title":"Transistor self-heating correction and thermal conductance extraction using only DC data","authors":"C. McAndrew, Alexandra Lorenzo-Cassagnes, O. Hartin","doi":"10.1109/ICMTS.2016.7476170","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476170","url":null,"abstract":"This paper presents a simple technique to correct measured transistor output characteristics for the effect of self-heating. The advantage of the proposed technique is that, unlike previous methods, it does not require special test structures, but can be applied to DC data measured from standard transistor DC measurement test structures. The technique also quantifies the thermal conductance gth. The accuracy of the technique is verified by comparison with TCAD simulations, both including and excluding self-heating, and with measured data.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476169
K. Jeppson, J. Bao, Shirong Huang, Yong Zhang, Shuangxi Sun, Yifeng Fu, Johan Liu
The design, fabrication, and use of a hotspot-producing and temperature-sensing test structure for evaluating the thermal properties of carbon nanotubes, graphene and boron nitride for cooling of electronic devices in applications like 3D integrated chip-stacks, power amplifiers and light-emitting diodes is described. The test structure is a simple meander-shaped metal resistor serving both as the hotspot and the temperature thermo-meter. By use of this test structure, the influence of emerging materials like those mentioned above on the temperature of the hotspot has been evaluated with good accuracy (±0.5°C).
{"title":"Hotspot test structures for evaluating carbon nanotube microfin coolers and graphene-like heat spreaders","authors":"K. Jeppson, J. Bao, Shirong Huang, Yong Zhang, Shuangxi Sun, Yifeng Fu, Johan Liu","doi":"10.1109/ICMTS.2016.7476169","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476169","url":null,"abstract":"The design, fabrication, and use of a hotspot-producing and temperature-sensing test structure for evaluating the thermal properties of carbon nanotubes, graphene and boron nitride for cooling of electronic devices in applications like 3D integrated chip-stacks, power amplifiers and light-emitting diodes is described. The test structure is a simple meander-shaped metal resistor serving both as the hotspot and the temperature thermo-meter. By use of this test structure, the influence of emerging materials like those mentioned above on the temperature of the hotspot has been evaluated with good accuracy (±0.5°C).","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：