Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476206
B. Tsui, Tze-Yu Fu
This work proposes a Schottky barrier extraction procedure which considers the thermionic field emission (TFE) model, image-force induced barrier lowering effect, and parasitic resistance. The accuracy of the Schottky barrier height extracted by the field emission (FE) model at forward bias and the TFE model at reverse bias is evaluated. The TFE model can obtain accurate SBH with low SBH (~0.3 eV) and high doping concentration (~1×l020 cm-3). It is thus recommended that the proposed extraction procedure could be used to study the Schottky junction precisely.
{"title":"A reliable Schottky barrier height extraction procedure","authors":"B. Tsui, Tze-Yu Fu","doi":"10.1109/ICMTS.2016.7476206","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476206","url":null,"abstract":"This work proposes a Schottky barrier extraction procedure which considers the thermionic field emission (TFE) model, image-force induced barrier lowering effect, and parasitic resistance. The accuracy of the Schottky barrier height extracted by the field emission (FE) model at forward bias and the TFE model at reverse bias is evaluated. The TFE model can obtain accurate SBH with low SBH (~0.3 eV) and high doping concentration (~1×l020 cm-3). It is thus recommended that the proposed extraction procedure could be used to study the Schottky junction precisely.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116553095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476178
L. Heiß, Andreas Lachmann, R. Schwab, G. Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, D. Schmitt-Landsiedel
This work presents an improved methodology for CMOS RF reliability assessment with on-chip AC stress circuits. Compared to previous work high frequency stress signals are not only generated on-chip, but are also monitored by an on-chip oscilloscope (OCO). Experimental data from a HKMG technology highlight that without the OCO, existing test structures often lead to misinterpreted results under AC and RF stress.
{"title":"Test structures for CMOS RF reliability assessment","authors":"L. Heiß, Andreas Lachmann, R. Schwab, G. Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, D. Schmitt-Landsiedel","doi":"10.1109/ICMTS.2016.7476178","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476178","url":null,"abstract":"This work presents an improved methodology for CMOS RF reliability assessment with on-chip AC stress circuits. Compared to previous work high frequency stress signals are not only generated on-chip, but are also monitored by an on-chip oscilloscope (OCO). Experimental data from a HKMG technology highlight that without the OCO, existing test structures often lead to misinterpreted results under AC and RF stress.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-01DOI: 10.1109/ICMTS.2016.7476174
Tsuyoshi Suzuki, S. Mori, H. Oishi, M. Bairo, Manabu Tomita, K. Ogawa, Y. Fukuzaki, H. Ohnuma
A Novel Ioff measurable MOSFET array has been developed. Body bias of peripheral circuit is controlled in order to eliminate the unwanted leakage current in peripheral circuit. SPICE simulation results indicate 10-14A or less of Ioff can be measured, and it is demonstrated that around 10-12A of Ioff can be measured directly without any additional correction measurement. Since it can be fit into scribe line, Ion and Ioff can be measured with high accuracy for plenty of MOSFETs during mass production. In addition, MOSFET characteristics depending on various types of layout parameters will be able to extract efficiently.
{"title":"Advanced ioff measureable MOSFET array with eliminating leakage current of peripheral circuits","authors":"Tsuyoshi Suzuki, S. Mori, H. Oishi, M. Bairo, Manabu Tomita, K. Ogawa, Y. Fukuzaki, H. Ohnuma","doi":"10.1109/ICMTS.2016.7476174","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476174","url":null,"abstract":"A Novel Ioff measurable MOSFET array has been developed. Body bias of peripheral circuit is controlled in order to eliminate the unwanted leakage current in peripheral circuit. SPICE simulation results indicate 10-14A or less of Ioff can be measured, and it is demonstrated that around 10-12A of Ioff can be measured directly without any additional correction measurement. Since it can be fit into scribe line, Ion and Ioff can be measured with high accuracy for plenty of MOSFETs during mass production. In addition, MOSFET characteristics depending on various types of layout parameters will be able to extract efficiently.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124648456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-01DOI: 10.1109/ICMTS.2016.7476167
T. Matsuda, Haruka Demachi, H. Iwata, T. Hatakeyama, T. Ohzone
A test structure for analysis of temperature distributions and effects of metal wires on thermal properties in stacked IC is presented. The effects on the temperature distributions and transient phenomena in the single die and the stacked ICs were analyzed. The heat transfer in the metal wires affects the temperature distributions, which are consistent with the thermal simulation results. The test structure can provide an effective way for analysis of thermal properties in various LSIs.
{"title":"A test structure for analysis of metal wire effect on temperature distribution in stacked IC","authors":"T. Matsuda, Haruka Demachi, H. Iwata, T. Hatakeyama, T. Ohzone","doi":"10.1109/ICMTS.2016.7476167","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476167","url":null,"abstract":"A test structure for analysis of temperature distributions and effects of metal wires on thermal properties in stacked IC is presented. The effects on the temperature distributions and transient phenomena in the single die and the stacked ICs were analyzed. The heat transfer in the metal wires affects the temperature distributions, which are consistent with the thermal simulation results. The test structure can provide an effective way for analysis of thermal properties in various LSIs.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125749900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-01DOI: 10.1109/ICMTS.2016.7476173
Shingo Sato, Y. Omura
A new array structure to detect the soft failure of resistive elements is reported. By adding terminals to sense local potentials and high pass filtering a bit map image, it becomes possible to detect soft failure. Thanks to a simplified peripheral circuit, the layout area is drastically reduced and an aging test with overcurrent becomes possible.
{"title":"Proposal of a new array structure to enable the detection of soft failure and the aging test with overcurrent of resistive element","authors":"Shingo Sato, Y. Omura","doi":"10.1109/ICMTS.2016.7476173","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476173","url":null,"abstract":"A new array structure to detect the soft failure of resistive elements is reported. By adding terminals to sense local potentials and high pass filtering a bit map image, it becomes possible to detect soft failure. Thanks to a simplified peripheral circuit, the layout area is drastically reduced and an aging test with overcurrent becomes possible.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129174607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-01DOI: 10.1109/ICMTS.2016.7476179
A. M. Mahfuzul Islam, Tatsuya Nakai, H. Onodera
We propose a characterization and modeling methodology for Random Telegraph Noise (RTN) induced ΔVth variation based on gate delay variation measurement. We characterize the total amount of ΔVth and model its scaling effect. A topology-reconfigurable ring oscillator (RO) is used to obtain gate delay variations between inverter stages. The devices under test are operated at near- or sub-threshold region to characterize RTN at low supply voltage. Measurement and characterization results from a 65 nm test chip show that lognormal distribution based modeling represents RTN-induced ΔVth variability precisely. We extract the model parameters and evaluate the gate size dependency of these parameters. It is found that μ1 of the lognormal distribution, lnN(μ1, σ12), does not have specific gate size dependency. Whereas, σ shows a W-a dependency to gate size rather than the commonly assumed W-1 dependency, where a is evaluated to be less than 0.5. The proposed comprehensive statistical model and its parameter dependency is suitable for performance analysis of circuits where transistors of different gate sizes are used.
{"title":"Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement","authors":"A. M. Mahfuzul Islam, Tatsuya Nakai, H. Onodera","doi":"10.1109/ICMTS.2016.7476179","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476179","url":null,"abstract":"We propose a characterization and modeling methodology for Random Telegraph Noise (RTN) induced ΔVt<sub>h</sub> variation based on gate delay variation measurement. We characterize the total amount of ΔV<sub>th</sub> and model its scaling effect. A topology-reconfigurable ring oscillator (RO) is used to obtain gate delay variations between inverter stages. The devices under test are operated at near- or sub-threshold region to characterize RTN at low supply voltage. Measurement and characterization results from a 65 nm test chip show that lognormal distribution based modeling represents RTN-induced ΔV<sub>th</sub> variability precisely. We extract the model parameters and evaluate the gate size dependency of these parameters. It is found that μ<sub>1</sub> of the lognormal distribution, lnN(μ<sub>1</sub>, σ<sub>1</sub><sup>2</sup>), does not have specific gate size dependency. Whereas, σ shows a W<sup>-a</sup> dependency to gate size rather than the commonly assumed W<sup>-1</sup> dependency, where a is evaluated to be less than 0.5. The proposed comprehensive statistical model and its parameter dependency is suitable for performance analysis of circuits where transistors of different gate sizes are used.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130792959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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