Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772346
J.F. Oliveira, J. Pedro
With the advent of wireless transceiver reconfigurability, a need has been felt to take profit of digital signal processing tools, this way increasing RF circuits' complexity and heterogeneity. Having this objective in mind, this paper presents an analytical formulation and a novel numerical method for simulating, in a very efficient way, strongly nonlinear heterogeneous RF circuits running in three different time-scales. In order to reduce the computational workload, a new multi-line double multi-rate shooting technique is proposed to operate within a multi-dimensional warped time framework. Obtained results of an illustrative circuit, reveal significant advantages in speed over previous methods recently proposed for the simulation of the same category of circuits.
{"title":"An Innovative Time-Domain Simulation Technique for Strongly Nonlinear Heterogeneous RF Circuits Operating in Diverse Time-Scales","authors":"J.F. Oliveira, J. Pedro","doi":"10.1109/EMICC.2008.4772346","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772346","url":null,"abstract":"With the advent of wireless transceiver reconfigurability, a need has been felt to take profit of digital signal processing tools, this way increasing RF circuits' complexity and heterogeneity. Having this objective in mind, this paper presents an analytical formulation and a novel numerical method for simulating, in a very efficient way, strongly nonlinear heterogeneous RF circuits running in three different time-scales. In order to reduce the computational workload, a new multi-line double multi-rate shooting technique is proposed to operate within a multi-dimensional warped time framework. Obtained results of an illustrative circuit, reveal significant advantages in speed over previous methods recently proposed for the simulation of the same category of circuits.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EUMC.2008.4751765
P. Colantonio, F. Giannini, R. Giofré, L. Piazzon
In this contribution, the design of an uneven AB-C Doherty power amplifier (DPA) in GaN technology, implementing a new approach to control the higher device harmonics, is presented. The DPA was designed to operate at 2.14 GHz and with the aim to reduce as much as possible the chip size, without losing the Doherty operating principle. The measurement results in CW conditions at 2.14 GHz had shown average drain efficiency higher than 55% at 6 dB of back-off, with a saturated output power of 37 dBm.
{"title":"GaN Doherty Amplifier With Compact Harmonic Traps","authors":"P. Colantonio, F. Giannini, R. Giofré, L. Piazzon","doi":"10.1109/EUMC.2008.4751765","DOIUrl":"https://doi.org/10.1109/EUMC.2008.4751765","url":null,"abstract":"In this contribution, the design of an uneven AB-C Doherty power amplifier (DPA) in GaN technology, implementing a new approach to control the higher device harmonics, is presented. The DPA was designed to operate at 2.14 GHz and with the aim to reduce as much as possible the chip size, without losing the Doherty operating principle. The measurement results in CW conditions at 2.14 GHz had shown average drain efficiency higher than 55% at 6 dB of back-off, with a saturated output power of 37 dBm.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128603612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772309
Hui Shen, S. Gong, N. S. Barker
This paper describes the development of DC-contact RF-MEMS SPST, SP3T, and SP4T switches implemented with a thin-film cantilever. Using aluminium as the sacrificial layer in the fabrication process, flat cantilevers are realized with a measured actuation voltage of 50~70 V. The SPST switch is used as a building block to realize more complicated SP3T and SP4T switches for use in true-time delay phase shifters. The preliminary measurements of the SP3T and SP4T switches demonstrate isolation of 20 dB and insertion loss less than 2 dB up to 50 GHz.
{"title":"DC-Contact RF MEMS Switches using Thin-Film Cantilevers","authors":"Hui Shen, S. Gong, N. S. Barker","doi":"10.1109/EMICC.2008.4772309","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772309","url":null,"abstract":"This paper describes the development of DC-contact RF-MEMS SPST, SP3T, and SP4T switches implemented with a thin-film cantilever. Using aluminium as the sacrificial layer in the fabrication process, flat cantilevers are realized with a measured actuation voltage of 50~70 V. The SPST switch is used as a building block to realize more complicated SP3T and SP4T switches for use in true-time delay phase shifters. The preliminary measurements of the SP3T and SP4T switches demonstrate isolation of 20 dB and insertion loss less than 2 dB up to 50 GHz.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130590085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772252
Ja-yol Lee, Hae-cheon Kim, Hyun-Kyu Yu
In this paper, we present the design of 52-GHz frequency synthesizer for 60 GHz WPAN application. The PLL consists of 26 GHz PLL and 52 GHz frequency doubler, generating two channels of output carriers with 2.08 GHz step by using high-speed four-modulus divider. The proposed PLL represents phase noise of - 89 dBc/Hz from 26.2 GHz carrier and - 81 dBc/Hz from 52.4 GHz carrier, at 1 MHz offset, respectively. Also, its integrated RMS phase noise from 1 MHz to 100 MHz is measured as 7.42deg Output frequency tuning range from the PLL is 50 to 53-GHz. The synthesizer including frequency doubler consumes 160 mA at 2.5V supply voltage and occupies 1.2 times 1.0 mm2 chip area.
{"title":"A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz WPAN Radio","authors":"Ja-yol Lee, Hae-cheon Kim, Hyun-Kyu Yu","doi":"10.1109/EMICC.2008.4772252","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772252","url":null,"abstract":"In this paper, we present the design of 52-GHz frequency synthesizer for 60 GHz WPAN application. The PLL consists of 26 GHz PLL and 52 GHz frequency doubler, generating two channels of output carriers with 2.08 GHz step by using high-speed four-modulus divider. The proposed PLL represents phase noise of - 89 dBc/Hz from 26.2 GHz carrier and - 81 dBc/Hz from 52.4 GHz carrier, at 1 MHz offset, respectively. Also, its integrated RMS phase noise from 1 MHz to 100 MHz is measured as 7.42deg Output frequency tuning range from the PLL is 50 to 53-GHz. The synthesizer including frequency doubler consumes 160 mA at 2.5V supply voltage and occupies 1.2 times 1.0 mm2 chip area.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772286
D. R. Burke, T. Brazil
The static and large-signal behaviour of a new model for a submicron partially-depleted (PD) body-tied (BT) silicon-on-insulator (SOI) MOSFET was recently shown to give excellent agreement with measurements. Here, we complete the model validation with a detailed study of its small-signal capabilities up to a frequency of 50 GHz. Additionally, a new direct procedure is described enabling the extraction of a full parasitic network without the need for any on-wafer de-embedding structures.
{"title":"A Non-Quasi-Static SOI MOSFET Model","authors":"D. R. Burke, T. Brazil","doi":"10.1109/EMICC.2008.4772286","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772286","url":null,"abstract":"The static and large-signal behaviour of a new model for a submicron partially-depleted (PD) body-tied (BT) silicon-on-insulator (SOI) MOSFET was recently shown to give excellent agreement with measurements. Here, we complete the model validation with a detailed study of its small-signal capabilities up to a frequency of 50 GHz. Additionally, a new direct procedure is described enabling the extraction of a full parasitic network without the need for any on-wafer de-embedding structures.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131936854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772244
A. de Souza, J. Nallatamby, M. Prigent
This paper describes a methodology to measure the low-frequency noise of InP-based transistors. These transistors have demonstrated transition frequencies (ft) greater than 200 GHz, generally achieved at current densities in excess of 200 kA/cm2. Depending on the DC current gain, this may represent base currents of some mA. For the first time, curves of Sib, Sic and Sibic for base currents of up to 3 mA are demonstrated, in excellent agreement with those obtained from one-port measurements. This is only possible with an accurate experimental characterisation of the small-signal parameters of the transistor, which are frequency-dependent due to self-heating.
{"title":"A Methodology to Characterize the Low-Frequency Noise of InP Based Transistors","authors":"A. de Souza, J. Nallatamby, M. Prigent","doi":"10.1109/EMICC.2008.4772244","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772244","url":null,"abstract":"This paper describes a methodology to measure the low-frequency noise of InP-based transistors. These transistors have demonstrated transition frequencies (ft) greater than 200 GHz, generally achieved at current densities in excess of 200 kA/cm2. Depending on the DC current gain, this may represent base currents of some mA. For the first time, curves of Sib, Sic and Sibic for base currents of up to 3 mA are demonstrated, in excellent agreement with those obtained from one-port measurements. This is only possible with an accurate experimental characterisation of the small-signal parameters of the transistor, which are frequency-dependent due to self-heating.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"s3-23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130099725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772220
G. Formicone, F. Boueri, J. Burger, W. Cheng, Y. Kim, J. Titizian
A 210 W RF LDMOS power transistor optimized for pulsed applications has been used to characterize VSWR ruggedness as a function of bias and gain compression. The ruggedness test used is the 10:1 VSWR load mismatch. The transistor, operated in class AB power amplifier, can deliver 210 W of output power when biased at 32 V (P3dB) or 36 V (P1dB), having a minimum breakdown voltage of 85 V. In both conditions the transistor passes 4:1 VSWR mismatch without degradation. We also found that when operated at 32 V and 210 W (3dB compression) the transistor passes 10:1 VSWR load mismatch without any degradation. On the contrary, when operated at 36 V (1dB compression), the transistor either goes into catastrophic failure or it survives the mismatch test with a severe power rating degradation in excess of 5%. Measured electrical data and simulated junction temperature data help explaining the different results on the VSWR ruggedness.
一种针对脉冲应用优化的210 W射频LDMOS功率晶体管被用来表征VSWR稳稳性作为偏置和增益压缩的函数。使用的坚固性测试是10:1的VSWR负载不匹配。该晶体管工作在AB类功率放大器中，当偏置在32 V (P3dB)或36 V (P1dB)时，可提供210 W的输出功率，最小击穿电压为85 V。在这两种情况下，晶体管通过4:1的VSWR失配而没有退化。我们还发现，当工作在32v和210w (3dB压缩)时，晶体管通过10:1的VSWR负载不匹配而没有任何退化。相反，当工作在36v (1dB压缩)时，晶体管要么进入灾难性故障，要么在失配测试中幸存下来，额定功率下降超过5%。测量的电气数据和模拟结温数据有助于解释VSWR坚固性的不同结果。
{"title":"Analysis of Bias Effects on VSWR Ruggedness in RF LDMOS for Avionics Applications","authors":"G. Formicone, F. Boueri, J. Burger, W. Cheng, Y. Kim, J. Titizian","doi":"10.1109/EMICC.2008.4772220","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772220","url":null,"abstract":"A 210 W RF LDMOS power transistor optimized for pulsed applications has been used to characterize VSWR ruggedness as a function of bias and gain compression. The ruggedness test used is the 10:1 VSWR load mismatch. The transistor, operated in class AB power amplifier, can deliver 210 W of output power when biased at 32 V (P3dB) or 36 V (P1dB), having a minimum breakdown voltage of 85 V. In both conditions the transistor passes 4:1 VSWR mismatch without degradation. We also found that when operated at 32 V and 210 W (3dB compression) the transistor passes 10:1 VSWR load mismatch without any degradation. On the contrary, when operated at 36 V (1dB compression), the transistor either goes into catastrophic failure or it survives the mismatch test with a severe power rating degradation in excess of 5%. Measured electrical data and simulated junction temperature data help explaining the different results on the VSWR ruggedness.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772264
Byron Alderman, H. Sanghera, Bertrand Thomas, David Matheson, A. Maestrini, Hui Wang, J. Treuttel, Jose V. Siles, Steve Davies, T. Narhi
Recent developments in the fabrication of GaAs integrated Schottky structures for applications above 100 GHz are presented. Two approaches are discussed; the fabrication of integrated circuits using a GaAs foundry service, coupled with the research based post-processing of these structures, and the fabrication of discrete and integrated Schottky structures using a bespoke research laboratory.
{"title":"Integrated Schottky Structures for Applications Above 100 GHz","authors":"Byron Alderman, H. Sanghera, Bertrand Thomas, David Matheson, A. Maestrini, Hui Wang, J. Treuttel, Jose V. Siles, Steve Davies, T. Narhi","doi":"10.1109/EMICC.2008.4772264","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772264","url":null,"abstract":"Recent developments in the fabrication of GaAs integrated Schottky structures for applications above 100 GHz are presented. Two approaches are discussed; the fabrication of integrated circuits using a GaAs foundry service, coupled with the research based post-processing of these structures, and the fabrication of discrete and integrated Schottky structures using a bespoke research laboratory.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133429318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772276
C. Pavageau, O. Dupuis, M. Dehan, B. Parvais, G. Carchon, W. Raedt
This paper demonstrates a broadband LNA for 60-GHz WPAN and a 92-GHz low-power distributed amplifier (DA) in an advanced CMOS technology. A post-processed technology (above-IC), used for packaging and bonding pads redistribution, provides ultra-low-loss on-chip passives in a cost-effective solution. In the WPAN bandwidth (57-64 GHz), the LNA has a 13.4 dB peak gain, a NF between 5.6-6.7 dB and a gain flatness of 1.7 dB. A 3-dB bandwidth of 11 GHz is achieved. The DA shows a 6.5 dB gain and a 3-dB BW of 92 GHz, giving a 195 GHz gain-bandwidth product (GBW), for a dc power consumption of 43 mW. Thank to the asset of Above-IC, this DA performs a ratio of the GBW and power consumption of 4.31 GHz/mW, which is by far the best reported tradeoff among similar architecture in CMOS, at least 2.8 times higher than others.
{"title":"A 60-GHz LNA and a 92-GHz Low-Power Distributed Amplifier in CMOS with Above-IC","authors":"C. Pavageau, O. Dupuis, M. Dehan, B. Parvais, G. Carchon, W. Raedt","doi":"10.1109/EMICC.2008.4772276","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772276","url":null,"abstract":"This paper demonstrates a broadband LNA for 60-GHz WPAN and a 92-GHz low-power distributed amplifier (DA) in an advanced CMOS technology. A post-processed technology (above-IC), used for packaging and bonding pads redistribution, provides ultra-low-loss on-chip passives in a cost-effective solution. In the WPAN bandwidth (57-64 GHz), the LNA has a 13.4 dB peak gain, a NF between 5.6-6.7 dB and a gain flatness of 1.7 dB. A 3-dB bandwidth of 11 GHz is achieved. The DA shows a 6.5 dB gain and a 3-dB BW of 92 GHz, giving a 195 GHz gain-bandwidth product (GBW), for a dc power consumption of 43 mW. Thank to the asset of Above-IC, this DA performs a ratio of the GBW and power consumption of 4.31 GHz/mW, which is by far the best reported tradeoff among similar architecture in CMOS, at least 2.8 times higher than others.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132151740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772298
S. Bastioli, F. di Maggio, P. Farinelli, F. Giacomozzi, B. Margesin, A. Ocera, I. Pomona, M. Russo, R. Sorrentino
This work presents the design, manufacturing and packaging of a novel K-band 5-bit MEMS phase shifter for applications in Satellite COTM (Communication On The Move) Terminals. The first 4 bits are realized by using a switched line topology whereas the less significant bit consists of a loaded line section. The device has been manufactured in microstrip technology on high resistivity silicon substrate by using the 8-masks FBK MEMS process. Excellent performances were measured for the MEMS switches as well as the single bits constituting the phase shifter. The phase shifter full wave simulations show excellent performance in the frequency band of interest 20.2-21.2 GHz. Return loss and insertion loss better than 17 dB and 2 dB and phase error minor than 2 degrees are obtained for all the 2^5 phase shifter states. The design and manufacturing of the low cost packaging solution is also presented.
{"title":"Design Manufacturing and Packaging of a 5-bit K-Band MEMS Phase Shifter","authors":"S. Bastioli, F. di Maggio, P. Farinelli, F. Giacomozzi, B. Margesin, A. Ocera, I. Pomona, M. Russo, R. Sorrentino","doi":"10.1109/EMICC.2008.4772298","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772298","url":null,"abstract":"This work presents the design, manufacturing and packaging of a novel K-band 5-bit MEMS phase shifter for applications in Satellite COTM (Communication On The Move) Terminals. The first 4 bits are realized by using a switched line topology whereas the less significant bit consists of a loaded line section. The device has been manufactured in microstrip technology on high resistivity silicon substrate by using the 8-masks FBK MEMS process. Excellent performances were measured for the MEMS switches as well as the single bits constituting the phase shifter. The phase shifter full wave simulations show excellent performance in the frequency band of interest 20.2-21.2 GHz. Return loss and insertion loss better than 17 dB and 2 dB and phase error minor than 2 degrees are obtained for all the 2^5 phase shifter states. The design and manufacturing of the low cost packaging solution is also presented.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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