Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772283
M. Rudolph
This paper gives an overview on recent achievements in the modeling of GaAs or InP based HBTs. The emphasis lies on the description of weakly nonlinear behavior, and on advanced descriptions for 1/f and shot noise for nonlinear simulation. Although compact HBT modeling already reached a high level of accuracy, certain limitations remain that will also be addressed.
{"title":"Current Trends and Challenges in III-V HBT Compact Modeling","authors":"M. Rudolph","doi":"10.1109/EMICC.2008.4772283","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772283","url":null,"abstract":"This paper gives an overview on recent achievements in the modeling of GaAs or InP based HBTs. The emphasis lies on the description of weakly nonlinear behavior, and on advanced descriptions for 1/f and shot noise for nonlinear simulation. Although compact HBT modeling already reached a high level of accuracy, certain limitations remain that will also be addressed.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772310
V. Gutta, A. Fattorini, A. Parker, J. Harvey
An investigation in to the asymmetry of the current-voltage characteristics and the local-oscillator breakthrough in anti-parallel diode sub-harmonic mixers is presented. Twenty nine bare anti-parallel diode pair circuits, have been used to identify those aspects of the diode geometry, that have a strong influence on the diode mismatch and consequently the local-oscillator breakthrough. The circuits were fabricated on a six-inch gallium arsenide high electron mobility transistor process.
{"title":"Impact of Diode Geometry on Local Oscillator Breakthrough in Sub-Harmonic Mixers","authors":"V. Gutta, A. Fattorini, A. Parker, J. Harvey","doi":"10.1109/EMICC.2008.4772310","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772310","url":null,"abstract":"An investigation in to the asymmetry of the current-voltage characteristics and the local-oscillator breakthrough in anti-parallel diode sub-harmonic mixers is presented. Twenty nine bare anti-parallel diode pair circuits, have been used to identify those aspects of the diode geometry, that have a strong influence on the diode mismatch and consequently the local-oscillator breakthrough. The circuits were fabricated on a six-inch gallium arsenide high electron mobility transistor process.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772277
M. Ferndahl, T. Johansson, H. Zirath
Five different 20 GHz power amplifiers in 130 nm CMOS technology have been designed and characterized. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, as well as the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor level characterization using load pull measurements on 1 mm gate width transistors yielded 148 mW output power. These numbers are, to the authors' knowledge, the highest reported for CMOS above 10 GHz. Transistor modeling and layout for power amplifiers are also discussed.
{"title":"20 GHz Power Amplifier Design in 130 nm CMOS","authors":"M. Ferndahl, T. Johansson, H. Zirath","doi":"10.1109/EMICC.2008.4772277","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772277","url":null,"abstract":"Five different 20 GHz power amplifiers in 130 nm CMOS technology have been designed and characterized. The power amplifiers explore single versus cascode configuration, smaller versus larger transistor sizes, as well as the combination of two amplifiers using power splitters/combiners. A maximum output power of 63 mW at 20 GHz was achieved. Transistor level characterization using load pull measurements on 1 mm gate width transistors yielded 148 mW output power. These numbers are, to the authors' knowledge, the highest reported for CMOS above 10 GHz. Transistor modeling and layout for power amplifiers are also discussed.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772251
D. Chang, S. Javvadi, C. Muñoz, J. Abele, A. Hadiashar, M. Lugin, R. Quintal, G. Dawe
A flexible ADC for a multi-band and multi-mode transceiver is presented. It can be reconfigured between pipeline and DeltaSigma architectures for power optimum operation in WLAN/WiMAX and GSM/CDMA2000/WCDMA, respectively. A maximum dynamic range of 76 dB with less than 1 mW at 1.2 V supply was achieved using voltage scaling and closed-loop opamp design techniques. The prototype was built in 0.13 mum CMOS and the active die area is 0.43 mm2.
{"title":"A 1.2V Programmable ADC for a Multi-Mode Transceiver in 0.13μm CMOS","authors":"D. Chang, S. Javvadi, C. Muñoz, J. Abele, A. Hadiashar, M. Lugin, R. Quintal, G. Dawe","doi":"10.1109/EMICC.2008.4772251","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772251","url":null,"abstract":"A flexible ADC for a multi-band and multi-mode transceiver is presented. It can be reconfigured between pipeline and DeltaSigma architectures for power optimum operation in WLAN/WiMAX and GSM/CDMA2000/WCDMA, respectively. A maximum dynamic range of 76 dB with less than 1 mW at 1.2 V supply was achieved using voltage scaling and closed-loop opamp design techniques. The prototype was built in 0.13 mum CMOS and the active die area is 0.43 mm2.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114236449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772312
M. Nezhad-Ahmadi, B. Biglarbegian, H. Mirzaei, Safieddin Safavi-Naieini
An optimum gate-loaded cascode topology for maximizing the gain of a stable CMOS amplifier in micro/millimeter wave band is presented. By adding a piece of transmission line in the gate of cascode transistor, choosing an appropriate matching circuit that includes biasing, and exploiting the proper transmission line structure the gain per stage of CMOS amplifier can be increased and an optimum design can be achieved. Based on this topology a 28 GHz amplifier in 0.18 mum CMOS technology has been designed and fabricated. Gain of about 16 dB was measured for a two-stage cascode at 28 GHz in a 0.18 mum CMOS technology.
提出了一种可使微/毫米波稳定CMOS放大器增益最大化的最佳栅极负载级联码拓扑结构。通过在级联晶体管栅极中增加一段传输线，选择合适的含偏置的匹配电路，利用合适的传输线结构，可以提高CMOS放大器的每级增益，实现优化设计。基于该拓扑结构，设计并制作了一个0.18 μ m CMOS技术的28 GHz放大器。采用0.18 μ m CMOS技术，在28 GHz频率下测量了两级级联码的增益约为16 dB。
{"title":"An Optimum Cascode Topology for High Gain Micro/Millimeter Wave CMOS Amplifier Design","authors":"M. Nezhad-Ahmadi, B. Biglarbegian, H. Mirzaei, Safieddin Safavi-Naieini","doi":"10.1109/EMICC.2008.4772312","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772312","url":null,"abstract":"An optimum gate-loaded cascode topology for maximizing the gain of a stable CMOS amplifier in micro/millimeter wave band is presented. By adding a piece of transmission line in the gate of cascode transistor, choosing an appropriate matching circuit that includes biasing, and exploiting the proper transmission line structure the gain per stage of CMOS amplifier can be increased and an optimum design can be achieved. Based on this topology a 28 GHz amplifier in 0.18 mum CMOS technology has been designed and fabricated. Gain of about 16 dB was measured for a two-stage cascode at 28 GHz in a 0.18 mum CMOS technology.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116869780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772269
O. Bengtsson, L. Vestling, J. Olsson
In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.
{"title":"A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications","authors":"O. Bengtsson, L. Vestling, J. Olsson","doi":"10.1109/EMICC.2008.4772269","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772269","url":null,"abstract":"In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122858383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772313
D. Dubuc, C. Bordas, K. Grenier
This paper describes a design methodology specifically developed for RF-MEMS based tuner, which translates into optimal performances in terms of both impedance coverage of the Smith Chart and |GammaMAX| value. The design methodology is moreover associated with an RF-MEMS technology developed for medium power (in the watt range) applications and exhibiting a design robustness regarding the capacitive RF-MEMS contact quality. A tuner has been designed thanks to this efficient procedure, fabricated and measured. The circuit exhibits excellent measured RF-performances: a wide impedance coverage is reached from the first test with a value of |GammaMAX| of 0.82 at 14 GHz.
{"title":"Efficient Design Methodology of RF-MEMS based Tuner","authors":"D. Dubuc, C. Bordas, K. Grenier","doi":"10.1109/EMICC.2008.4772313","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772313","url":null,"abstract":"This paper describes a design methodology specifically developed for RF-MEMS based tuner, which translates into optimal performances in terms of both impedance coverage of the Smith Chart and |GammaMAX| value. The design methodology is moreover associated with an RF-MEMS technology developed for medium power (in the watt range) applications and exhibiting a design robustness regarding the capacitive RF-MEMS contact quality. A tuner has been designed thanks to this efficient procedure, fabricated and measured. The circuit exhibits excellent measured RF-performances: a wide impedance coverage is reached from the first test with a value of |GammaMAX| of 0.82 at 14 GHz.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128054754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772265
J. Stake, T. Bryllert, A. Olsen, J. Vukusic
We present progress and status of heterostructure barrier varactor quintupler sources for 170 GHz and 210 GHz (G-band). The source modules feature an ultra-compact waveguide block design, and a microstrip matching circuit on high-thermal-conductivity AlN to improve the power handling capability. Furthermore, we present progress on design and fabrication of integrated HBV circuits for terahertz applications.
{"title":"Heterostructure Barrier Varactor Quintuplers for Terahertz Applications","authors":"J. Stake, T. Bryllert, A. Olsen, J. Vukusic","doi":"10.1109/EMICC.2008.4772265","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772265","url":null,"abstract":"We present progress and status of heterostructure barrier varactor quintupler sources for 170 GHz and 210 GHz (G-band). The source modules feature an ultra-compact waveguide block design, and a microstrip matching circuit on high-thermal-conductivity AlN to improve the power handling capability. Furthermore, we present progress on design and fabrication of integrated HBV circuits for terahertz applications.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772318
A. Khy, B. Huyart, H. Teillet
This paper presents the design and performance of a highly linear (40.5 - 43.5)GHz MMIC single balanced pHEMT resistive up-converter mixer dedicated to LMDS applications. The mixer achieves good performance in terms of conversion loss which is about 6 -7 dB and LO/RF isolation that is better than 30 dB under LO power equal to 14 dBm. The main feature of the mixer is its high linearity since it presents an RF output power@1 dB compression point (Pout@1 dB) superior to 5 dBm in the (39.5 - 43.5)GHz frequency range. The measured OIP3 is equal to 20.2 dBm at 40.5 GHz and 12.2 dBm at 42 GHz. The 2 mmtimes1.5 mm circuit was fabricated using the D01PH (0.13 mum GaAs depletion mode pHEMT) process provided by the OMMIC foundry. To the best of our knowledge, this is the most linear up-converter mixer reported to date in this frequency range associated with as low conversion loss.
{"title":"A Highly Linear (40.5 - 43.5) GHz MMIC Single Balanced pHEMT Resistive Up-Converter Mixer for LMDS Applications","authors":"A. Khy, B. Huyart, H. Teillet","doi":"10.1109/EMICC.2008.4772318","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772318","url":null,"abstract":"This paper presents the design and performance of a highly linear (40.5 - 43.5)GHz MMIC single balanced pHEMT resistive up-converter mixer dedicated to LMDS applications. The mixer achieves good performance in terms of conversion loss which is about 6 -7 dB and LO/RF isolation that is better than 30 dB under LO power equal to 14 dBm. The main feature of the mixer is its high linearity since it presents an RF output power@1 dB compression point (Pout@1 dB) superior to 5 dBm in the (39.5 - 43.5)GHz frequency range. The measured OIP3 is equal to 20.2 dBm at 40.5 GHz and 12.2 dBm at 42 GHz. The 2 mmtimes1.5 mm circuit was fabricated using the D01PH (0.13 mum GaAs depletion mode pHEMT) process provided by the OMMIC foundry. To the best of our knowledge, this is the most linear up-converter mixer reported to date in this frequency range associated with as low conversion loss.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121613415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772311
J. Guo, Yi-Min Lin, Y. Tsai
RF noise shielding methods with different coverage areas (Pad and TML shielding) were implemented in two port test structures adopting 100-nm MOSFETs. Noise measurement reveals an effective suppression of NFmin but increase of NF50, simultaneously from the shielding methods. The suppression of NFmin is contributed from the reduction of Re(Yopt) while the noise resistance Rn is kept nearly the same. A lossy substrate model developed in our original work for a standard structure without shielding can be easily extended based on the layout and topology of the shielding schemes to predict the noise shielding effect and explain the mechanisms. The extended lossy substrate model indicates that the elimination of substrate loss represented by substrate RLC networks is the major mechanism contributing the reduction of NFmin. However, the increase of parasitic capacitance generated from the shielding structures is responsible for the degradation of fT and NF50. The results provide an important insight and guideline for low noise RF circuit design.
{"title":"RF Noise Shielding Method and Modelling for Nanoscale MOSFET","authors":"J. Guo, Yi-Min Lin, Y. Tsai","doi":"10.1109/EMICC.2008.4772311","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772311","url":null,"abstract":"RF noise shielding methods with different coverage areas (Pad and TML shielding) were implemented in two port test structures adopting 100-nm MOSFETs. Noise measurement reveals an effective suppression of NFmin but increase of NF50, simultaneously from the shielding methods. The suppression of NFmin is contributed from the reduction of Re(Yopt) while the noise resistance Rn is kept nearly the same. A lossy substrate model developed in our original work for a standard structure without shielding can be easily extended based on the layout and topology of the shielding schemes to predict the noise shielding effect and explain the mechanisms. The extended lossy substrate model indicates that the elimination of substrate loss represented by substrate RLC networks is the major mechanism contributing the reduction of NFmin. However, the increase of parasitic capacitance generated from the shielding structures is responsible for the degradation of fT and NF50. The results provide an important insight and guideline for low noise RF circuit design.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121828604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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