Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772245
J. Tinoco, J. Raskin
Adequate modelling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We present the relative sensitivity of each published RF characterization method to the measurement noise floor of Vectorial Network Analyzer. Additionally, the Bracale's method demonstrates to be less sensitive to the measurement noise but the extracted resistance values suffer from the mobility degradation due to the transversal electric field and the asymmetry of the device under test. Based on these theoretical and experimental results we propose a revised extraction procedure suitable for deep submicron transistors.
{"title":"Revised RF Extraction Methods for Deep Submicron MOSFETs","authors":"J. Tinoco, J. Raskin","doi":"10.1109/EMICC.2008.4772245","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772245","url":null,"abstract":"Adequate modelling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We present the relative sensitivity of each published RF characterization method to the measurement noise floor of Vectorial Network Analyzer. Additionally, the Bracale's method demonstrates to be less sensitive to the measurement noise but the extracted resistance values suffer from the mobility degradation due to the transversal electric field and the asymmetry of the device under test. Based on these theoretical and experimental results we propose a revised extraction procedure suitable for deep submicron transistors.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114515337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EUMC.2008.4751771
C. Jiang, G. Mekonnen, V. Krozer, T. Johansen, H. Bach
Packaging is a major problem at millimetre-wave frequencies approaching 100 GHz. In this paper we present that insertion losses in a multi-chip module (MCM) can be less IL <0.6 dB at 100 GHz. The paper also analyzes in detail resonance modes in the packages. The characteristic of conductor-backed coplanar waveguides (CBCPWs) with vias is accurately analyzed using 3D electromagnetic (EM) simulation over a wide frequency range. Patch antenna mode resonances are identified as a major origin of resonances in simulated and measured transmission characteristics of the CBCPW with vias. Based on EM simulations, we propose several optimized arrangements for vias and bonding wires placement, to efficiently suppress the resonances and achieve excellent transmission performance of the PD module packaging. Based on our simulated results we postulate that it is possible to obtain resonance-free electrical transmission in the PD package with IL <0.6 dB over a frequency from DC to 110 GHz.
{"title":"Packaging Aspects of Photodetector Modules for 100 Gbit/s Ethernet Applications","authors":"C. Jiang, G. Mekonnen, V. Krozer, T. Johansen, H. Bach","doi":"10.1109/EUMC.2008.4751771","DOIUrl":"https://doi.org/10.1109/EUMC.2008.4751771","url":null,"abstract":"Packaging is a major problem at millimetre-wave frequencies approaching 100 GHz. In this paper we present that insertion losses in a multi-chip module (MCM) can be less IL <0.6 dB at 100 GHz. The paper also analyzes in detail resonance modes in the packages. The characteristic of conductor-backed coplanar waveguides (CBCPWs) with vias is accurately analyzed using 3D electromagnetic (EM) simulation over a wide frequency range. Patch antenna mode resonances are identified as a major origin of resonances in simulated and measured transmission characteristics of the CBCPW with vias. Based on EM simulations, we propose several optimized arrangements for vias and bonding wires placement, to efficiently suppress the resonances and achieve excellent transmission performance of the PD module packaging. Based on our simulated results we postulate that it is possible to obtain resonance-free electrical transmission in the PD package with IL <0.6 dB over a frequency from DC to 110 GHz.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772343
A. Cidronali, N. Giovannelli, I. Magrini, G. Manes
The aim of this paper is to focus on the dual band power amplifier design and characterization as an enabling technology for beyond 3G wireless systems. The design approach within a full characterization of the dual band power amplifier is given in the paper. For 1.98 GHz 3 GPP UL WCDMA and 3.42 GHz 5 MHz 16QAM WiMAX digital systems, the dual-band concurrent exhibited simultaneous peak power levels of 24 dBm and 17 dBm respectively, to maintain ACPR and EVM within the regulatory requirements. A performance discussion is then outlined with respect to multi band multi module PA architectures for software defined radio wireless transmitters.
{"title":"Compact Concurrent Dual-Band Power Amplifier for 1.9GHz WCDMA and 3.5GHz OFDM Wireless Systems","authors":"A. Cidronali, N. Giovannelli, I. Magrini, G. Manes","doi":"10.1109/EMICC.2008.4772343","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772343","url":null,"abstract":"The aim of this paper is to focus on the dual band power amplifier design and characterization as an enabling technology for beyond 3G wireless systems. The design approach within a full characterization of the dual band power amplifier is given in the paper. For 1.98 GHz 3 GPP UL WCDMA and 3.42 GHz 5 MHz 16QAM WiMAX digital systems, the dual-band concurrent exhibited simultaneous peak power levels of 24 dBm and 17 dBm respectively, to maintain ACPR and EVM within the regulatory requirements. A performance discussion is then outlined with respect to multi band multi module PA architectures for software defined radio wireless transmitters.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124870477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772301
M. Wei, Sheng-Fuh Chang, Yu-Chun Liu
A low-power ultra-compact CMOS low-noise amplifier (LNA) in a shunt-resonating current-reused topology is presented. The common-source transistors are connected with a shunt-resonating inter-stage match network such that the bias current is shared to have low power consumption and RF signal is doubly amplified to have high gain and low noise figure. The implemented 0.18 mum CMOS LNA achieves 15.2 dB power gain and 3.0 dB noise figure, while only consuming 1.81 mW. Compared with previously published current-reused LNA, the proposed LNA has smallest chip size of 0.28 mm2, excluding the I/O pads, and the highest FOM of 2.77.
提出了一种并联谐振电流复用拓扑结构的低功耗超小型CMOS低噪声放大器。共源晶体管通过并联谐振级间匹配网络连接，使偏置电流共享，具有低功耗，射频信号被加倍放大，具有高增益和低噪声系数。所实现的0.18 μ m CMOS LNA功率增益为15.2 dB，噪声系数为3.0 dB，功耗仅为1.81 mW。与先前发布的电流复用LNA相比，该LNA的芯片尺寸最小，为0.28 mm2(不包括I/O焊盘)，FOM最高，为2.77。
{"title":"A Low-Power Ultra-Compact CMOS LNA with Shunt-Resonating Current-Reused Topology","authors":"M. Wei, Sheng-Fuh Chang, Yu-Chun Liu","doi":"10.1109/EMICC.2008.4772301","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772301","url":null,"abstract":"A low-power ultra-compact CMOS low-noise amplifier (LNA) in a shunt-resonating current-reused topology is presented. The common-source transistors are connected with a shunt-resonating inter-stage match network such that the bias current is shared to have low power consumption and RF signal is doubly amplified to have high gain and low noise figure. The implemented 0.18 mum CMOS LNA achieves 15.2 dB power gain and 3.0 dB noise figure, while only consuming 1.81 mW. Compared with previously published current-reused LNA, the proposed LNA has smallest chip size of 0.28 mm2, excluding the I/O pads, and the highest FOM of 2.77.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125368912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772227
Peter Abele, Michael Schäfer, J. Splettstößer, Martin Thinnes, Hermann Stieglauer, Dag Behammer
In this work we investigate device simulations for a sensitivity analyses on the PH25 single recess pHEMT process. The relation of the most critical process and epitaxial parameters on the electrical DC parameters are presented and discussed. The control of the recess etching is an important process module in stabilizing the electrical parameters. Improving the recess etching resulted in a significant reduced spread of the electrical parameters.
{"title":"Process Stabilization and Sensitivity Analyses of a Single Recess GaAs pHEMT Process using Device Simulations","authors":"Peter Abele, Michael Schäfer, J. Splettstößer, Martin Thinnes, Hermann Stieglauer, Dag Behammer","doi":"10.1109/EMICC.2008.4772227","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772227","url":null,"abstract":"In this work we investigate device simulations for a sensitivity analyses on the PH25 single recess pHEMT process. The relation of the most critical process and epitaxial parameters on the electrical DC parameters are presented and discussed. The control of the recess etching is an important process module in stabilizing the electrical parameters. Improving the recess etching resulted in a significant reduced spread of the electrical parameters.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772295
M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, B. Mulvaney, K. Gullapalli
A new oscillator macromodel in the form of phase differential equation is proposed. The comparison of new macromodel with the Adler equation and with the macromodel based on Floquet theory is presented. It is shown that the proposed approach allows to perform phase noise analysis of any oscillator circuit with arbitrary periodic injection waveform. The approach can be easily implemented into a circuit simulator.
{"title":"New Macromodeling Approach to Phase Noise Analysis of Locked Oscillators","authors":"M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, B. Mulvaney, K. Gullapalli","doi":"10.1109/EMICC.2008.4772295","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772295","url":null,"abstract":"A new oscillator macromodel in the form of phase differential equation is proposed. The comparison of new macromodel with the Adler equation and with the macromodel based on Floquet theory is presented. It is shown that the proposed approach allows to perform phase noise analysis of any oscillator circuit with arbitrary periodic injection waveform. The approach can be easily implemented into a circuit simulator.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772274
V. Fusco, C. Wang, T. Pochiraju
A novel method for directly producing QPSK modulation from baseband IQ signals is presented. The key feature of the architecture is the absence of mixers and as a result unwanted mixing products. A broadband MMIC modulator chip is demonstrated at V band to showcase the performance of the modulator. It completely covers the world wide frequency band allocation for the forthcoming 60 GHz indoor wireless communication system. The power consumption of the circuit is less than 50 mW and its 1 dB compression point is 17 dBm. The overall insertion loss of the circuit is 9.5plusmn2 dB over the frequency band 35-65 GHz with phase state errors below plusmn15 deg. Up to 2 Gbps bit rate signaling rates should be achievable using the circuit.
{"title":"35-65GHz MMIC QPSK Modulator","authors":"V. Fusco, C. Wang, T. Pochiraju","doi":"10.1109/EMICC.2008.4772274","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772274","url":null,"abstract":"A novel method for directly producing QPSK modulation from baseband IQ signals is presented. The key feature of the architecture is the absence of mixers and as a result unwanted mixing products. A broadband MMIC modulator chip is demonstrated at V band to showcase the performance of the modulator. It completely covers the world wide frequency band allocation for the forthcoming 60 GHz indoor wireless communication system. The power consumption of the circuit is less than 50 mW and its 1 dB compression point is 17 dBm. The overall insertion loss of the circuit is 9.5plusmn2 dB over the frequency band 35-65 GHz with phase state errors below plusmn15 deg. Up to 2 Gbps bit rate signaling rates should be achievable using the circuit.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"76 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772216
G. Boeck, V. Subramanian, W. Keusgen, Van-Hoang Do
A 60 GHz SiGe HBT chipset for high speed wireless communication systems has been developed. The functionalities of LNA, up-converter, down-converter and PA have been realized with good performance. Design strategy, achieved results and comparison with state-of-the-art work will be presented. The work proves that single chip integration of the whole 60 GHz RF-frond-end will be possible using silicon based technologies.
{"title":"A 60 GHz SiGe HBT Chip Set","authors":"G. Boeck, V. Subramanian, W. Keusgen, Van-Hoang Do","doi":"10.1109/EMICC.2008.4772216","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772216","url":null,"abstract":"A 60 GHz SiGe HBT chipset for high speed wireless communication systems has been developed. The functionalities of LNA, up-converter, down-converter and PA have been realized with good performance. Design strategy, achieved results and comparison with state-of-the-art work will be presented. The work proves that single chip integration of the whole 60 GHz RF-frond-end will be possible using silicon based technologies.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772229
Y. Mo, E. Skafidas, R. Evans, I. Mareels
In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the divider's performance. The proposed CML frequency divider contains four spiral inductors and is fabricated on standard 130-nm CMOS technology. The division range of the proposed divider was measured from 30 GHz to 50 GHz with 11.7 mW power dissipation at a 1.5-V supply voltage.
{"title":"Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequency Divider Based on LC-tank","authors":"Y. Mo, E. Skafidas, R. Evans, I. Mareels","doi":"10.1109/EMICC.2008.4772229","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772229","url":null,"abstract":"In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the divider's performance. The proposed CML frequency divider contains four spiral inductors and is fabricated on standard 130-nm CMOS technology. The division range of the proposed divider was measured from 30 GHz to 50 GHz with 11.7 mW power dissipation at a 1.5-V supply voltage.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-10-01DOI: 10.1109/EMICC.2008.4772263
E. Yi Chang, C. Kuo, H. Hsu, Chia-Yuan Chang
80-nm InAs channel HEMTs with different lattice matched sub-channels, In0.53Ga0.47As and In0.7Ga0.3As, have been fabricated. The device with InAs/In0.7Ga0.3As composite channel exhibits high drain current density (1101 mA/mm), and high transconductance (1605 mS/mm) at drain bias VDS = 0.8 V. The high current gain cutoff frequency (ft) of 360 GHz and maximum oscillation frequency (fmax) of 380 GHz of the device with InAs/In0.7Ga0.3As were obtained at VDS = 0.7 V in comparison to the InAs/In0.53Ga0.47 As channel HEMTs with ft = 310 and fmax = 330 GHz. This is due to the high electron mobility and electron confinement in the InAs/In0.7Ga0.3As channel. In addition, a low gate delay time 0.84 psec was obtained at VDS = 0.5 V. The excellent performance of the InAs channel HEMTs demonstrated in this study shows great potential for high speed and very low power logic applications with the optimal design of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel.
{"title":"InAs/In1-xGaxAs Composite Channel High Electron Mobility Transistors for High Speed Applications","authors":"E. Yi Chang, C. Kuo, H. Hsu, Chia-Yuan Chang","doi":"10.1109/EMICC.2008.4772263","DOIUrl":"https://doi.org/10.1109/EMICC.2008.4772263","url":null,"abstract":"80-nm InAs channel HEMTs with different lattice matched sub-channels, In<sub>0.53</sub>Ga<sub>0.47</sub>As and In<sub>0.7</sub>Ga<sub>0.3</sub>As, have been fabricated. The device with InAs/In<sub>0.7</sub>Ga<sub>0.3</sub>As composite channel exhibits high drain current density (1101 mA/mm), and high transconductance (1605 mS/mm) at drain bias V<sub>DS</sub> = 0.8 V. The high current gain cutoff frequency (f<sub>t</sub>) of 360 GHz and maximum oscillation frequency (f<sub>max</sub>) of 380 GHz of the device with InAs/In<sub>0.7</sub>Ga<sub>0.3</sub>As were obtained at V<sub>DS</sub> = 0.7 V in comparison to the InAs/In<sub>0.53</sub>Ga<sub>0.47</sub> As channel HEMTs with f<sub>t</sub> = 310 and f<sub>max</sub> = 330 GHz. This is due to the high electron mobility and electron confinement in the InAs/In<sub>0.7</sub>Ga<sub>0.3</sub>As channel. In addition, a low gate delay time 0.84 psec was obtained at V<sub>DS</sub> = 0.5 V. The excellent performance of the InAs channel HEMTs demonstrated in this study shows great potential for high speed and very low power logic applications with the optimal design of In<sub>0.7</sub>Ga<sub>0.3</sub>As/InAs/In<sub>0.7</sub>Ga<sub>0.3</sub>As composite channel.","PeriodicalId":344657,"journal":{"name":"2008 European Microwave Integrated Circuit Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126200984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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