Test cost is becoming a more and more significant portion of the cost structure in advanced semiconductor products. To address this issue, we propose HOY - a novel wireless test system with enhanced embedded test features. We present the concept, architecture, and test flow for future semiconductor products tested by HOY. Necessary technologies for the success of HOY also are presented, though most of which require further investigation. A preliminary demonstration system has been constructed, and experiments are being conducted
{"title":"The HOY Tester-Can IC Testing Go Wireless?","authors":"Cheng-Wen Wu, Chih-Tsun Huang, Shi-Yu Huang, Po-Chiun Huang, Tsin-Yuan Chang, Yu-Tsao Hsing","doi":"10.1109/VDAT.2006.258155","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258155","url":null,"abstract":"Test cost is becoming a more and more significant portion of the cost structure in advanced semiconductor products. To address this issue, we propose HOY - a novel wireless test system with enhanced embedded test features. We present the concept, architecture, and test flow for future semiconductor products tested by HOY. Necessary technologies for the success of HOY also are presented, though most of which require further investigation. A preliminary demonstration system has been constructed, and experiments are being conducted","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128241594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258121
K. Shi, D. Howard
Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency
{"title":"Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum","authors":"K. Shi, D. Howard","doi":"10.1109/VDAT.2006.258121","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258121","url":null,"abstract":"Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130207050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258107
Shimohigashi
Summary form only given. The old good days, when the process and the design engineers were in each technology silo and didn't need to interact frequently, have gone. As the device size shrinks to nanometer scale and the integration level exceeds well over giga scale, the landscape of technology developments has become very different from the past. The variability, for example, becomes a critical issue not only for performance, but also for production yield. The problems, which have been seen as secondary for long time, suddenly come into play and will grow according to the device size reduction. The solution is DFM, design for manufacturing. The DFM will not be done without collaborations between various technology parties, such as process, design, mask, EDA, and so on. The DFM will give us a big challenge and opportunity in nanometer era. In this talk, the perspective of the DFM was presented and how the work-flow for making chips should be changed was discussed. The DFM initiative under a collaborative consortium scheme in Japan were also presented
{"title":"DFM in Perspective - A Challenge and Opportunity in Nanometer Era -","authors":"Shimohigashi","doi":"10.1109/VDAT.2006.258107","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258107","url":null,"abstract":"Summary form only given. The old good days, when the process and the design engineers were in each technology silo and didn't need to interact frequently, have gone. As the device size shrinks to nanometer scale and the integration level exceeds well over giga scale, the landscape of technology developments has become very different from the past. The variability, for example, becomes a critical issue not only for performance, but also for production yield. The problems, which have been seen as secondary for long time, suddenly come into play and will grow according to the device size reduction. The solution is DFM, design for manufacturing. The DFM will not be done without collaborations between various technology parties, such as process, design, mask, EDA, and so on. The DFM will give us a big challenge and opportunity in nanometer era. In this talk, the perspective of the DFM was presented and how the work-flow for making chips should be changed was discussed. The DFM initiative under a collaborative consortium scheme in Japan were also presented","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126663632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258129
Wei-Chang Li, Chao-Shiun Wang, Chorng-Kuang Wang
This paper proposes a multi-band low noise amplifier design for WMAN and WLAN applications. The target frequency bands include licensed bands of 2.3 GHz, 2.5 ~ 2.7 GHz and 3.5 ~3.7 GHz, and un-licensed bands of ISM 2.4 GHz and U-NII 5 GHz. The LNA adopts a band selection technique that uses a multi-tap inductor with complementary switch capacitor array. The measured NFs and IIP3s of the proposed LNA are 6.5 dB and -3 dBm at 2.4 GHz, 7.6 dB and -5 dBm at 3.5 GHz, and 8.5 dB and +1 dBm at 5.2 GHz, respectively. The insertion gain S21's are 15 dB at 2.4 GHz, 17 dB at 3.5 GHz, and 15.4 dB at 5.4 GHz. Using a 0.18μm CMOS process, the multi-band LNA dissipates 14.6 mW at 2.4 GHz, and 27.7 mW at 3.5 and 5 GHz without output buffer from a 1.8-V supply voltage
{"title":"A 2.4-GHz/3.5-GHz/5-GHz multi-band LNA with complementary switched capacitor multi-tap inductor in 0.18μm CMOS","authors":"Wei-Chang Li, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/VDAT.2006.258129","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258129","url":null,"abstract":"This paper proposes a multi-band low noise amplifier design for WMAN and WLAN applications. The target frequency bands include licensed bands of 2.3 GHz, 2.5 ~ 2.7 GHz and 3.5 ~3.7 GHz, and un-licensed bands of ISM 2.4 GHz and U-NII 5 GHz. The LNA adopts a band selection technique that uses a multi-tap inductor with complementary switch capacitor array. The measured NFs and IIP3s of the proposed LNA are 6.5 dB and -3 dBm at 2.4 GHz, 7.6 dB and -5 dBm at 3.5 GHz, and 8.5 dB and +1 dBm at 5.2 GHz, respectively. The insertion gain S21's are 15 dB at 2.4 GHz, 17 dB at 3.5 GHz, and 15.4 dB at 5.4 GHz. Using a 0.18μm CMOS process, the multi-band LNA dissipates 14.6 mW at 2.4 GHz, and 27.7 mW at 3.5 and 5 GHz without output buffer from a 1.8-V supply voltage","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121055046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258173
Yun-Nan Chang, Yu-Chung Ding
In this paper, a low-power design of Viterbi decoders has been proposed based on a novel survivor path trace mechanism. By incorporating the dynamic multiple path convergence scheme, the survivor path can be determined at earlier stage such that the overall survivor memory access can be reduced. The experimental results show that the average memory reference can be reduced up to more than 30% for digital video broadcasting (DVB) application at high signal-to-noise ratio. The bit-error-rate (BER) performance of the proposed approach can be even better in some cases. This approach can lead to the reduction of power since memory operation is considered as the major power consumption of the entire decoders. An efficient VLSI architecture of Viterbi decoder for DVB standard is also presented based on the proposed design methodology. One salient feature of this architecture is that the survivor memory can be implemented by using only three single-port memory banks
{"title":"A Lower-Power Viterbi Decoder Design Methodology Based on Dynamic Survivor Path Decision","authors":"Yun-Nan Chang, Yu-Chung Ding","doi":"10.1109/VDAT.2006.258173","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258173","url":null,"abstract":"In this paper, a low-power design of Viterbi decoders has been proposed based on a novel survivor path trace mechanism. By incorporating the dynamic multiple path convergence scheme, the survivor path can be determined at earlier stage such that the overall survivor memory access can be reduced. The experimental results show that the average memory reference can be reduced up to more than 30% for digital video broadcasting (DVB) application at high signal-to-noise ratio. The bit-error-rate (BER) performance of the proposed approach can be even better in some cases. This approach can lead to the reduction of power since memory operation is considered as the major power consumption of the entire decoders. An efficient VLSI architecture of Viterbi decoder for DVB standard is also presented based on the proposed design methodology. One salient feature of this architecture is that the survivor memory can be implemented by using only three single-port memory banks","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130379580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1049/iet-cdt:20060205
Chao-Wen Tzeng, Jeffrey Hsu, Shi-Yu Huang
Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm are proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness
{"title":"A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains","authors":"Chao-Wen Tzeng, Jeffrey Hsu, Shi-Yu Huang","doi":"10.1049/iet-cdt:20060205","DOIUrl":"https://doi.org/10.1049/iet-cdt:20060205","url":null,"abstract":"Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm are proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133340108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258169
Hong-Ming Shieh, Chun-Shien Wu, Jin-Fu Li
With the nano-scale technology, a system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VLSI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than the single-code compression schemes. The area cost of the multi-code decompressor is small - only about 3498mum2 based on TSMC 0.18mum standard cell technology
{"title":"A Multi-Code Compression Technique for Reducing System-On-Chip Test Time","authors":"Hong-Ming Shieh, Chun-Shien Wu, Jin-Fu Li","doi":"10.1109/VDAT.2006.258169","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258169","url":null,"abstract":"With the nano-scale technology, a system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VLSI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than the single-code compression schemes. The area cost of the multi-code decompressor is small - only about 3498mum2 based on TSMC 0.18mum standard cell technology","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128542842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258120
S. Lo, K. Das, C. Chuang, J. Sleight
Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving active-mode performance, and reducing virtual supply bounce and standby leakage power is demonstrated
{"title":"Power-Gating Schemes for Ultra-Thin SOI (UTSOI) Circuits in Hybrid SOI-Epitaxial CMOS Structures","authors":"S. Lo, K. Das, C. Chuang, J. Sleight","doi":"10.1109/VDAT.2006.258120","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258120","url":null,"abstract":"Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving active-mode performance, and reducing virtual supply bounce and standby leakage power is demonstrated","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258185
S. Jang, Yun-Hsueh Chuang, Chien-Keng Lee, Shao-Hua Lee
A 4.8GHz low-noise quadrature Colpitts VCO is presented. Use of the current switching differential Colpitts configuration together with super harmonic coupling scheme for quadrature signal generation ensures low phase noise operation. The advantage of proposed differential VCO is analyzed in terms of power consumption, phase noise, and figure of merit. The QVCO has been fabricated with the 0.18-m TSMC CMOS technology for 4.8GHz band operation and the obtained phase noise is -120 dBc/Hz at 1MHz offset frequency while 7mA current consumption and 12.6mW power consumption from 1.8V power supply
提出了一种4.8GHz低噪声正交Colpitts压控振荡器。使用电流开关差分科尔皮茨配置和超谐波耦合方案来产生正交信号，确保低相位噪声运行。从功耗、相位噪声和优值等方面分析了差分压控振荡器的优点。该QVCO采用0.18 m TSMC CMOS工艺制作，工作在4.8GHz频段，在1MHz偏置频率下，相位噪声为-120 dBc/Hz，电流消耗为7mA，功耗为12.6mW，电源为1.8V
{"title":"A 4.8GHz Low-Phase Noise Quadrature Colpitts VCO","authors":"S. Jang, Yun-Hsueh Chuang, Chien-Keng Lee, Shao-Hua Lee","doi":"10.1109/VDAT.2006.258185","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258185","url":null,"abstract":"A 4.8GHz low-noise quadrature Colpitts VCO is presented. Use of the current switching differential Colpitts configuration together with super harmonic coupling scheme for quadrature signal generation ensures low phase noise operation. The advantage of proposed differential VCO is analyzed in terms of power consumption, phase noise, and figure of merit. The QVCO has been fabricated with the 0.18-m TSMC CMOS technology for 4.8GHz band operation and the obtained phase noise is -120 dBc/Hz at 1MHz offset frequency while 7mA current consumption and 12.6mW power consumption from 1.8V power supply","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258170
Po-Kai Chen, Yu-Tsao Hsing, Cheng-Wen Wu
As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers
{"title":"On Feasibility of HOYߞA Wireless Test Methodology for VLSI Chips and Wafers","authors":"Po-Kai Chen, Yu-Tsao Hsing, Cheng-Wen Wu","doi":"10.1109/VDAT.2006.258170","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258170","url":null,"abstract":"As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127547032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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