Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258157
Chao-Chyun Chen, Sheng-chou Lee, Shen-Iuan Liu
This paper presents a fully-integrated spread-spectrum clock generator (SSCG) with triangular modulation. This SSCG with spread ratios of 0.5% and 1% has been fabricated in 0.35mum double-poly quadruple-metal CMOS process. It consumes 140mW at 400MHz output from the supply of 3.3V. The required capacitance is equivalently reduced by a factor of 10 compared with the conventional one
{"title":"A Fully Integrated Spread Spectrum Clock Generator","authors":"Chao-Chyun Chen, Sheng-chou Lee, Shen-Iuan Liu","doi":"10.1109/VDAT.2006.258157","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258157","url":null,"abstract":"This paper presents a fully-integrated spread-spectrum clock generator (SSCG) with triangular modulation. This SSCG with spread ratios of 0.5% and 1% has been fabricated in 0.35mum double-poly quadruple-metal CMOS process. It consumes 140mW at 400MHz output from the supply of 3.3V. The required capacitance is equivalently reduced by a factor of 10 compared with the conventional one","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129307452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258171
Tsu-Ming Liu, Chen-Yi Lee
Memory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. Further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy (To Wei Chen et al., 2005 and Hu et al., 2004)
在H.264/AVC视频解码系统中，内存存储是至关重要的功耗因素。在本文中，我们利用三层内存层次结构来打破数据依赖，减少对外部内存的访问次数。此外，我们采用线像素预估(LPL)方案，在功耗和内存成本之间做出妥协。实验结果证明，与同类解码器相比，在不利用内存层次结构的情况下，可以实现约50%的内存功耗降低(to Wei Chen et al.， 2005和Hu et al.， 2004)。
{"title":"Memory-Hierarchy-Based Power Reduction for H. 264/AVC Video Decoder","authors":"Tsu-Ming Liu, Chen-Yi Lee","doi":"10.1109/VDAT.2006.258171","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258171","url":null,"abstract":"Memory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. Further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy (To Wei Chen et al., 2005 and Hu et al., 2004)","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128679959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258110
Ping-Ying Wang
We prove existence of chaos in phase locked loop (PLL). It is the first time that border-collision bifurcations and chaotic phenomenon in digital charge pump PLL is reported. The numerical result of behavior model is also presented to explain why the chaotic phenomenon exists in PLL. Moreover we highlight that the same chaotic phenomenon will exist in general sample hold feedback circuits
{"title":"Chaos In Phase Locked Loop","authors":"Ping-Ying Wang","doi":"10.1109/VDAT.2006.258110","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258110","url":null,"abstract":"We prove existence of chaos in phase locked loop (PLL). It is the first time that border-collision bifurcations and chaotic phenomenon in digital charge pump PLL is reported. The numerical result of behavior model is also presented to explain why the chaotic phenomenon exists in PLL. Moreover we highlight that the same chaotic phenomenon will exist in general sample hold feedback circuits","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258186
Y. Tsai, T. Horng
A new broadband nine-element single-stage model is developed for the high-Q spiral inductor buried into the organic laminate package substrate. The technique utilizes only one RLC resonator incorporated in modified T equivalent circuit to accurate characterize high-frequency effects such as skin, proximate, and fringing effects, and that led to the model more compact. Parameter extraction of model is used analytical all-mathematical formulations to evaluate frequency-independent elements. This enables the modeling procedure effectively integrated in SPICE-compatible simulators feasible and facile for efficient design of RFIC modules. The proposed model has been verified using embedded inductor in a 4-layer BT laminate, one of today's most popular package substrate. Good agreement between measurements and modeling results over the whole interesting frequency regime has been shown to demonstrate the validity of proposed method
{"title":"Modeling of Hi-Q Embedded Inductors for RF-SOP Applications","authors":"Y. Tsai, T. Horng","doi":"10.1109/VDAT.2006.258186","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258186","url":null,"abstract":"A new broadband nine-element single-stage model is developed for the high-Q spiral inductor buried into the organic laminate package substrate. The technique utilizes only one RLC resonator incorporated in modified T equivalent circuit to accurate characterize high-frequency effects such as skin, proximate, and fringing effects, and that led to the model more compact. Parameter extraction of model is used analytical all-mathematical formulations to evaluate frequency-independent elements. This enables the modeling procedure effectively integrated in SPICE-compatible simulators feasible and facile for efficient design of RFIC modules. The proposed model has been verified using embedded inductor in a 4-layer BT laminate, one of today's most popular package substrate. Good agreement between measurements and modeling results over the whole interesting frequency regime has been shown to demonstrate the validity of proposed method","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114646655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258183
Jia-Liang Chen, T. Chiu, C. Jou
A highly integrated 2.4-GHz class F power amplifier using TSMC 0.35mum 3P3M standard SiGe BiCMOS process is presented. This amplifier integrates both the input matching network and output fundamental and third harmonic loading networks onto the chip. Additional fine tuning output circuit is implemented outside the chip for some flexibility. Measurement results show that the power amplifier can exhibit an output power about 20dBm, with power added efficiency (PAE) of 34.2% at 2.4-GHz Bluetooth frequency band. This result demonstrates the potential of full-scale integration of the high efficiency power amplifier
{"title":"A highly Integrated SiGe BiCMOS Class F Power Amplifier for Bluetooth Application","authors":"Jia-Liang Chen, T. Chiu, C. Jou","doi":"10.1109/VDAT.2006.258183","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258183","url":null,"abstract":"A highly integrated 2.4-GHz class F power amplifier using TSMC 0.35mum 3P3M standard SiGe BiCMOS process is presented. This amplifier integrates both the input matching network and output fundamental and third harmonic loading networks onto the chip. Additional fine tuning output circuit is implemented outside the chip for some flexibility. Measurement results show that the power amplifier can exhibit an output power about 20dBm, with power added efficiency (PAE) of 34.2% at 2.4-GHz Bluetooth frequency band. This result demonstrates the potential of full-scale integration of the high efficiency power amplifier","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258168
Kuan-Chung Wang, Hung-Ming Chen
In SoC era, it is necessary to have a good and efficient large-scale modules placement for better performance estimation in chip implementation or rapid prototyping. Good representation for non-slicing floorplan/placement and ability to solve large-scale modules packing are key components. MB*-tree (Lee et al., 2003) adopted very good and well-known representation B*-tree and modern multilevel framework to handle large-scale modules floorplanning/placement. However the simulated annealing approach in declustering stage paid more time to find candidate solutions with lower cost. In this paper, we transform the epsi-neighborhood and lambda-exchange (Goto, 1981) to fit in the large-scale modules placement and use it in the refinement stage of MB*-tree algorithm. The results are encouraging. We have obtained comparable or better results in area and wirelength metrics in less time spent (up to 30% improvement), compared with original MB*-tree framework
在SoC时代，为了在芯片实现或快速原型设计中更好地进行性能评估，有必要有一个良好而高效的大规模模块放置。良好的非切片平面图/布局表示和解决大规模模块封装的能力是关键组件。MB*-tree (Lee et al.， 2003)采用了非常好的和众所周知的表示B*-tree和现代多层框架来处理大型模块的平面规划/放置。然而，模拟退火方法在聚类阶段花费了更多的时间和更低的成本来寻找候选解。本文将epsi邻域和lambda-exchange (Goto, 1981)转换为适合大规模模块放置的方法，并将其用于MB*-tree算法的细化阶段。结果令人鼓舞。与最初的MB -tree框架相比，我们在更短的时间内获得了相当或更好的面积和波长指标(提高了30%)
{"title":"Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange","authors":"Kuan-Chung Wang, Hung-Ming Chen","doi":"10.1109/VDAT.2006.258168","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258168","url":null,"abstract":"In SoC era, it is necessary to have a good and efficient large-scale modules placement for better performance estimation in chip implementation or rapid prototyping. Good representation for non-slicing floorplan/placement and ability to solve large-scale modules packing are key components. MB*-tree (Lee et al., 2003) adopted very good and well-known representation B*-tree and modern multilevel framework to handle large-scale modules floorplanning/placement. However the simulated annealing approach in declustering stage paid more time to find candidate solutions with lower cost. In this paper, we transform the epsi-neighborhood and lambda-exchange (Goto, 1981) to fit in the large-scale modules placement and use it in the refinement stage of MB*-tree algorithm. The results are encouraging. We have obtained comparable or better results in area and wirelength metrics in less time spent (up to 30% improvement), compared with original MB*-tree framework","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125606487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258150
Chao-Da Huang, Tsu-Wei Tseng, Jin-Fu Li
Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%
{"title":"An Infrastructure IP for Repairing Multiple RAMs in SOCs","authors":"Chao-Da Huang, Tsu-Wei Tseng, Jin-Fu Li","doi":"10.1109/VDAT.2006.258150","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258150","url":null,"abstract":"Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258138
H. Zare-Hoseini, I. Kale
This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques
{"title":"Clock-Jitter Reduction Techniques in Continuous Time Delta-Sigma Modulators","authors":"H. Zare-Hoseini, I. Kale","doi":"10.1109/VDAT.2006.258138","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258138","url":null,"abstract":"This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258133
Y. Jeang, Yong Lin
A field partition based instruction compression/decompression system for ARM series architecture is proposed. Due to a high degree of repetition in the encoding of the specific fields of the instructions in a program, we could get a statistics of the appearances of each field in all instructions of a program. Depending on the statistics, we partition each instruction into three fields and compress each field using Huffman coding method. Experimental results show that our method is better than others with a 55% of average compression ratio. For decompression, single buffering, double buffering and pipeline techniques have been proposed. However, due to jump penalty, these techniques incur more delays in pipeline or have to stop and fill in the cache buffers. We proposed a pipeline with back-up for flushing technique that incurs no delay and without stopping due to jump. The average performance is increased about 10% to 60%
{"title":"An Efficient Field-Partition Based Code Compression and Its Pipelined Decompression System","authors":"Y. Jeang, Yong Lin","doi":"10.1109/VDAT.2006.258133","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258133","url":null,"abstract":"A field partition based instruction compression/decompression system for ARM series architecture is proposed. Due to a high degree of repetition in the encoding of the specific fields of the instructions in a program, we could get a statistics of the appearances of each field in all instructions of a program. Depending on the statistics, we partition each instruction into three fields and compress each field using Huffman coding method. Experimental results show that our method is better than others with a 55% of average compression ratio. For decompression, single buffering, double buffering and pipeline techniques have been proposed. However, due to jump penalty, these techniques incur more delays in pipeline or have to stop and fill in the cache buffers. We proposed a pipeline with back-up for flushing technique that incurs no delay and without stopping due to jump. The average performance is increased about 10% to 60%","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258136
Ying-Min Liao, Tai-Cheng Lee
A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter (DAC) and lowers the accuracy requirement of the capacitor in the conventional successive-approximation (SA)-ADC by the C-2C architecture. Designed in a 0.18-mum technology, the ADC operates at 1.3-Gs/s clock rate while power dissipation is 196 mW. The FFT simulation result shows that the SNDR is 34 dB at 130-MHz input frequency and 1.3-Gs/s conversion rate
提出了一种6-b 1.3 g /s流水线逐次逼近模数转换器(ADC)。该电路采用改进的mms和C-2C架构，具有高速度和低功耗的特点。采用开环结构，可实现高转换率。所提出的架构降低了电荷再分配数模转换器(DAC)的静态功耗，并降低了采用C-2C架构的传统连续逼近(SA)-ADC中电容的精度要求。该ADC采用0.18 μ m技术设计，时钟速率为1.3 g /s，功耗为196 mW。FFT仿真结果表明，在130 mhz输入频率和1.3 g /s转换速率下，SNDR为34 dB
{"title":"A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique","authors":"Ying-Min Liao, Tai-Cheng Lee","doi":"10.1109/VDAT.2006.258136","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258136","url":null,"abstract":"A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter (DAC) and lowers the accuracy requirement of the capacitor in the conventional successive-approximation (SA)-ADC by the C-2C architecture. Designed in a 0.18-mum technology, the ADC operates at 1.3-Gs/s clock rate while power dissipation is 196 mW. The FFT simulation result shows that the SNDR is 34 dB at 130-MHz input frequency and 1.3-Gs/s conversion rate","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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