Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258187
F. Huang, Y. Chan
While the operation frequency of the wireless and the wire-used modern communication systems has being extended to millimeter-wave band, the timing circuits also become important for the low-cost and performance concerns, such as synthesizer or frequency divider. As the millimeter-wave wireless local area network (WLAN) transmitting a digital modulated data upon a carrier frequency through a antenna, is proposed to either obtain a broadcasting service in local area or provide the flexible data access. For the requirement of synchronization, hence the high speed and high frequency dividers/prescalars up to 60 GHz may be employed in phase-locked loop (PLL). Moreover, the power consumption and the low noise features in the divider circuits are also the major concerns. Conventional common-mode logic (CML) dividers are difficult to push the maximum operation frequency to over the microwave range due to its limitation by the cut-off frequency fT, regardless it reaches a wide dividing range. Extreme high power consumption is also the disadvantage for CML approach. Thus to fulfil the low power dissipation dividers, the LC-type injection-locked frequency dividers (ILFD) have been proposed and being used in PLL or clock-data recovery (CDR) circuits as stated in H. R. Rategh et al. (1999). The CMOS submicron techniques have been progressed to a proper high frequency divider design. In this work, there are two 60 GHz ILFDs have been realized by using the CMOS 0.18mum 1P6M technology, in which contain the self-oscillation frequencies of 30 GHz and 15 GHz respectively for a divided-by 2 or 4 operation. Both ILFDs demonstrate the improved locking ranges using a self-oscillation frequency tuning and a 0/180deg single-to-differential power divider with low dc power consumptions
当无线和有线现代通信系统的工作频率已扩展到毫米波波段时，定时电路也成为低成本和性能方面的重要考虑，如合成器或分频器。毫米波无线局域网(WLAN)是一种通过天线在载波频率上传输数字调制数据的无线局域网，它既可以在本地获得广播业务，也可以提供灵活的数据访问。为了满足同步的要求，锁相环(PLL)中可以采用高达60 GHz的高速高频分频/预标量。此外，分频电路的功耗和低噪声特性也是主要关注的问题。传统的共模逻辑(CML)分频器尽管具有较宽的分频范围，但由于其截止频率fT的限制，很难将最大工作频率推到微波范围以上。极高的功耗也是CML方法的缺点。因此，为了实现低功耗分频器，已经提出了lc型注入锁定分频器(ILFD)，并在锁相环或时钟数据恢复(CDR)电路中使用，如H. R. Rategh等人(1999)所述。CMOS亚微米技术已经发展到合适的高频分频器设计。本文采用CMOS 0.18mum 1P6M技术实现了两个60 GHz的ilfd，其自振荡频率分别为30 GHz和15 GHz，可用于除2或除4运算。这两款ilfd都采用了自振荡频率调谐和0/180度单对差分功率分压器，具有较低的直流功耗，从而展示了改进的锁定范围
{"title":"V-Band CMOS Differential-type Injection Locked Frequency Dividers","authors":"F. Huang, Y. Chan","doi":"10.1109/VDAT.2006.258187","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258187","url":null,"abstract":"While the operation frequency of the wireless and the wire-used modern communication systems has being extended to millimeter-wave band, the timing circuits also become important for the low-cost and performance concerns, such as synthesizer or frequency divider. As the millimeter-wave wireless local area network (WLAN) transmitting a digital modulated data upon a carrier frequency through a antenna, is proposed to either obtain a broadcasting service in local area or provide the flexible data access. For the requirement of synchronization, hence the high speed and high frequency dividers/prescalars up to 60 GHz may be employed in phase-locked loop (PLL). Moreover, the power consumption and the low noise features in the divider circuits are also the major concerns. Conventional common-mode logic (CML) dividers are difficult to push the maximum operation frequency to over the microwave range due to its limitation by the cut-off frequency fT, regardless it reaches a wide dividing range. Extreme high power consumption is also the disadvantage for CML approach. Thus to fulfil the low power dissipation dividers, the LC-type injection-locked frequency dividers (ILFD) have been proposed and being used in PLL or clock-data recovery (CDR) circuits as stated in H. R. Rategh et al. (1999). The CMOS submicron techniques have been progressed to a proper high frequency divider design. In this work, there are two 60 GHz ILFDs have been realized by using the CMOS 0.18mum 1P6M technology, in which contain the self-oscillation frequencies of 30 GHz and 15 GHz respectively for a divided-by 2 or 4 operation. Both ILFDs demonstrate the improved locking ranges using a self-oscillation frequency tuning and a 0/180deg single-to-differential power divider with low dc power consumptions","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125426560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258174
D. Howard, K. Shi
Various current control techniques are described to limit current surge when sleep transistor are turned on to power a design. Advantages and disadvantages in the techniques are also discussed. The trade-off consideration on power-on latency adds more challenges in the current control in sleep transistor implementations which is addressed in the paper
{"title":"Power-On Current Control In Sleep Transistor Implementations","authors":"D. Howard, K. Shi","doi":"10.1109/VDAT.2006.258174","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258174","url":null,"abstract":"Various current control techniques are described to limit current surge when sleep transistor are turned on to power a design. Advantages and disadvantages in the techniques are also discussed. The trade-off consideration on power-on latency adds more challenges in the current control in sleep transistor implementations which is addressed in the paper","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258148
S.D. Wu, C. Tsai, M. Yang
This paper describes a novel graph fixing algorithm which can be used to fix the design constraint violations for a VLSI layout. Layouts are designed so that the process design rule and user specified constraints must be satisfied. Custom layout methodologies and process design rule migration activities introduce rule and constraint violations in layouts. Traditionally, layout compaction technique based on minimal area criterion is used to solve layout constraint violation problem. Unfortunately such layout compaction technique often fail in real designs since the layout often changed significantly and resulted in circuit performance degeneracy after layout compaction. Recently, a minimum layout perturbation was proposed to overcome the aforementioned drawback. The layout legalization was formulated as a linear programming problem which objective function was the summation of the perturbation of shapes. Such works reduced the impact on circuit performance greatly. In this paper, based on the concept of minimum layout perturbation, a more efficient graph fixing algorithm is proposed to solve layout legalization problem. This algorithm has been implemented as a part of Lakertrade AutoCorrect function and demonstrated the efficiency and feasibility for several real designs
{"title":"A VLSI Layout Legalization Technique Based on a Graph Fixing Algorithm","authors":"S.D. Wu, C. Tsai, M. Yang","doi":"10.1109/VDAT.2006.258148","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258148","url":null,"abstract":"This paper describes a novel graph fixing algorithm which can be used to fix the design constraint violations for a VLSI layout. Layouts are designed so that the process design rule and user specified constraints must be satisfied. Custom layout methodologies and process design rule migration activities introduce rule and constraint violations in layouts. Traditionally, layout compaction technique based on minimal area criterion is used to solve layout constraint violation problem. Unfortunately such layout compaction technique often fail in real designs since the layout often changed significantly and resulted in circuit performance degeneracy after layout compaction. Recently, a minimum layout perturbation was proposed to overcome the aforementioned drawback. The layout legalization was formulated as a linear programming problem which objective function was the summation of the perturbation of shapes. Such works reduced the impact on circuit performance greatly. In this paper, based on the concept of minimum layout perturbation, a more efficient graph fixing algorithm is proposed to solve layout legalization problem. This algorithm has been implemented as a part of Lakertrade AutoCorrect function and demonstrated the efficiency and feasibility for several real designs","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114627121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258144
A. Eltawil, F. Kurdahi
This paper addresses the fact that memory yield is the dominant issue affecting overall yield in nano-scale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics
{"title":"System Redundancy; A Means of Improving Process Variation Yield Degradation in Memory Arrays","authors":"A. Eltawil, F. Kurdahi","doi":"10.1109/VDAT.2006.258144","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258144","url":null,"abstract":"This paper addresses the fact that memory yield is the dominant issue affecting overall yield in nano-scale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258172
Tsung-Hsueh Lee, Jing-Siang Jhuang, T. Chiueh
In this paper, we have completed system and circuit design of a high-speed baseband transceiver for a high-rate wireless LAN. This system adopts multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) technique, which can be more robust to channel effects in the band that the WLAN will operate. Detail design of the baseband receiver is completed and functional simulation shows promising results for the proposed baseband transceiver. Further circuit design indicates that the receiver can support a signal bandwidth higher than 150MHz and channel bit rate well above 1Gbps
{"title":"A High-Speed Baseband Receiver for MIMO OFDM Based WLAN","authors":"Tsung-Hsueh Lee, Jing-Siang Jhuang, T. Chiueh","doi":"10.1109/VDAT.2006.258172","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258172","url":null,"abstract":"In this paper, we have completed system and circuit design of a high-speed baseband transceiver for a high-rate wireless LAN. This system adopts multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) technique, which can be more robust to channel effects in the band that the WLAN will operate. Detail design of the baseband receiver is completed and functional simulation shows promising results for the proposed baseband transceiver. Further circuit design indicates that the receiver can support a signal bandwidth higher than 150MHz and channel bit rate well above 1Gbps","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133301446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258182
Wen-Yaw Chung, Yu-Chien Tseng, Yu-Wen Chen, Chih-Jen Yen
This article proposes a column driver circuit design for a passive organic electro-luminescent display (PMOELD). A new method for grayscale driving has been developed for providing better visual effect. Besides, a novel programmable current-mode data driver circuit with calibration techniques is used to overcome process and environmental variations, especially there is column current mismatch due to the different distance to a bias reference. The proposed circuit has been designed and verified by using VIS 0.35mum, 2P4M and 13.5V high voltage process. The brightness current has been emphasized to simulate the performance of the variations elimination between different column circuits. By using the Monte Carlo simulation, the result of the current variation in different column is under 2% when the standard deviation of threshold voltage is 0.18V
{"title":"The Column Driver Circuit Design for Passive Organic Electroluminescence Display","authors":"Wen-Yaw Chung, Yu-Chien Tseng, Yu-Wen Chen, Chih-Jen Yen","doi":"10.1109/VDAT.2006.258182","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258182","url":null,"abstract":"This article proposes a column driver circuit design for a passive organic electro-luminescent display (PMOELD). A new method for grayscale driving has been developed for providing better visual effect. Besides, a novel programmable current-mode data driver circuit with calibration techniques is used to overcome process and environmental variations, especially there is column current mismatch due to the different distance to a bias reference. The proposed circuit has been designed and verified by using VIS 0.35mum, 2P4M and 13.5V high voltage process. The brightness current has been emphasized to simulate the performance of the variations elimination between different column circuits. By using the Monte Carlo simulation, the result of the current variation in different column is under 2% when the standard deviation of threshold voltage is 0.18V","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129339460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a prototype of the COFDM demodulator conforming to the European DVB-T standard. The proposed prototype mainly contains four blocks: time synchronization, frequency synchronization, 2K/8K FFT processor, and channel estimation. Each block is implemented by the relatively simple algorithm to avoid the overhead of hardware complexity. TSMC 0.18 mum CMOS technology is adopted to carry out the proposed COFDM demodulator. The proposed prototype uses 637 Kbits of SRAM and occupies a total area of 17.2 mm2
{"title":"A 0.18 μm CMOS Prototype of COFDM Demodulator for European DVB-T Standard","authors":"Chua-Chin Wang, Jian-Ming Huang, Yung-Mu Tseng, Chih-Yi Chang","doi":"10.1109/VDAT.2006.258126","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258126","url":null,"abstract":"This paper presents a prototype of the COFDM demodulator conforming to the European DVB-T standard. The proposed prototype mainly contains four blocks: time synchronization, frequency synchronization, 2K/8K FFT processor, and channel estimation. Each block is implemented by the relatively simple algorithm to avoid the overhead of hardware complexity. TSMC 0.18 mum CMOS technology is adopted to carry out the proposed COFDM demodulator. The proposed prototype uses 637 Kbits of SRAM and occupies a total area of 17.2 mm2","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122097203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258139
P. Chou
Real-world wireless sensing applications pose a number of great challenges on low-power hardware/software platform designs, including a wide range of size, cost, power consumption, connectivity, performance, and flexibility requirements. Based on a classification of sensing functions, detection methods, timeliness of data, and characteristics of power supply, the platform may need to incorporate different features in order to operate in a low-power, energy-efficient manner. The design issues are highlighted in the context of a number of sensing systems ranging from high-performance, high-precision data acquisition wireless sensor node for civil engineering and an ultra-compact wireless sensor node for infant monitoring to a laser-based breast cancer detector
{"title":"Challenges on Low-Power Platform Design for Real-World Wireless Sensing Applications","authors":"P. Chou","doi":"10.1109/VDAT.2006.258139","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258139","url":null,"abstract":"Real-world wireless sensing applications pose a number of great challenges on low-power hardware/software platform designs, including a wide range of size, cost, power consumption, connectivity, performance, and flexibility requirements. Based on a classification of sensing functions, detection methods, timeliness of data, and characteristics of power supply, the platform may need to incorporate different features in order to operate in a low-power, energy-efficient manner. The design issues are highlighted in the context of a number of sensing systems ranging from high-performance, high-precision data acquisition wireless sensor node for civil engineering and an ultra-compact wireless sensor node for infant monitoring to a laser-based breast cancer detector","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115660199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258122
O. Goren, Y. Netanel
As VLSI technology continuously scales and market requirements from embedded SoC rapidly change, there is a growing need for on-chip interconnect that fits high performance multiprocessor systems and allows fast SoC generation to reduce time to market. Historically, most of the on-chip interconnects were based on a shared bus architecture, connecting a plurality of masters and a plurality of slaves. This approach becomes obsolete as technology performance increases, due to limited scalability and huge circuit design effort involved. On the other hand, the approach, which proposes non-ordered packet-based interconnect (network on a chip) cannot fulfil the need for latency-sensitive on-chip interconnect and implies complex design and verification. Focusing on high performance multiprocessors systems, addressing the need for fast SoC generation and keeping design and verification efficient, the chip level arbitration and switching system (CLASS), designed by Freescale Semiconductor, proposes a complete on-chip interconnect system which addresses the challenges in today's SoC architectures
{"title":"High performance on-chip interconnect system supporting fast SoC generation","authors":"O. Goren, Y. Netanel","doi":"10.1109/VDAT.2006.258122","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258122","url":null,"abstract":"As VLSI technology continuously scales and market requirements from embedded SoC rapidly change, there is a growing need for on-chip interconnect that fits high performance multiprocessor systems and allows fast SoC generation to reduce time to market. Historically, most of the on-chip interconnects were based on a shared bus architecture, connecting a plurality of masters and a plurality of slaves. This approach becomes obsolete as technology performance increases, due to limited scalability and huge circuit design effort involved. On the other hand, the approach, which proposes non-ordered packet-based interconnect (network on a chip) cannot fulfil the need for latency-sensitive on-chip interconnect and implies complex design and verification. Focusing on high performance multiprocessors systems, addressing the need for fast SoC generation and keeping design and verification efficient, the chip level arbitration and switching system (CLASS), designed by Freescale Semiconductor, proposes a complete on-chip interconnect system which addresses the challenges in today's SoC architectures","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258109
D. Quoc-Dang Ho, Chin Chang, J. Rathore, L. D'Souza, Yuwen Swei, Kuan-Dar Chen, Jyhfong Lin
A 2.7V fully-integrated voice-band codec for digital cellular phone applications is presented. The codec includes a 16b ΣΔ ADC and DAC, channel filters, PGAs, a low-noise microphone preamplifier and 32 Ω loudspeaker/earpiece drivers. With a PLL for clock generation and a voltage reference integrated on the same chip, the ADC achieves an SNDR of 83 dB and a dynamic range of 88 dB in a 4 KHz signal bandwidth, while the DAC yields 80 dB and 84 dB, respectively. Analog and digital portions of the codec consume only 4.8 mA and 0.53 mA, respectively, and occupy a combined area of 1.0 mm2 in a 0.18-μm CMOS technology
{"title":"A Low-Power and Compact Sigma-Delta Voice-band Codec in a 0.18-μm CMOS Technology","authors":"D. Quoc-Dang Ho, Chin Chang, J. Rathore, L. D'Souza, Yuwen Swei, Kuan-Dar Chen, Jyhfong Lin","doi":"10.1109/VDAT.2006.258109","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258109","url":null,"abstract":"A 2.7V fully-integrated voice-band codec for digital cellular phone applications is presented. The codec includes a 16b ΣΔ ADC and DAC, channel filters, PGAs, a low-noise microphone preamplifier and 32 Ω loudspeaker/earpiece drivers. With a PLL for clock generation and a voltage reference integrated on the same chip, the ADC achieves an SNDR of 83 dB and a dynamic range of 88 dB in a 4 KHz signal bandwidth, while the DAC yields 80 dB and 84 dB, respectively. Analog and digital portions of the codec consume only 4.8 mA and 0.53 mA, respectively, and occupy a combined area of 1.0 mm2 in a 0.18-μm CMOS technology","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114572567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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