Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258132
Chi-Chia Sun, B. Heyne, S. Ruan, Juergen Goetze
In this paper, a low-power and high-quality preserving DCT architecture is presented. It is obtained by optimizing the Loeffler DCT based on the Cordic algorithm. The experimental results show that the proposed DCT architecture occupies 19% of the area and consumes about 16% of the power compared to the original Loeffler DCT. Additionally the good transformation quality is retained. In this regard, the proposed Cordic based Loeffler DCT is very suitable for low-power and high-quality CODECs, especially for battery-based systems
{"title":"A Low-Power and High-Quality Cordic Based Loeffler DCT","authors":"Chi-Chia Sun, B. Heyne, S. Ruan, Juergen Goetze","doi":"10.1109/VDAT.2006.258132","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258132","url":null,"abstract":"In this paper, a low-power and high-quality preserving DCT architecture is presented. It is obtained by optimizing the Loeffler DCT based on the Cordic algorithm. The experimental results show that the proposed DCT architecture occupies 19% of the area and consumes about 16% of the power compared to the original Loeffler DCT. Additionally the good transformation quality is retained. In this regard, the proposed Cordic based Loeffler DCT is very suitable for low-power and high-quality CODECs, especially for battery-based systems","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128928455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258140
A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr
Increasing complexity of cutting-edge applications for future embedded systems demand even higher processor performance with a strong consideration for battery-life. Low power optimization techniques are, therefore, widely applied towards the development of modern application specific instruction-set processors (ASIPs). Architecture description languages (ADLs) offer the ASIP designers a quick and optimal design convergence by automatically generating the software tool-suite as well as the register transfer level (RTL) description of the processor. The automatically generated processor description is then subjected to the traditional RTL-based synthesis flow. Power-specific optimizations, often found in RTL-based commercial tools, cannot take the full advantage of the architectural knowledge embedded in the ADL description, resulting in sub-optimal power efficiency. In this paper, we address this issue by describing an efficient and universal technique of automatic insertion of gated clocks during the ADL-based ASIP design flow. Experiments with ASIP benchmarks show the dramatic impact of our approach by reducing power consumption up to 41% percent compared to naive RTL synthesis from ADL description, without any incurred overhead for area and speed
{"title":"Automatic Low Power Optimizations during ADL-driven ASIP Design","authors":"A. Chattopadhyay, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr","doi":"10.1109/VDAT.2006.258140","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258140","url":null,"abstract":"Increasing complexity of cutting-edge applications for future embedded systems demand even higher processor performance with a strong consideration for battery-life. Low power optimization techniques are, therefore, widely applied towards the development of modern application specific instruction-set processors (ASIPs). Architecture description languages (ADLs) offer the ASIP designers a quick and optimal design convergence by automatically generating the software tool-suite as well as the register transfer level (RTL) description of the processor. The automatically generated processor description is then subjected to the traditional RTL-based synthesis flow. Power-specific optimizations, often found in RTL-based commercial tools, cannot take the full advantage of the architectural knowledge embedded in the ADL description, resulting in sub-optimal power efficiency. In this paper, we address this issue by describing an efficient and universal technique of automatic insertion of gated clocks during the ADL-based ASIP design flow. Experiments with ASIP benchmarks show the dramatic impact of our approach by reducing power consumption up to 41% percent compared to naive RTL synthesis from ADL description, without any incurred overhead for area and speed","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258160
J. Huang, Chih-Hsien Lin, S. Jou
In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13mum 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz
{"title":"Adaptive Quadrature Clock Generator","authors":"J. Huang, Chih-Hsien Lin, S. Jou","doi":"10.1109/VDAT.2006.258160","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258160","url":null,"abstract":"In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13mum 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258164
J. Lu, Chi-Lun Luo, Shen-Iuan Liu
In this paper, an adaptive 3.125Gbps coaxial cable equalizer is realized in a 0.18-mum CMOS technology. For the length of 15m and 20m Belden 8219 cables, the signal attenuation are -12dB and -16dB, respectively, at 1.5625GHz. Due to the signal attenuation after passing through the coaxial cable, this adaptive 3.125Gbps coaxial cable equalizer compensates the broadband loss to be adaptive to different length of the cables. The core circuit excluding output buffers dissipates only 14.8mW from a 1.8V supply with output swing up to 400mV p-p. The core circuit occupies 0.5times0.63mm2 and the measured timing jitter for a cable of 20m is less than 0.25UI
本文采用0.18 μ m CMOS技术实现了一种自适应3.125Gbps同轴电缆均衡器。对于长度为15m和20m的Belden 8219电缆，在1.5625GHz处信号衰减分别为-12dB和-16dB。由于信号经过同轴电缆后会衰减，该自适应3.125Gbps同轴电缆均衡器补偿了宽带损耗，可以适应不同长度的电缆。不包括输出缓冲器的核心电路仅从输出摆幅高达400mV p-p的1.8V电源中耗散14.8mW。芯电路占用0.5 × 0.63mm2，测量20m电缆的定时抖动小于0.25UI
{"title":"An Adaptive 3.125Gbps Coaxial Cable Equalizer","authors":"J. Lu, Chi-Lun Luo, Shen-Iuan Liu","doi":"10.1109/VDAT.2006.258164","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258164","url":null,"abstract":"In this paper, an adaptive 3.125Gbps coaxial cable equalizer is realized in a 0.18-mum CMOS technology. For the length of 15m and 20m Belden 8219 cables, the signal attenuation are -12dB and -16dB, respectively, at 1.5625GHz. Due to the signal attenuation after passing through the coaxial cable, this adaptive 3.125Gbps coaxial cable equalizer compensates the broadband loss to be adaptive to different length of the cables. The core circuit excluding output buffers dissipates only 14.8mW from a 1.8V supply with output swing up to 400mV p-p. The core circuit occupies 0.5times0.63mm2 and the measured timing jitter for a cable of 20m is less than 0.25UI","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"37 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121693483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258141
Hung Hsie Lee, S. H. Tsai, J. Chi, Mely Chen Chi
We proposed an effective voltage scaling technique to assign the supply voltage to gates in the circuit of dual power supplies. The algorithm is composed of a greedy voltage assignment phase and an iterative voltage re-assignment refinement phase. It reduces the total power without performance degradation. We apply the algorithm to several test cases. It shows that on average the total power saved is 54.7%. Compared to the GECVS technique (Kulkami, 2004), our algorithm reduces the number of level converters by 23.2% and the power consumption by 5.5%. The experimental result also shows the distribution of slack in the original and the power optimized designs. It shows that majority slacks of the gates are reduced. The algorithm utilizes the slack of gates to scale down the supply voltage of the gates such that the power consumption is reduced
{"title":"A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs","authors":"Hung Hsie Lee, S. H. Tsai, J. Chi, Mely Chen Chi","doi":"10.1109/VDAT.2006.258141","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258141","url":null,"abstract":"We proposed an effective voltage scaling technique to assign the supply voltage to gates in the circuit of dual power supplies. The algorithm is composed of a greedy voltage assignment phase and an iterative voltage re-assignment refinement phase. It reduces the total power without performance degradation. We apply the algorithm to several test cases. It shows that on average the total power saved is 54.7%. Compared to the GECVS technique (Kulkami, 2004), our algorithm reduces the number of level converters by 23.2% and the power consumption by 5.5%. The experimental result also shows the distribution of slack in the original and the power optimized designs. It shows that majority slacks of the gates are reduced. The algorithm utilizes the slack of gates to scale down the supply voltage of the gates such that the power consumption is reduced","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258117
Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu
We report a 5.4 mW ultra low dc power low noise amplifier (LNA) at 5.5 GHz, which is based on a 0.35-mum BiCMOS technology. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the usage of the HBT-cascade-MOS methodology is simultaneously satisfied the tradeoff between noise figure (NF) and linearity of LNA. This amplifier achieves a gain/(NF times PDC ) ratio figure of merit of 0.774 (1/mW) which is the better reported at 5~6-GHz band and suitable for wireless LAN applications
{"title":"Design Trade-offs for Low-power and High Figure-of-merit LNA","authors":"Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu","doi":"10.1109/VDAT.2006.258117","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258117","url":null,"abstract":"We report a 5.4 mW ultra low dc power low noise amplifier (LNA) at 5.5 GHz, which is based on a 0.35-mum BiCMOS technology. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the usage of the HBT-cascade-MOS methodology is simultaneously satisfied the tradeoff between noise figure (NF) and linearity of LNA. This amplifier achieves a gain/(NF times PDC ) ratio figure of merit of 0.774 (1/mW) which is the better reported at 5~6-GHz band and suitable for wireless LAN applications","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258146
Chia-Yi Chang, Hung-Ming Chen
Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration
{"title":"Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization","authors":"Chia-Yi Chang, Hung-Ming Chen","doi":"10.1109/VDAT.2006.258146","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258146","url":null,"abstract":"Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258118
T. Fukuda, S. Hayakawa, N. Shigyo
Alpha and neutron SERs of embedded-SRAMs are evaluated. From the results for several technology generations, SER is expressed as a function of diffusion area and critical charge for devices, but the effect of collection efficiency is constant for the generations. Then, the technology independent SER model named universal curve is introduced. Moreover, SER trend to 45nm generation is quantitatively estimated based on the future trend of device technology
{"title":"Alpha and Neutron SER of embedded-SRAM and Novel Estimation Method","authors":"T. Fukuda, S. Hayakawa, N. Shigyo","doi":"10.1109/VDAT.2006.258118","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258118","url":null,"abstract":"Alpha and neutron SERs of embedded-SRAMs are evaluated. From the results for several technology generations, SER is expressed as a function of diffusion area and critical charge for devices, but the effect of collection efficiency is constant for the generations. Then, the technology independent SER model named universal curve is introduced. Moreover, SER trend to 45nm generation is quantitatively estimated based on the future trend of device technology","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114833470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258184
Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu
In this paper, the design and application of an on-chip transformer balun for RFIC has presented. Single-ended primary and differential secondary are constructed without using three individual windings for simple layout. Besides, this new topology has the same physical common visual ground point for second winding, which eliminates imbalance due to potential difference at the ground from conventional trifilar. Furthermore, this new on-chip balun is successfully applied to the integration of 5.8-GHz LNA-mixer implemented on SiGe 0.35-mum BiCMOS process then achieves 4.15-dB noise figure (NF), 34.61-dB conversion gain, and -9.5-dBm input third-order intercept-point with low power consumption of 9-mW
{"title":"A Merged LNA-Mixer Design with On-Chip Balun","authors":"Hsien-Ku Chen, J. Sha, D. Chang, Y. Juang, Chin-Fong Chiu","doi":"10.1109/VDAT.2006.258184","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258184","url":null,"abstract":"In this paper, the design and application of an on-chip transformer balun for RFIC has presented. Single-ended primary and differential secondary are constructed without using three individual windings for simple layout. Besides, this new topology has the same physical common visual ground point for second winding, which eliminates imbalance due to potential difference at the ground from conventional trifilar. Furthermore, this new on-chip balun is successfully applied to the integration of 5.8-GHz LNA-mixer implemented on SiGe 0.35-mum BiCMOS process then achieves 4.15-dB noise figure (NF), 34.61-dB conversion gain, and -9.5-dBm input third-order intercept-point with low power consumption of 9-mW","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"413 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123506696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258163
Chung-Wei Lin, Yen-Jen Liu
In this paper a low drop out regulator (LDO) is proposed, which can adaptively change driving current to the PMOS gate and have a fast transient response time. As we know, LDO circuits have to provide a regulated output voltage regardless of input voltage variation, load current variation, and process variation. A load transient test will test the transient behavior of changing output loading. In order to get a good performance in a load transient testing, a buffer with current driving capability is usually added in front of PMOS gate to make the transient response faster. This buffer needs to drive the PMOS gate, and it will consume a few quiescent current in LDO circuits. This static quiescent current will occupy a few percentage of power consumption of LDO circuits at a light load condition, and the efficiency of the LDO at a light load condition will be very poor. In this paper, we proposed a new architecture of LDO, which can adaptively change the driving current of the buffer to the PMOS gate. Then we can improve the efficiency of the LDO up to 10% at light load condition. Meanwhile, we can have a fast transient response time. The load transient response time from 1mA to 138mA is about 2mus, which is faster than other reference designs. This chip is manufactured in 0.35mum standard CMOS process, and it consumes 24muA in a light load condition
{"title":"A Power Efficient and Fast Transient Response Low Drop-Out Regulator in Standard CMOS Process","authors":"Chung-Wei Lin, Yen-Jen Liu","doi":"10.1109/VDAT.2006.258163","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258163","url":null,"abstract":"In this paper a low drop out regulator (LDO) is proposed, which can adaptively change driving current to the PMOS gate and have a fast transient response time. As we know, LDO circuits have to provide a regulated output voltage regardless of input voltage variation, load current variation, and process variation. A load transient test will test the transient behavior of changing output loading. In order to get a good performance in a load transient testing, a buffer with current driving capability is usually added in front of PMOS gate to make the transient response faster. This buffer needs to drive the PMOS gate, and it will consume a few quiescent current in LDO circuits. This static quiescent current will occupy a few percentage of power consumption of LDO circuits at a light load condition, and the efficiency of the LDO at a light load condition will be very poor. In this paper, we proposed a new architecture of LDO, which can adaptively change the driving current of the buffer to the PMOS gate. Then we can improve the efficiency of the LDO up to 10% at light load condition. Meanwhile, we can have a fast transient response time. The load transient response time from 1mA to 138mA is about 2mus, which is faster than other reference designs. This chip is manufactured in 0.35mum standard CMOS process, and it consumes 24muA in a light load condition","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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