Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258180
J. Doutreloigne
A complete ultra-low-power high-voltage driver for 80 times 104 passive-matrix bistable LCD is integrated in a 0.7mum CMOS smart-power technology. It features 100V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3V battery. An original level-shifter design for the high-voltage multiplexers yields extremely low internal power consumption below 1-10mW for the entire driver chip
一个完整的超低功耗高压驱动器80 × 104无源矩阵双稳态LCD集成在一个0.7 μ m CMOS智能功率技术。它在所有行和列输出上具有100V驱动能力，包括所有必要的数字可编程高压发生器和多路复用器，以合成所需的复杂高压波形，来自3V电池。用于高压多路复用器的原始电平移相器设计使整个驱动芯片的内部功耗极低，低于1-10mW
{"title":"A Fully Integrated Ultra-Low-Power High-Voltage Driver for Bistable LCDs","authors":"J. Doutreloigne","doi":"10.1109/VDAT.2006.258180","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258180","url":null,"abstract":"A complete ultra-low-power high-voltage driver for 80 times 104 passive-matrix bistable LCD is integrated in a 0.7mum CMOS smart-power technology. It features 100V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3V battery. An original level-shifter design for the high-voltage multiplexers yields extremely low internal power consumption below 1-10mW for the entire driver chip","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133362257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258135
D. Muthers, R. Tielert
A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation
{"title":"A 75MS/s Low Power Pipeline ADC with scalable Resolution","authors":"D. Muthers, R. Tielert","doi":"10.1109/VDAT.2006.258135","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258135","url":null,"abstract":"A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128985930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258142
Y. Nakamura
System-on-a-chip (SoC) refers to a system designed by integrating IP (intellectual property) cores such as CPUs, DSPs, and various types of function. Recently, since a complex SoC has more than 10 CPU cores, the software development term of such complex SoCs is longer than the hardware development term of them. Thus, a fast, low cost and accurate simulator for the embedded software for SoC, is needed. In this paper we described a new hardware/software co-verification method for system-on-a-chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, keeping the clock synchronization, and high verification speed, at a low cost. We applied this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development In these projects, our verification methodology was used to perform complete system verification at 0.2-2.5 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break". These results indicate that the proposed environment has the adequate performance as the simulator for the embedded software development for SoC
{"title":"Software Verification for System on a Chip using a C/C++ Simulator and FPGA Emulator","authors":"Y. Nakamura","doi":"10.1109/VDAT.2006.258142","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258142","url":null,"abstract":"System-on-a-chip (SoC) refers to a system designed by integrating IP (intellectual property) cores such as CPUs, DSPs, and various types of function. Recently, since a complex SoC has more than 10 CPU cores, the software development term of such complex SoCs is longer than the hardware development term of them. Thus, a fast, low cost and accurate simulator for the embedded software for SoC, is needed. In this paper we described a new hardware/software co-verification method for system-on-a-chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, keeping the clock synchronization, and high verification speed, at a low cost. We applied this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development In these projects, our verification methodology was used to perform complete system verification at 0.2-2.5 MHz, while supporting full graphical interface functions such as \"waveform\" or \"signal dump\" viewers, and debugging functions such as \"step\" or \"break\". These results indicate that the proposed environment has the adequate performance as the simulator for the embedded software development for SoC","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133416793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258112
Jih-Nung Lee, Ta-Chia Yeh, Chi-Feng Wu, Shih-Arn Hwang, Chao-Cheng Lee
As semiconductor process technologies keep improving, more and more high frequency chips will be designed and manufactured. Testing of timing-related defects thus is becoming essential to guarantee high quality deep sub-micron products. In this paper, we presented our experiences in scan-based at-speed delay testing. Based on transition delay and path delay fault model, we enhance the traditional production test flow with scan-based at-speed delay tests. To test chips at operational speed, we designed an on-chip test clock generator to generate at-speed launch-capture clock pulses. Therefore, high-speed testers will not be required. Commercial EDA tools are used for test pattern generation and timing analysis. In addition, stress test flow is proposed to enhance the test quality. Experimental results show that our approach can detect delay defects, which can be correlated with results of at-speed functional tests
{"title":"Experiences In Deep Sub-Micron Scan-Based At-Speed Delay Testing","authors":"Jih-Nung Lee, Ta-Chia Yeh, Chi-Feng Wu, Shih-Arn Hwang, Chao-Cheng Lee","doi":"10.1109/VDAT.2006.258112","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258112","url":null,"abstract":"As semiconductor process technologies keep improving, more and more high frequency chips will be designed and manufactured. Testing of timing-related defects thus is becoming essential to guarantee high quality deep sub-micron products. In this paper, we presented our experiences in scan-based at-speed delay testing. Based on transition delay and path delay fault model, we enhance the traditional production test flow with scan-based at-speed delay tests. To test chips at operational speed, we designed an on-chip test clock generator to generate at-speed launch-capture clock pulses. Therefore, high-speed testers will not be required. Commercial EDA tools are used for test pattern generation and timing analysis. In addition, stress test flow is proposed to enhance the test quality. Experimental results show that our approach can detect delay defects, which can be correlated with results of at-speed functional tests","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258166
Chin-Hsing Chen, W. Huang, Chun-Ta Chen, Rong-Shue Hsiao
JFFS2 (Journaling Flash File System, version 2) is a popular file system of Linux platform that is employed to manage NAND type flash memory, briefly denoted by NandFlash. Based on JFFS2 mechanism, we propose an effective management method of NandFlash, new flash file system for NandFlash called NFFSNand. Our method focuses on reducing the cycle-leveling degree in a balanced manner. Moreover, NFFSNand can enhance the system performance and prolongs life-cycle of NandFlash. In this study, we verify the system cost, the reliability, and space utilization of NFFSNand are better than JFFS2 by 50% at Samsung SMDK2410X platform
JFFS2 (Journaling Flash File System, version 2)是Linux平台上一种流行的文件系统，用于管理NAND型闪存，简称NandFlash。基于JFFS2机制，提出了一种有效的NandFlash管理方法，即NandFlash的新型flash文件系统NFFSNand。我们的方法侧重于以平衡的方式降低循环均衡度。此外，NFFSNand可以提高系统性能，延长NandFlash的生命周期。在本研究中，我们在三星SMDK2410X平台上验证了NFFSNand的系统成本、可靠性和空间利用率比JFFS2好50%
{"title":"Improving the Reliability of JFFS2","authors":"Chin-Hsing Chen, W. Huang, Chun-Ta Chen, Rong-Shue Hsiao","doi":"10.1109/VDAT.2006.258166","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258166","url":null,"abstract":"JFFS2 (Journaling Flash File System, version 2) is a popular file system of Linux platform that is employed to manage NAND type flash memory, briefly denoted by NandFlash. Based on JFFS2 mechanism, we propose an effective management method of NandFlash, new flash file system for NandFlash called NFFSNand. Our method focuses on reducing the cycle-leveling degree in a balanced manner. Moreover, NFFSNand can enhance the system performance and prolongs life-cycle of NandFlash. In this study, we verify the system cost, the reliability, and space utilization of NFFSNand are better than JFFS2 by 50% at Samsung SMDK2410X platform","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116346525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/DDECS.2007.4295246
D. Gajski
With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure
{"title":"New Strategies for System Level Design","authors":"D. Gajski","doi":"10.1109/DDECS.2007.4295246","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295246","url":null,"abstract":"With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131744872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258176
S. Heng, C. Pham
A low-voltage and low-power consumption of current-mode operational amplifier designed with level shifter technique is presented. This simple integrator is built up with only 9 typical MOSFETs and 2 bias current sources. To minimize the influence of common-mode signal and noise to the signal processing, the differential structure is applied. As the result of simulation, it has been confirmed that the proposed circuit works as integrator in the frequency range 0-1.6MHz at 1.5V supply voltage and consumed DC power at maximum 8.85muW with 1.2mum double-poly CMOS process
{"title":"A 1.5V Current-Mode Operational Amplifier Using Level Shifter Technique","authors":"S. Heng, C. Pham","doi":"10.1109/VDAT.2006.258176","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258176","url":null,"abstract":"A low-voltage and low-power consumption of current-mode operational amplifier designed with level shifter technique is presented. This simple integrator is built up with only 9 typical MOSFETs and 2 bias current sources. To minimize the influence of common-mode signal and noise to the signal processing, the differential structure is applied. As the result of simulation, it has been confirmed that the proposed circuit works as integrator in the frequency range 0-1.6MHz at 1.5V supply voltage and consumed DC power at maximum 8.85muW with 1.2mum double-poly CMOS process","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258143
H. Shim, Sang-Heon Lee, Yun-Sik Woo, Moo-Kyoung Chung, Jae-Gon Lee, C. Kyung
This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test vectors, to verify RTL design. As there is no commercial simulation environment that can efficiently handle transaction-level and RTL models at the same time, we employed two simulators for each abstraction-level modeling. To translate abstraction levels of communication between the two simulators, we implemented transactor that is inserted between them. This paper shows the principle of operation of the transactor focusing on the synchronization between transaction-level simulator and RTL simulator. In addition, we replaced RTL simulator with hardware accelerator to improve simulation performance. We implemented wrapper for hiding access routines of hardware acceleration from transaction-level simulator which is attached to the above mentioned transactor
{"title":"Cycle-accurate Verification of AHB-based RTL IP with Transaction-level System Environment","authors":"H. Shim, Sang-Heon Lee, Yun-Sik Woo, Moo-Kyoung Chung, Jae-Gon Lee, C. Kyung","doi":"10.1109/VDAT.2006.258143","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258143","url":null,"abstract":"This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test vectors, to verify RTL design. As there is no commercial simulation environment that can efficiently handle transaction-level and RTL models at the same time, we employed two simulators for each abstraction-level modeling. To translate abstraction levels of communication between the two simulators, we implemented transactor that is inserted between them. This paper shows the principle of operation of the transactor focusing on the synchronization between transaction-level simulator and RTL simulator. In addition, we replaced RTL simulator with hardware accelerator to improve simulation performance. We implemented wrapper for hiding access routines of hardware acceleration from transaction-level simulator which is attached to the above mentioned transactor","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126433457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-01DOI: 10.1109/vdat.2006.258108
B. Thuillier
Summary form only given. Mobile phone baseband, power management unit and RF integration is an area of expanding interest within the semiconductor industry as it enables highly integrated solution and hence has the capability to address mobile phone fragmentation in ultra low cost, mid and high end areas. This paper presents the progress, limits and challenges of integration in relation with mobility. Some suggestions regarding potential directions are included. VLSI design, automation and testing progress may help to further improve new features integration flexibility, application speed and power consumption optimization
{"title":"VLSI & Mobility","authors":"B. Thuillier","doi":"10.1109/vdat.2006.258108","DOIUrl":"https://doi.org/10.1109/vdat.2006.258108","url":null,"abstract":"Summary form only given. Mobile phone baseband, power management unit and RF integration is an area of expanding interest within the semiconductor industry as it enables highly integrated solution and hence has the capability to address mobile phone fragmentation in ultra low cost, mid and high end areas. This paper presents the progress, limits and challenges of integration in relation with mobility. Some suggestions regarding potential directions are included. VLSI design, automation and testing progress may help to further improve new features integration flexibility, application speed and power consumption optimization","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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