Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258125
Chen-Yi Lee, Hsuan-Yu Liu, Chien-Ching Lin
Coded orthogonal frequency division multiplexing (COFDM) technology has been widely accepted in many communication systems due to both bandwidth efficiency and robustness to channel distortion. This opens a great of opportunities for SoC society to deal with design complexity by exploiting benefits of giga-scale integration. In this paper, we'll first review the general design concept of COFDM systems and then highlight several key issues in SoC realization. Then a system-level design flow by taking into account both performance indices and hardware complexity was introduced. Several core modules related to COFDM system were also addressed to see how better solutions can be achieved, especially for wireless applications. Finally two case studies on WLAN and OFDM-UWB were discussed to demonstrate our proposals as well as to provide some directions for further research
{"title":"SoC for COFDM Wireless Communications: Challenges and Opportunities","authors":"Chen-Yi Lee, Hsuan-Yu Liu, Chien-Ching Lin","doi":"10.1109/VDAT.2006.258125","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258125","url":null,"abstract":"Coded orthogonal frequency division multiplexing (COFDM) technology has been widely accepted in many communication systems due to both bandwidth efficiency and robustness to channel distortion. This opens a great of opportunities for SoC society to deal with design complexity by exploiting benefits of giga-scale integration. In this paper, we'll first review the general design concept of COFDM systems and then highlight several key issues in SoC realization. Then a system-level design flow by taking into account both performance indices and hardware complexity was introduced. Several core modules related to COFDM system were also addressed to see how better solutions can be achieved, especially for wireless applications. Finally two case studies on WLAN and OFDM-UWB were discussed to demonstrate our proposals as well as to provide some directions for further research","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123972258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258130
Shu-Hui Yen, Yo‐Sheng Lin
In this paper, we demonstrate a 1.2-to-17-GHz ultra-wideband (UWB) low-noise amplifier (LNA) with multiple feedback loops implemented in a 0.35 mum SiGe BiCMOS technology. A method named inductive peaking, which adds an inductor in series with the base terminal of the second stage BJT to enhance the frequency of the dominant pole, was adopted to improve gain and bandwidth of the LNA. The measurement results show very flat gain (S21) of 8plusmn0.5 dB was achieved for frequencies lower than 15 GHz. In addition, reverse isolation (S12 ) lower than -27 dB, input return loss (S11) and output return loss (S22) lower than -9 dB, and noise figure (NF) lower than 5.7 dB was achieved in the 3.1-10.6 GHz UWB band. The chip area was 775 mum times 710 mum, excluding the test pads. This LNA drains 7 mA current at supply voltage of 3 V, i.e. it only consumes 21 mW power
{"title":"Design and Implementation of a 1.2-to-17-GHz UWB SiGe LNA with a Peaking Inductor","authors":"Shu-Hui Yen, Yo‐Sheng Lin","doi":"10.1109/VDAT.2006.258130","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258130","url":null,"abstract":"In this paper, we demonstrate a 1.2-to-17-GHz ultra-wideband (UWB) low-noise amplifier (LNA) with multiple feedback loops implemented in a 0.35 mum SiGe BiCMOS technology. A method named inductive peaking, which adds an inductor in series with the base terminal of the second stage BJT to enhance the frequency of the dominant pole, was adopted to improve gain and bandwidth of the LNA. The measurement results show very flat gain (S21) of 8plusmn0.5 dB was achieved for frequencies lower than 15 GHz. In addition, reverse isolation (S12 ) lower than -27 dB, input return loss (S11) and output return loss (S22) lower than -9 dB, and noise figure (NF) lower than 5.7 dB was achieved in the 3.1-10.6 GHz UWB band. The chip area was 775 mum times 710 mum, excluding the test pads. This LNA drains 7 mA current at supply voltage of 3 V, i.e. it only consumes 21 mW power","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258177
M. B. Vahidfar, O. Shoaei, M. Fardis
A low power analog feedforward error equalizer (AFFE) is presented in this paper that cancels precursor inter symbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain is beneficial due to consuming lower power and silicon area comparing to digital forward equalizers. Moreover it leads to higher speed which is demanded for real time equalization and also less equalizer complexity. The proposed equalizer is a five tap discrete time filter which is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 42mW from a 1.8V supply. Each filter taps is implemented by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap. Moreover S/H power and speed requirements are relaxed by using redundant S/H's and additional clocking phase
提出了一种低功耗模拟前馈误差均衡器(AFFE)，用于消除千兆以太网双绞线接口前端的前驱码间干扰(ISI)。与数字前向均衡器相比，模拟域前向均衡器的功耗和硅面积更小，因此具有优势。此外，它还提高了实时均衡所需的速度，降低了均衡器的复杂度。所提出的均衡器是采用0.18 μ m CMOS技术设计的五分路离散时间滤波器。该设计工作频率为125MHz，功耗为42mW，来自1.8V电源。每个滤波器抽头由改进的吉尔伯特单元实现，而不是对滤波器抽头的每个位使用乘法器。此外，通过使用冗余S/H和额外的时钟相位，放宽了S/H功率和速度要求
{"title":"A Low Power, Transverse Analog FIR Filter as Feed Forward Equalizer in Gigabit Ethernet","authors":"M. B. Vahidfar, O. Shoaei, M. Fardis","doi":"10.1109/VDAT.2006.258177","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258177","url":null,"abstract":"A low power analog feedforward error equalizer (AFFE) is presented in this paper that cancels precursor inter symbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain is beneficial due to consuming lower power and silicon area comparing to digital forward equalizers. Moreover it leads to higher speed which is demanded for real time equalization and also less equalizer complexity. The proposed equalizer is a five tap discrete time filter which is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 42mW from a 1.8V supply. Each filter taps is implemented by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap. Moreover S/H power and speed requirements are relaxed by using redundant S/H's and additional clocking phase","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116821271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average
{"title":"A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling","authors":"Tsung-Chu Huang, J.-C. Tzeng, Yuan-Wei Chao, Ji-Jan Chen, Wei-Ting Liu, Kuen-Jong Lee","doi":"10.1109/VDAT.2006.258151","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258151","url":null,"abstract":"Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121013831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258162
Wei-Jen Huang, Sao-Hung Lu, Shen-Iuan Liu
A CMOS low dropout (LDO) regulator is presented to be stable for any load capacitor. A modified AC boosting technique is adapted in this regulator. Moreover, a slew rate enhancement circuit is presented to increase the slew rate and decrease the output voltage dips when a large load current is switched from 0 to 150mA. A 3.3V, 150mA, LDO regulator has been fabricated in a 0.35mum process
{"title":"A Capacitor-free CMOS Low Dropout Regulator with Slew Rate Enhancement","authors":"Wei-Jen Huang, Sao-Hung Lu, Shen-Iuan Liu","doi":"10.1109/VDAT.2006.258162","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258162","url":null,"abstract":"A CMOS low dropout (LDO) regulator is presented to be stable for any load capacitor. A modified AC boosting technique is adapted in this regulator. Moreover, a slew rate enhancement circuit is presented to increase the slew rate and decrease the output voltage dips when a large load current is switched from 0 to 150mA. A 3.3V, 150mA, LDO regulator has been fabricated in a 0.35mum process","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"446 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121332328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258165
H. Fredriksson, C. Svensson
This paper presents a mixed signal decision feedback equalizer (DFE) efficiently implementing sign-sign least-mean-square (SS-LMS) coefficient updating, offset estimation and compensation. The equalizer is designed for multi-drop buses and has 16 six bit fully programmable filter coefficients. The equalizer filter is implemented with a novel carry-save-DAC architecture eliminating the carry propagation limiting factor. Measurement results from a test chip are presented showing no transmission errors and good clock skew robustness when receiving data at 700 Mb/s over a heavily polluted channel. The test chip also includes bit error rate (BER) measurement circuits and equalized eye-chart extraction
{"title":"Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses","authors":"H. Fredriksson, C. Svensson","doi":"10.1109/VDAT.2006.258165","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258165","url":null,"abstract":"This paper presents a mixed signal decision feedback equalizer (DFE) efficiently implementing sign-sign least-mean-square (SS-LMS) coefficient updating, offset estimation and compensation. The equalizer is designed for multi-drop buses and has 16 six bit fully programmable filter coefficients. The equalizer filter is implemented with a novel carry-save-DAC architecture eliminating the carry propagation limiting factor. Measurement results from a test chip are presented showing no transmission errors and good clock skew robustness when receiving data at 700 Mb/s over a heavily polluted channel. The test chip also includes bit error rate (BER) measurement circuits and equalized eye-chart extraction","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116013024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258178
Yo‐Sheng Lin, Si-Chang Chen, Shu-Bin Chang
In this paper, a dual-transformer-feedback LNA architecture is proposed. One of the transformer-feedback is for reducing the supply voltage, the other is for improving the linearity of the LNA. A 1-V fully integrated dual-transformer-feedback LNA was implemented in standard 0.18 mum CMOS process to demonstrate the idea. The LNA exhibits voltage gain of 11.5 dB, input return loss (S11) of -11 dB, reverse isolation (S12) of -29.9 dB, NF of 2.65 dB, and IIP3 of 7 dBm at 2.4 GHz. The chip area is only 0.28 mm2, excluding the test pads. This LNA drains 15.3 mA current at supply voltage of 1 V, i.e. it consumes 15.3 mW power. Besides, a 1.2 V 5-GHz band transformer-feedback VCO was also implemented. The VCO exhibits tuning range of 165 MHz (5.449 - 5.614 GHz for Vtune = 0-0.7 V), phase noise of -97 dBc/Hz at 1 MHz offset from 5.6 GHz. The chip area is only 0.525 mm2, excluding the test pads. The VCO consumes 8.82 mW power
{"title":"Design and Implementation of a 1-V Dual-Transformer-Feedback LNA and a 5-GHz-Band Transformer-Feedback VCO","authors":"Yo‐Sheng Lin, Si-Chang Chen, Shu-Bin Chang","doi":"10.1109/VDAT.2006.258178","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258178","url":null,"abstract":"In this paper, a dual-transformer-feedback LNA architecture is proposed. One of the transformer-feedback is for reducing the supply voltage, the other is for improving the linearity of the LNA. A 1-V fully integrated dual-transformer-feedback LNA was implemented in standard 0.18 mum CMOS process to demonstrate the idea. The LNA exhibits voltage gain of 11.5 dB, input return loss (S11) of -11 dB, reverse isolation (S12) of -29.9 dB, NF of 2.65 dB, and IIP3 of 7 dBm at 2.4 GHz. The chip area is only 0.28 mm2, excluding the test pads. This LNA drains 15.3 mA current at supply voltage of 1 V, i.e. it consumes 15.3 mW power. Besides, a 1.2 V 5-GHz band transformer-feedback VCO was also implemented. The VCO exhibits tuning range of 165 MHz (5.449 - 5.614 GHz for Vtune = 0-0.7 V), phase noise of -97 dBc/Hz at 1 MHz offset from 5.6 GHz. The chip area is only 0.525 mm2, excluding the test pads. The VCO consumes 8.82 mW power","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125848776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258161
D. Sheng, Ching-Che Chung, Chen-Yi Lee
In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for system-on-chip (SoC) and system-level applications
{"title":"An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications","authors":"D. Sheng, Ching-Che Chung, Chen-Yi Lee","doi":"10.1109/VDAT.2006.258161","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258161","url":null,"abstract":"In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for system-on-chip (SoC) and system-level applications","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258154
S. Nazarian, Massoud Pedram
Conventional cell delay modeling approaches calculate the propagation delay and output transition time of a CMOS logic cell, which is subjected to a noisy input waveform, by approximating this noisy waveform with a saturated ramp signal and then utilizing cell library delay look-up tables to report the output timing information. Modeling the input waveform as a saturated ramp may however result in significant error in the timing parameters of interest because the actual output waveform can be very different from the one that is implied by a simple saturated ramp input. This paper therefore presents, gcdm, a gain-based cell delay modeling technique for accurate computation of the electrical output waveform of a CMOS logic cell under a noisy input waveform. The key contribution of gcdm is that it directly calculates the output waveform of the logic cell without the need to approximate the input waveform. In effect, gcdm requires a new pre-characterization process for each cell in the library, resulting in construction of a small-signal gain lookup table. This lookup table-based approach is compatible with the existing timing analysis tools. The high accuracy of our approach is confirmed by Spice simulations
{"title":"Gain-based Cell Delay Modeling","authors":"S. Nazarian, Massoud Pedram","doi":"10.1109/VDAT.2006.258154","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258154","url":null,"abstract":"Conventional cell delay modeling approaches calculate the propagation delay and output transition time of a CMOS logic cell, which is subjected to a noisy input waveform, by approximating this noisy waveform with a saturated ramp signal and then utilizing cell library delay look-up tables to report the output timing information. Modeling the input waveform as a saturated ramp may however result in significant error in the timing parameters of interest because the actual output waveform can be very different from the one that is implied by a simple saturated ramp input. This paper therefore presents, gcdm, a gain-based cell delay modeling technique for accurate computation of the electrical output waveform of a CMOS logic cell under a noisy input waveform. The key contribution of gcdm is that it directly calculates the output waveform of the logic cell without the need to approximate the input waveform. In effect, gcdm requires a new pre-characterization process for each cell in the library, resulting in construction of a small-signal gain lookup table. This lookup table-based approach is compatible with the existing timing analysis tools. The high accuracy of our approach is confirmed by Spice simulations","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133953067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258124
T. Hisakado, N. Kobayashi, S. Goto, T. Ikenaga, K. Higashi, I. Kitao, Y. Tsunoo
RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellular phone. This paper describes a RSA cryptography co-processor LSI. It can process up to 2048-bit key data, which is required to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 mum TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/O modules) have been integrated into a 2.2 times 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 2048-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems
{"title":"61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier","authors":"T. Hisakado, N. Kobayashi, S. Goto, T. Ikenaga, K. Higashi, I. Kitao, Y. Tsunoo","doi":"10.1109/VDAT.2006.258124","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258124","url":null,"abstract":"RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellular phone. This paper describes a RSA cryptography co-processor LSI. It can process up to 2048-bit key data, which is required to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 mum TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/O modules) have been integrated into a 2.2 times 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 2048-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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